** ) L: k3 K1 J4 S * @brief Clears the USARTx抯 interrupt pending bits., u' m) R5 s$ T8 n3 i* p
* @param USARTx: Select the USART peripheral. + ~- T/ _' c0 t- @4 [0 M * This parameter can be one of the following values: / f0 _3 Y8 x9 n1 C) b * USART1, USART2 or USART3.7 J5 J2 k" e. O( ]& n! Z
* @param USART_IT: specifies the interrupt pending bit to clear.; C g) D: q( K7 d( R7 _! o0 {5 q
* This parameter can be one of the following values: 1 O; D7 L+ V8 [7 a4 ~. N$ a: J * @arg USART_IT_CTS: CTS change interrupt8 c0 {& \ ~; _, y c' \2 s
* @arg USART_IT_LBD: LIN Break detection interrupt / F) V, W' X1 ]) I! f8 S* ?. v8 c * @arg USART_IT_TC: Transmission complete interrupt. 6 Y4 q8 y( D" I; }( y' t7 P9 ~ * @arg USART_IT_RXNE: Receive Data register not empty interrupt. * l* n. @( U6 r2 n- M/ H * 3 c5 N: ]/ ]( G- `2 x * @note 4 f% T# T5 A, w, D# U& t * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun : I. G+ {7 A% A! }' M7 j7 x% t
* error) and IDLE (Idle line detected) pending bits are cleared by & v% y0 N. {# z# T" F. | * software sequence: a read operation to USART_SR register . u$ R5 h0 X& A * (USART_GetITStatus()) followed by a read operation to USART_DR register % t) g6 `* j4 D * (USART_ReceiveData()). / r- `3 N& ^ Y4 F6 m, b/ a * - RXNE pending bit can be also cleared by a read to the USART_DR register & y2 M/ M$ f. @- H+ Y * (USART_ReceiveData()).
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RE:【原创教程】《零死角玩转STM32》初级/中级/高级/系统篇-480页PDF教程
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* @brief Clears the USARTx抯 interrupt pending bits., u' m) R5 s$ T8 n3 i* p
* @param USARTx: Select the USART peripheral.
* This parameter can be one of the following values:
* USART1, USART2 or USART3.7 J5 J2 k" e. O( ]& n! Z
* @param USART_IT: specifies the interrupt pending bit to clear.; C g) D: q( K7 d( R7 _! o0 {5 q
* This parameter can be one of the following values:
* @arg USART_IT_CTS: CTS change interrupt8 c0 {& \ ~; _, y c' \2 s
* @arg USART_IT_LBD: LIN Break detection interrupt
* @arg USART_IT_TC: Transmission complete interrupt.
* @arg USART_IT_RXNE: Receive Data register not empty interrupt.
*
* @note
* - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun : I. G+ {7 A% A! }' M7 j7 x% t
* error) and IDLE (Idle line detected) pending bits are cleared by
* software sequence: a read operation to USART_SR register
* (USART_GetITStatus()) followed by a read operation to USART_DR register
* (USART_ReceiveData()).
* - RXNE pending bit can be also cleared by a read to the USART_DR register
* (USART_ReceiveData()).
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