**4 }7 y6 q$ I8 o6 r9 R g: B
* @brief Clears the USARTx抯 interrupt pending bits.( B& u+ g0 s5 o2 w
* @param USARTx: Select the USART peripheral. 2 @4 V% p* V4 E! B" s * This parameter can be one of the following values: " c' u+ t. F6 u4 `9 ? * USART1, USART2 or USART3.3 T: m7 g3 `. y- _" ~: o
* @param USART_IT: specifies the interrupt pending bit to clear. * b z- n; J$ @; Z" x2 m. g * This parameter can be one of the following values: " J1 P0 H" \4 j/ Y) M% L0 g6 X * @arg USART_IT_CTS: CTS change interrupt + j0 v4 v( G4 T& Y$ J f8 M * @arg USART_IT_LBD: LIN Break detection interrupt3 }+ m$ K3 j9 ~) I$ u- @& \
* @arg USART_IT_TC: Transmission complete interrupt. 4 j5 [- y: r: o6 t) z. R
* @arg USART_IT_RXNE: Receive Data register not empty interrupt.7 @7 d, ^6 k4 I" `4 P/ o5 K" ?& F
* 0 t- V5 |3 a/ {7 Z * @note ) ?+ y0 V f9 C/ ? h7 a6 Q3 [ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun * l( T5 A+ x' o- a* @+ r
* error) and IDLE (Idle line detected) pending bits are cleared by . R+ Y2 v1 {% w1 S- x! h9 }, C * software sequence: a read operation to USART_SR register 6 m3 |/ f8 t" P; W4 P
* (USART_GetITStatus()) followed by a read operation to USART_DR register $ g- _) W: U! `3 H+ h6 z% t" S! l& q * (USART_ReceiveData()). $ p2 h1 \+ _# _ * - RXNE pending bit can be also cleared by a read to the USART_DR register 3 c5 [$ Q) G% U, ~ * (USART_ReceiveData()).
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RE:【原创教程】《零死角玩转STM32》初级/中级/高级/系统篇-480页PDF教程
RE:【原创教程】《零死角玩转STM32》初级/中级/高级/系统篇-480页PDF教程
* @brief Clears the USARTx抯 interrupt pending bits.( B& u+ g0 s5 o2 w
* @param USARTx: Select the USART peripheral.
* This parameter can be one of the following values:
* USART1, USART2 or USART3.3 T: m7 g3 `. y- _" ~: o
* @param USART_IT: specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg USART_IT_CTS: CTS change interrupt
* @arg USART_IT_LBD: LIN Break detection interrupt3 }+ m$ K3 j9 ~) I$ u- @& \
* @arg USART_IT_TC: Transmission complete interrupt. 4 j5 [- y: r: o6 t) z. R
* @arg USART_IT_RXNE: Receive Data register not empty interrupt.7 @7 d, ^6 k4 I" `4 P/ o5 K" ?& F
*
* @note
* - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun * l( T5 A+ x' o- a* @+ r
* error) and IDLE (Idle line detected) pending bits are cleared by
* software sequence: a read operation to USART_SR register 6 m3 |/ f8 t" P; W4 P
* (USART_GetITStatus()) followed by a read operation to USART_DR register
* (USART_ReceiveData()).
* - RXNE pending bit can be also cleared by a read to the USART_DR register
* (USART_ReceiveData()).
RE:【原创教程】《零死角玩转STM32》初级/中级/高级/系统篇-480页PDF教程
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