37.8.1 DWT functionalityThe processor watchpoints implement both data address and PC based watchpointfunctionality, a PC sampling register, and support comparator address masking, asdescribed in the **ARMv6-M Arm**.
37.8.2 DWT Program Counter Sample RegisterA processor that implements the data watchpoint unit also implements the ARMv6-Moptional **DWT Program Counter Sample Register **(DWT_PCSR). This register permits adebugger to periodically sample the PC without halting the processor. This provides coarsegrained profiling. See the **ARMv6-M Arm **for more information.The Cortex**®**-M0+ DWT_PCSR records both instructions that pass their condition codes andthose that fail
M0,M0+内核确定支持DWT吗?
先看看M0的手册
M0+手册
37.8 DWT (Data Watchpoint) The Cortex**®**-M0+ DWT implementation provides two watchpoint register sets.
37.8.1 DWT functionality The processor watchpoints implement both data address and PC based watchpoint functionality, a PC sampling register, and support comparator address masking, as described in the **ARMv6-M Arm**.
37.8.2 DWT Program Counter Sample Register A processor that implements the data watchpoint unit also implements the ARMv6-M optional **DWT Program Counter Sample Register **(DWT_PCSR). This register permits a debugger to periodically sample the PC without halting the processor. This provides coarse grained profiling. See the **ARMv6-M Arm **for more information. The Cortex**®**-M0+ DWT_PCSR records both instructions that pass their condition codes and those that fail