在库文件中，system_stm32f4xx.c文件里面有这么的代码：
# c; A' A: x& L" t, J5 U#ifdef DATA_IN_ExtSDRAM
/**
  * @brief  Setup the external memory controller.
% E( K0 k5 i8 F: y; ^% H  *         Called in startup_stm32f4xx.s before jump to main.
, A- ^1 j6 ~% n) m3 N* ^0 r( s. V  *         This function configures the external SDRAM mounted on STM324x9I_EVAL board
  *         This SDRAM will be used as program data memory (including heap and stack).
  * @param  None
  * @retval None
  */
void SystemInit_ExtMemCtl(void)
% L4 C' i6 g$ u8 p  S{
  register uint32_t tmpreg = 0, timeout = 0xFFFF;
  register uint32_t index;

  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
7 n$ ]: u/ S# t) ~7 b+ U* _* d      clock */
. \1 i! C5 D/ {0 R  RCC->AHB1ENR |= 0x000001FC;

  /* Connect PCx pins to FMC Alternate function */
  GPIOC->AFR[0]  = 0x0000000c;
2 P/ q: G# _/ W/ r9 a/ B  GPIOC->AFR[1]  = 0x00007700;
  /* Configure PCx pins in Alternate function mode */  
& V5 z3 h* s* ~2 }- a' d  GPIOC->MODER   = 0x00a00002;
  /* Configure PCx pins speed to 50 MHz */  
0 @/ n) `( w. f! ^  GPIOC->OSPEEDR = 0x00a00002;
) F  u# f- R+ C% d  /* Configure PCx pins Output type to push-pull */  
0 M& t9 a) R, g& b6 a8 g  GPIOC->OTYPER  = 0x00000000;
. S, S9 [/ D2 Q) q  /* No pull-up, pull-down for PCx pins */
1 p7 P* L4 S7 W( @  GPIOC->PUPDR   = 0x00500000;
7 L* c8 y/ U$ Q' X7 h7 c5 r
" [/ U$ ^; B# x2 ^  Z5 j' A" f5 h  /* Connect PDx pins to FMC Alternate function */
  GPIOD->AFR[0]  = 0x000000CC;
  GPIOD->AFR[1]  = 0xCC000CCC;
  /* Configure PDx pins in Alternate function mode */  
  GPIOD->MODER   = 0xA02A000A;
1 t" Y! l  m) c7 \  /* Configure PDx pins speed to 50 MHz */  
. X7 O" V* u% d4 h# L$ v9 m  GPIOD->OSPEEDR = 0xA02A000A;
  /* Configure PDx pins Output type to push-pull */  
7 _6 T4 B- I( ?7 i  GPIOD->OTYPER  = 0x00000000;
% r! D4 {( {: y' u3 ^  /* No pull-up, pull-down for PDx pins */
  GPIOD->PUPDR   = 0x00000000;

  /* Connect PEx pins to FMC Alternate function */
4 Z6 g, Y1 m  J# D! o* Y  GPIOE->AFR[0]  = 0xC00000CC;
( T7 s  z# h& x7 X' I( n, h  GPIOE->AFR[1]  = 0xCCCCCCCC;
1 m0 K) }7 `  ~& V) I  /* Configure PEx pins in Alternate function mode */
  GPIOE->MODER   = 0xAAAA800A;
( a, g  p$ H" X3 s7 b  /* Configure PEx pins speed to 50 MHz */
  GPIOE->OSPEEDR = 0xAAAA800A;
  /* Configure PEx pins Output type to push-pull */  
- I5 \: z& N  Q4 X# G: N+ H1 K8 p  F  GPIOE->OTYPER  = 0x00000000;
) `% Q+ t+ a, X/ \( q; [$ E  /* No pull-up, pull-down for PEx pins */
  GPIOE->PUPDR   = 0x00000000;
% A- e/ x) E3 f  H/ [6 E2 r/ o6 ~
  /* Connect PFx pins to FMC Alternate function */
$ ?# f; a* p$ K9 U  GPIOF->AFR[0]  = 0xcccccccc;
% x5 S- ?" V( F( t& f3 c  GPIOF->AFR[1]  = 0xcccccccc;
  /* Configure PFx pins in Alternate function mode */   
  GPIOF->MODER   = 0xAA800AAA;
  /* Configure PFx pins speed to 50 MHz */
5 W6 h* v% ^$ q) z9 g  k: ~' S, c  GPIOF->OSPEEDR = 0xAA800AAA;
, t8 E- A2 X4 J6 b& `5 H7 L" z, O  /* Configure PFx pins Output type to push-pull */  
  U, s& I8 B" \. ~9 V. s5 x& j* |/ v  GPIOF->OTYPER  = 0x00000000;
% s$ W0 C" k9 R+ y% Y# E3 @  /* No pull-up, pull-down for PFx pins */
. O3 L; {( u* i7 ?- x$ @, \  GPIOF->PUPDR   = 0x00000000;

6 U+ k! E& t/ P9 q  /* Connect PGx pins to FMC Alternate function */
  GPIOG->AFR[0]  = 0xcccccccc;
8 O- c2 g; [; H  GPIOG->AFR[1]  = 0xcccccccc;
' l& r( P6 H. C7 b8 y0 k  /* Configure PGx pins in Alternate function mode */
7 L6 l6 s) l6 b% w8 H( h  GPIOG->MODER   = 0xaaaaaaaa;
( w. F: P) o7 W! G% a  /* Configure PGx pins speed to 50 MHz */
  GPIOG->OSPEEDR = 0xaaaaaaaa;
  /* Configure PGx pins Output type to push-pull */  
  GPIOG->OTYPER  = 0x00000000;
  /* No pull-up, pull-down for PGx pins */
  GPIOG->PUPDR   = 0x00000000;

  /* Connect PHx pins to FMC Alternate function */
3 m" f$ u9 p. K; a' e: P  GPIOH->AFR[0]  = 0x00C0CC00;
# o+ G% V& T/ ^) u2 W$ P  GPIOH->AFR[1]  = 0xCCCCCCCC;
  u8 X" Y; k+ |  t3 r; q! k  /* Configure PHx pins in Alternate function mode */
  GPIOH->MODER   = 0xAAAA08A0;
  /* Configure PHx pins speed to 50 MHz */
  GPIOH->OSPEEDR = 0xAAAA08A0;
' }9 w+ m5 A# y# U7 [  /* Configure PHx pins Output type to push-pull */  
  GPIOH->OTYPER  = 0x00000000;
& A- m  s  a+ F+ v* G+ [3 A  /* No pull-up, pull-down for PHx pins */
4 x- O+ n  h* x+ S" w2 ^0 y  GPIOH->PUPDR   = 0x00000000;
- N# v5 Y; x, t) `5 N- l$ I
  /* Connect PIx pins to FMC Alternate function */
  GPIOI->AFR[0]  = 0xCCCCCCCC;
5 N. k7 A2 C; p/ E  GPIOI->AFR[1]  = 0x00000CC0;
  g# c) z) @$ f& ^4 i1 U3 Q8 @  /* Configure PIx pins in Alternate function mode */
4 ^3 i3 y* o6 D: X  GPIOI->MODER   = 0x0028AAAA;
  /* Configure PIx pins speed to 50 MHz */
! ^6 }+ P& D5 e9 m, a6 h0 {  GPIOI->OSPEEDR = 0x0028AAAA;
# x+ I! D# D5 h; h  /* Configure PIx pins Output type to push-pull */  
% ]( L- Q; g4 o( l$ N; e  GPIOI->OTYPER  = 0x00000000;
  /* No pull-up, pull-down for PIx pins */
6 }6 E- E4 x; x9 O5 p  GPIOI->PUPDR   = 0x00000000;

/*-- FMC Configuration ------------------------------------------------------*/
  ]) M1 I1 Z8 R* ~' n- T% o  /* Enable the FMC interface clock */
  RCC->AHB3ENR |= 0x00000001;
$ t" Q! d1 C( e3 d" E
  /* Configure and enable SDRAM bank1 */
. ~2 v$ z$ h+ S" E) J. f  FMC_Bank5_6->SDCR[0] = 0x000039D0;
  FMC_Bank5_6->SDTR[0] = 0x01115351;      
, G8 t) \. z- ^( e
  /* SDRAM initialization sequence */
  /* Clock enable command */
  FMC_Bank5_6->SDCMR = 0x00000011;
* ^7 J  @' B# Q" U7 Q  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
  while((tmpreg != 0) & (timeout-- > 0))
  {
# Y1 M( T5 h) P- U3 h    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
9 F! h& J4 |" c% @& c# g( p  }
1 ^: v& ~7 L) ^! e9 J1 e
  /* Delay */
5 N/ ~4 p+ _/ b) t/ b  x, P* Z1 S  for (index = 0; index<1000; index++);

  /* PALL command */
  FMC_Bank5_6->SDCMR = 0x00000012;           
3 k- o! H. c& l$ s* v7 W9 N' _" Q  timeout = 0xFFFF;
  while((tmpreg != 0) & (timeout-- > 0))
) V0 P" n# H7 n  \9 ]  {
0 G* Q" D8 C6 \# M" `" T  n  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
; e) i1 e- b. [' }  }

  /* Auto refresh command */
  FMC_Bank5_6->SDCMR = 0x00000073;
0 M1 i- R- E( u  timeout = 0xFFFF;
  while((tmpreg != 0) & (timeout-- > 0))
  {
" Z& c$ r4 N# @, p  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
' u" g/ Y. ?' W7 O. [& F  }

  /* MRD register program */
3 }. Z- e; t& G2 ]/ r7 t# \: h0 _, U  FMC_Bank5_6->SDCMR = 0x00046014;
  timeout = 0xFFFF;
  while((tmpreg != 0) & (timeout-- > 0))
7 z# @8 N8 H# f* o% T' q7 i  {
4 b5 z& R, D1 o# N  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
! g  a" ]/ W8 V, A. m  }
/ i9 I* a% E1 T. Z
2 f/ N! J9 D: r  /* Set refresh count */
. G9 l4 f! z- n  tmpreg = FMC_Bank5_6->SDRTR;
  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));

  /* Disable write protection */
" F6 _9 Y. Q' B: o- d" k  tmpreg = FMC_Bank5_6->SDCR[0];
  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
0 G5 x. T9 ]$ u3 K" _
% O/ z; a1 Q0 I! e) L7 `/*
  Bank1_SDRAM is configured as follow:

  FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;      
  FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6;  
0 x; z/ E5 Q) E: `4 R) l2 |  FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;        
  FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6;         
; M' @/ |0 X7 h. `$ P6 ?; [" [  FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;      
  FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;               
- Y* |6 \2 J$ k% q  FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;               
1 N' V0 w* V  N- ^# P( e
6 h8 p$ ?0 \. ?; S  FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK;
3 n* a! w/ d6 V  FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
  FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b;
  FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;
/ E( l$ t, m  ^* K, p8 l4 @: \  FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
0 h& B+ @! k" s& N' E( \; q3 a" N7 G  FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3;
4 P1 _# m% u5 {2 v  FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
6 S6 y9 g6 w* @# i  e& @' r  FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2;
; g5 g# M- m% f9 Q8 ?9 O  ]  FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable;
. K4 h$ E- A; X/ S* y( Y5 C; m  FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
% j% {2 K$ L4 X. f. y, [# N' L  FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
*/

( @+ j$ ?; K* v3 Z' X}
#endif /* DATA_IN_ExtSDRAM */
$ I1 V( s# ~; g( c+ A; v, m& R
0 b+ h8 a3 c9 ]/ t
# N; a$ f+ r; O$ `5 {很简单，说的就是如果你定义了这个宏，那么就给你初始化一下FMC使用的引脚。
我使用了F429 Discovery，在用SDRAM的时候，直接把SDRAM_Init中初始化引脚的代码删了，定义了一个宏DATA_IN_ExtSDRAM来完成初始化引脚的代码。但是当实验的时候却发现不行。
  W6 E- k8 X, B" W4 J2 l8 C最后好好查看了下system_stm32f4xx.c中的代码，也就是上面的代码，发现竟然没有初始化PB5，PB6两个引脚，也正是SDCKE1，SDNE1两个引脚。加上这两个引脚的初始化代码之后程序正常。
不知道为什么这里没有设置这两个引脚的模式。吐槽一下。希望用SDRAM的人不要挂在这个地方。
; ?4 r! B8 u! _4 G" b# m2 c1 A
* A$ ~  `: |# n* w: `

谢谢分享

帮你吐下

官方库有时是有点锉，版本变动一下subroutine 也跟着变动，不同的库编译出来的结果完全不一样。看你需求了其实自己写底层封装也不会太难。

楼主应该还在论坛
弱弱求个初始化代码，还有要怎么配置那个SDRAM作为数据内存？官方那个例程没跑通。。。

GPIOA GPIOB GPIOC 怎么加。。。我好像也遇到了这个问题