问题:在使用定时器输出PWM时,假如此时关闭PWM的输出,其IO口会出现高低电平交替出现的情况!1.代码设置:TIM2->CCER2寄存器设置的是输出使能和输出有效电平为低电平;' [, n9 \; V% P8 ~3 k- _% L# L' F
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- /* Disable the Channel 1: Reset the CCE Bit, Set the Output State, the Output Polarity(low) */
" Q6 f* q8 K- h: _# U) R) r. W7 ? - TIM2->CCER2 &= (uint8_t)(~( TIM2_CCER2_CC3E | TIM2_CCER2_CC3P));0 p1 J9 x) _3 ~( _) e! M2 `! D
- /* Set the Output State & Set the Output Polarity */
. ]! n% Z. u2 x6 W8 x - TIM2->CCER2 |= (uint8_t)((uint8_t)(0x11 & TIM2_CCER2_CC3E) | (uint8_t)(0x02 & TIM2_CCER2_CC3P));2 q O5 d* d" ]- c* i% a
- /* Reset the Output Compare Bits & Set the Output Compare Mode(PWM1) */5 q! {" \/ ^ [3 K: U3 s
- TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_OCM)) |<font color="#ff0000"> (uint8_t)0x60</font>);
复制代码 2.停止输出PWN:先使能定时器,然后强制输出为有效电平;1 I! ]3 v- C r3 d: J/ U1 N
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- /* Disable timer2 */
3 o! n0 |$ p- R& |, s; n7 e - TIM2->CR1 &= (uint8_t)(~TIM2_CR1_CEN);
2 M8 T5 W7 Q9 b1 g4 Z) ~ - /* Reset the OCM Bits & Configure the Forced output Mode */
# I/ L) ]& k! g% f% j - TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_OCM)) | <font color="#ff0000">(uint8_t)0x50</font>);
复制代码 3.重新启动定时器输出PWM:重新配置位输出PWM1模式,启动定时器
) J B e3 a' ^- L0 K- /* Reset the OCM Bits & Configure the Forced output Mode */
- A9 x2 j% r7 S8 r5 F) p6 ]: N - TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_OCM)) | <font color="#ff0000">(uint8_t)0x60</font>);: ~& @+ {' T/ Q; D: f! l5 g8 D
- TIM2->CR1 |= (uint8_t)TIM2_CR1_CEN; //产生pwm
复制代码 4.至于上面红色的设置关键字:* @6 g* v8 n# T6 L# I0 f
来自于stm8s参考手册TIMx_CCMR1
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