问题:在使用定时器输出PWM时,假如此时关闭PWM的输出,其IO口会出现高低电平交替出现的情况!1.代码设置:TIM2->CCER2寄存器设置的是输出使能和输出有效电平为低电平;
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- /* Disable the Channel 1: Reset the CCE Bit, Set the Output State, the Output Polarity(low) */
" X& K5 d8 a0 x8 M - TIM2->CCER2 &= (uint8_t)(~( TIM2_CCER2_CC3E | TIM2_CCER2_CC3P));& A( R1 w& S2 g8 p1 w5 S
- /* Set the Output State & Set the Output Polarity */1 F$ ^! f3 S! U# R7 c/ u1 N8 M
- TIM2->CCER2 |= (uint8_t)((uint8_t)(0x11 & TIM2_CCER2_CC3E) | (uint8_t)(0x02 & TIM2_CCER2_CC3P));. M0 t0 S3 k2 n$ k2 k. I
- /* Reset the Output Compare Bits & Set the Output Compare Mode(PWM1) */
- D' X# [/ ~9 d6 f - TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_OCM)) |<font color="#ff0000"> (uint8_t)0x60</font>);
复制代码 2.停止输出PWN:先使能定时器,然后强制输出为有效电平;$ V, A* W- o: U1 G8 f
6 x/ I* n7 {) j4 p" g+ I- /* Disable timer2 */
$ M" \" j8 o! E) n - TIM2->CR1 &= (uint8_t)(~TIM2_CR1_CEN); 6 w: T! r* W% z, l: A! m
- /* Reset the OCM Bits & Configure the Forced output Mode */
$ B% `: r3 y z5 K; G7 A- g) { - TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_OCM)) | <font color="#ff0000">(uint8_t)0x50</font>);
复制代码 3.重新启动定时器输出PWM:重新配置位输出PWM1模式,启动定时器7 |2 R; Y0 O& A$ O
- /* Reset the OCM Bits & Configure the Forced output Mode */
" a9 M: P1 Z. n4 h. ^' A, O- R& a4 w( i - TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_OCM)) | <font color="#ff0000">(uint8_t)0x60</font>);
3 s6 D. w+ D4 P3 c2 C; h$ A% w. u - TIM2->CR1 |= (uint8_t)TIM2_CR1_CEN; //产生pwm
复制代码 4.至于上面红色的设置关键字:
0 j9 T: H; A. `% M来自于stm8s参考手册TIMx_CCMR1
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