在cubeide中，用cubemx产生stm32g474re LL库的初始代码中，ADC1和ADC2配成独立工作，但是在MX_ADC2_Init(void)中，这两句是错的  LL_ADC_DisableDeepPowerDown(ADC1);
5 r) f# Z  i8 \  u  LL_ADC_EnableInternalRegulator(ADC1);

将导致ADC2不供电，无法工作，每次都要手工改过来才能正常工作。

* X/ a0 k2 G# o5 Y/ D
  * @brief ADC2 Initialization Function
  * @param None
; g; Z# P$ Z: I% M6 F" E5 {4 O1 G  * @retval None
9 ]6 {, O3 j# E' u  */
4 F, _& r) j# kstatic void MX_ADC2_Init(void)
6 _* z; [' d8 c* S% C' _{

0 ^4 {: Z' e$ O7 i7 T1 s  /* USER CODE BEGIN ADC2_Init 0 */
% ^& y0 a) Z5 J! G8 B+ p2 r
  /* USER CODE END ADC2_Init 0 */
# ?1 N3 R- h* {! G
  LL_ADC_InitTypeDef ADC_InitStruct = {0};
/ k9 _, q# p, K: e9 J  LL_ADC_REG_InitTypeDef ADC_REG_InitStruct = {0};
) A+ }7 O; H, W
# y' m. r7 P$ u* Q! ?$ L  /* Peripheral clock enable */
8 C. ]  ^9 v- b: W6 D! ?  {  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC12);

  /* ADC2 DMA Init */
' e: e% L" C9 a' t( N% L* c
+ K' V; g( `+ D, C, t/ h% z- Z3 S) G" K  /* ADC2 Init */
+ |2 A) H  h4 [; i/ x  LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMAMUX_REQ_ADC2);
) `7 ^1 R3 x& v. O  D0 z$ `
  LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_1, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);

4 W* n8 O% o+ i  LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PRIORITY_MEDIUM);

9 T! Q; {" `$ b$ {  LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MODE_NORMAL);

  LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PERIPH_NOINCREMENT);

4 N: R1 ^5 ?/ ]8 t! I  LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MEMORY_INCREMENT);
/ ^% ]7 E" w2 a3 H( I( @
  LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PDATAALIGN_WORD);

1 M7 p. o; E# X( w3 e1 K& N  LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MDATAALIGN_HALFWORD);

4 d! y6 _7 p, H3 `* o  /* USER CODE BEGIN ADC2_Init 1 */

$ A& @0 W# O, g3 |: P  /* USER CODE END ADC2_Init 1 */
" A6 P. Q3 s8 {5 {* }  /** Common config
  */
  ADC_InitStruct.Resolution = LL_ADC_RESOLUTION_12B;
  ADC_InitStruct.DataAlignment = LL_ADC_DATA_ALIGN_LEFT;
  ADC_InitStruct.LowPowerMode = LL_ADC_LP_MODE_NONE;
0 ?' o9 g6 q. H' T) t0 `1 O  LL_ADC_Init(ADC2, &ADC_InitStruct);
! N' y1 `1 v% N7 m  ADC_REG_InitStruct.TriggerSource = LL_ADC_REG_TRIG_EXT_TIM8_TRGO;
. h" U/ V1 z0 w/ }: D  ADC_REG_InitStruct.SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
) k* H0 p& R# Y9 |  ADC_REG_InitStruct.SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
, [/ R/ ]( `5 d* L/ |5 q( {$ d  ADC_REG_InitStruct.ContinuousMode = LL_ADC_REG_CONV_SINGLE;
7 w8 ~  f$ B9 H: H. ]) U3 }) @! J; f6 k  ADC_REG_InitStruct.DMATransfer = LL_ADC_REG_DMA_TRANSFER_UNLIMITED;
  ADC_REG_InitStruct.Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
  LL_ADC_REG_Init(ADC2, &ADC_REG_InitStruct);
  LL_ADC_SetGainCompensation(ADC2, 0);
  LL_ADC_SetOverSamplingScope(ADC2, LL_ADC_OVS_DISABLE);
  |; b% H! M: \! n( ^# ]6 D: ?+ E
& r/ \- T: ~4 P& x' O# R# Z! A# P" I) @  /* Disable ADC deep power down (enabled by default after reset state) */
  LL_ADC_DisableDeepPowerDown(ADC1);
  /* Enable ADC internal voltage regulator */
  LL_ADC_EnableInternalRegulator(ADC1);
: C1 _$ Y, s9 S8 {  /* Delay for ADC internal voltage regulator stabilization. */
  /* Compute number of CPU cycles to wait for, from delay in us. */
2 M# C1 e8 y$ W& c* k% N0 g  /* Note: Variable divided by 2 to compensate partially */
. m5 m0 a2 O6 F7 w  /* CPU processing cycles (depends on compilation optimization). */
  Y1 R' ]- ]! @1 r5 w  /* Note: If system core clock frequency is below 200kHz, wait time */
  /* is only a few CPU processing cycles. */

; `2 u- l6 p8 B7 _: m2 h: D3 a2 Y  uint32_t wait_loop_index;
  wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (100000 * 2))) / 10);
  while(wait_loop_index != 0)
  {
& a6 z' H0 @/ H; X% M9 p    wait_loop_index--;
  }
  LL_ADC_REG_SetTriggerEdge(ADC2, LL_ADC_REG_TRIG_EXT_RISING);
; h' l( I. U1 O5 z5 J' r/ F  /** Configure Regular Channel
  */
! _$ \! G% ~8 r/ r+ `7 l  LL_ADC_REG_SetSequencerRanks(ADC2, LL_ADC_REG_RANK_1, LL_ADC_CHANNEL_VOPAMP3_ADC2);
2 D4 C, n: x, ~/ k5 E# B  LL_ADC_SetChannelSamplingTime(ADC2, LL_ADC_CHANNEL_VOPAMP3_ADC2, LL_ADC_SAMPLINGTIME_6CYCLES_5);
. ^4 A  E; q! F4 L  LL_ADC_SetChannelSingleDiff(ADC2, LL_ADC_CHANNEL_VOPAMP3_ADC2, LL_ADC_SINGLE_ENDED);
2 W6 b0 l/ O6 y8 k  LL_ADC_SetOffset(ADC2, LL_ADC_OFFSET_1, LL_ADC_CHANNEL_VOPAMP3_ADC2, 0);
  LL_ADC_SetOffsetSign(ADC2, LL_ADC_OFFSET_1, LL_ADC_OFFSET_SIGN_NEGATIVE);
8 u/ v+ [. W! \- P  LL_ADC_SetOffsetSaturation(ADC2, LL_ADC_OFFSET_1, LL_ADC_OFFSET_SATURATION_DISABLE);
  /* USER CODE BEGIN ADC2_Init 2 */
, K) i. x8 I7 C4 T8 j+ A  LL_ADC_StartCalibration(ADC2, LL_ADC_SINGLE_ENDED);
  while (LL_ADC_IsCalibrationOnGoing(ADC2) != 0)  { };

  wait_loop_index = (ADC_DELAY_CALIB_ENABLE_CPU_CYCLES >> 1);
0 f' N; z/ S4 D2 h7 I6 L$ Y  while(wait_loop_index != 0)
  {
    wait_loop_index--;
# W% T* _( ^. ?0 i6 S$ q  }
* h/ Y5 H! Z6 I" _- V# |  /* Enable ADC */
  LL_ADC_Enable(ADC2);
  T6 V% _* z* m/ d) `# F+ ^& O
0 j0 `0 w# @7 h3 T  /* Poll for ADC ready to convert */
  while (LL_ADC_IsActiveFlag_ADRDY(ADC2) == 0)         { };

  /* USER CODE END ADC2_Init 2 */

* h% e; l, a6 E7 e# Y}