在cubeide中，用cubemx产生stm32g474re LL库的初始代码中，ADC1和ADC2配成独立工作，但是在MX_ADC2_Init(void)中，这两句是错的  LL_ADC_DisableDeepPowerDown(ADC1);
) k* |! d# q) s9 Q4 Y8 J; H  LL_ADC_EnableInternalRegulator(ADC1);
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将导致ADC2不供电，无法工作，每次都要手工改过来才能正常工作。


  * @brief ADC2 Initialization Function
1 B  N! `" c0 z& q3 a" V2 p& Q: n  * @param None
  * @retval None
& z+ A" M1 V- Y8 r  */
8 k) K  d9 L0 U9 ~, E$ a- Zstatic void MX_ADC2_Init(void)
7 n  m5 _, V$ u6 {% x{

/ x/ R7 g! l6 X) |  /* USER CODE BEGIN ADC2_Init 0 */

  /* USER CODE END ADC2_Init 0 */
' y! x4 f$ {1 u- r0 U5 }- ]% Q
" d* O. M7 H' _% J  LL_ADC_InitTypeDef ADC_InitStruct = {0};
% g& o6 ?* y% h! V" O/ B  P  LL_ADC_REG_InitTypeDef ADC_REG_InitStruct = {0};

7 Q) F: H* u2 A9 V  /* Peripheral clock enable */
  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC12);

  /* ADC2 DMA Init */

  /* ADC2 Init */
  LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMAMUX_REQ_ADC2);
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  LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_1, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);

' {  W- `" q! K7 C9 _# i  LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PRIORITY_MEDIUM);
$ a, K! Y0 A, ]
- }4 P8 Z( K) R7 ?. F* P% Y9 w9 i4 ^  LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MODE_NORMAL);
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- B/ u* m, {" n; h  LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PERIPH_NOINCREMENT);
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6 u' I- V# `: W7 r% a& B% \  LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MEMORY_INCREMENT);
; I8 c9 H" A- Q, e& N' }* {
/ h4 H# j5 i, x  `0 J( _. ?  LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PDATAALIGN_WORD);
( x; j( ^/ n" H3 ^. G2 V
( m$ ^) T' v" I' K  LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MDATAALIGN_HALFWORD);

: X/ c; N2 l1 G; G( s" @  /* USER CODE BEGIN ADC2_Init 1 */

  /* USER CODE END ADC2_Init 1 */
) ^$ q; n/ W# G# T/ t# f  /** Common config
7 v. L, A5 x6 b  */
  ADC_InitStruct.Resolution = LL_ADC_RESOLUTION_12B;
, U) r3 b' D: k% b0 c7 u! f$ ?) E# Z  ADC_InitStruct.DataAlignment = LL_ADC_DATA_ALIGN_LEFT;
  ADC_InitStruct.LowPowerMode = LL_ADC_LP_MODE_NONE;
  LL_ADC_Init(ADC2, &ADC_InitStruct);
3 M3 ?8 l" ~0 w& E% h+ w% C  ADC_REG_InitStruct.TriggerSource = LL_ADC_REG_TRIG_EXT_TIM8_TRGO;
( w) l! Y4 G; Q  V, S. k% c( D# I  ADC_REG_InitStruct.SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
, j; G1 E  X" v) R# Q  ADC_REG_InitStruct.SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
  ADC_REG_InitStruct.ContinuousMode = LL_ADC_REG_CONV_SINGLE;
; _6 e6 |% B" C4 [1 W9 V  ADC_REG_InitStruct.DMATransfer = LL_ADC_REG_DMA_TRANSFER_UNLIMITED;
  ADC_REG_InitStruct.Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
  LL_ADC_REG_Init(ADC2, &ADC_REG_InitStruct);
. R" E1 A% s& E9 s1 M  LL_ADC_SetGainCompensation(ADC2, 0);
8 R6 N8 _) a( K  d  LL_ADC_SetOverSamplingScope(ADC2, LL_ADC_OVS_DISABLE);

5 k9 p( ^+ |) ^% N# l. F( [  /* Disable ADC deep power down (enabled by default after reset state) */
  LL_ADC_DisableDeepPowerDown(ADC1);
0 t5 ~. ?- Z/ v; g0 E* \7 V9 S  /* Enable ADC internal voltage regulator */
  LL_ADC_EnableInternalRegulator(ADC1);
  /* Delay for ADC internal voltage regulator stabilization. */
  /* Compute number of CPU cycles to wait for, from delay in us. */
  /* Note: Variable divided by 2 to compensate partially */
1 _1 F7 |/ G5 K, x  /* CPU processing cycles (depends on compilation optimization). */
- K% o  G  P, E7 }4 `; v3 n+ d  /* Note: If system core clock frequency is below 200kHz, wait time */
  /* is only a few CPU processing cycles. */

9 J, |; p0 ?) c: `2 `  uint32_t wait_loop_index;
) O( R* N  ^4 ?) o, o) i; H6 @  wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (100000 * 2))) / 10);
  while(wait_loop_index != 0)
$ b0 p' f  Q7 }, \4 A7 k  {
9 t- ?+ x8 P/ ?: `    wait_loop_index--;
  }
  LL_ADC_REG_SetTriggerEdge(ADC2, LL_ADC_REG_TRIG_EXT_RISING);
  /** Configure Regular Channel
  */
  LL_ADC_REG_SetSequencerRanks(ADC2, LL_ADC_REG_RANK_1, LL_ADC_CHANNEL_VOPAMP3_ADC2);
  LL_ADC_SetChannelSamplingTime(ADC2, LL_ADC_CHANNEL_VOPAMP3_ADC2, LL_ADC_SAMPLINGTIME_6CYCLES_5);
  LL_ADC_SetChannelSingleDiff(ADC2, LL_ADC_CHANNEL_VOPAMP3_ADC2, LL_ADC_SINGLE_ENDED);
+ U  E, F3 d5 \2 u  r  LL_ADC_SetOffset(ADC2, LL_ADC_OFFSET_1, LL_ADC_CHANNEL_VOPAMP3_ADC2, 0);
, ?8 u. ]  \5 `* {  LL_ADC_SetOffsetSign(ADC2, LL_ADC_OFFSET_1, LL_ADC_OFFSET_SIGN_NEGATIVE);
7 N' J$ w  {, X$ l& k  LL_ADC_SetOffsetSaturation(ADC2, LL_ADC_OFFSET_1, LL_ADC_OFFSET_SATURATION_DISABLE);
  /* USER CODE BEGIN ADC2_Init 2 */
, T1 Y& [1 K/ ~; X% |0 i+ D$ J  LL_ADC_StartCalibration(ADC2, LL_ADC_SINGLE_ENDED);
  while (LL_ADC_IsCalibrationOnGoing(ADC2) != 0)  { };

: K& ~" G- o5 h8 {5 J  wait_loop_index = (ADC_DELAY_CALIB_ENABLE_CPU_CYCLES >> 1);
! @! C; W( q  a; S9 G  while(wait_loop_index != 0)
# m# @7 |6 Y3 j# F/ z  {
; U7 W+ E9 j- h; J: J$ @5 C! r0 F    wait_loop_index--;
4 D3 r$ D. P5 o$ ?  }
  /* Enable ADC */
  LL_ADC_Enable(ADC2);

- [' s* j1 t! r. y0 {% B  /* Poll for ADC ready to convert */
  while (LL_ADC_IsActiveFlag_ADRDY(ADC2) == 0)         { };
  }$ k* n) e5 {' E3 B
  /* USER CODE END ADC2_Init 2 */

% @6 @, J2 \9 q1 e; S& ~% Q" S" Q3 U}
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