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#include "stm8l15x.h" #include "NRF24l01P.h" /*********************************************************************/ #define IRQ (GPIOB->IDR & GPIO_Pin_2) #define MISO (GPIOB->IDR & GPIO_Pin_7) /*********************************************************************/ #define CE_0 GPIO_ResetBits(GPIOB, GPIO_Pin_3) #define CE_1 GPIO_SetBits(GPIOB, GPIO_Pin_3) #define CSN_0 GPIO_ResetBits(GPIOB, GPIO_Pin_4) #define CSN_1 GPIO_SetBits(GPIOB, GPIO_Pin_4) #define SCK_0 GPIO_ResetBits(GPIOB, GPIO_Pin_5) #define SCK_1 GPIO_SetBits(GPIOB, GPIO_Pin_5) #define MOSI_0 GPIO_ResetBits(GPIOB, GPIO_Pin_6) #define MOSI_1 GPIO_SetBits(GPIOB, GPIO_Pin_6) /*********************************************************************/ //unsigned char tx_buf[PAYLOAD_WIDTH]={0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08, // 0x09,0x10,0x11,0x12,0x13,0x14,0x15,0x16, // 0x17,0x18,0x19,0x20,0x21,0x22,0x23,0x24, // 0x25,0x26,0x27,0x28,0x29,0x30,0x31,0x32}; unsigned char TX_ADDRESS[ADDRESS_WIDTH] = {0xE7,0xE7,0xE7,0xE7,0x00}; unsigned char RX_ADDRESS0[ADDRESS_WIDTH] = {0xE7,0xE7,0xE7,0xE7,0x00}; unsigned char RX_ADDRESS1[ADDRESS_WIDTH] = {0xE7,0xE7,0xE7,0xE7,0x01}; unsigned char RX_ADDRESS2[1]= {0x02}; unsigned char RX_ADDRESS3[1]= {0x03}; unsigned char RX_ADDRESS4[1]= {0x04}; unsigned char RX_ADDRESS5[1]= {0x05}; /* nRF24L01 Instruction Definitions */ #define W_REGISTER 0x20 /**< Register write command */ #define R_RX_PAYLOAD 0x61 /**< Read RX payload command */ #define W_TX_PAYLOAD 0xA0 /**< Write TX payload command */ #define FLUSH_TX 0xE1 /**< Flush TX register command */ #define FLUSH_RX 0xE2 /**< Flush RX register command */ #define REUSE_TX_PL 0xE3 /**< Reuse TX payload command */ #define ACTIVATE 0x50 /**< Activate features */ #define R_RX_PL_WID 0x60 /**< Read RX payload command */ #define W_ACK_PAYLOAD 0xA8 /**< Write ACK payload command */ #define W_TX_PAYLOAD_NOACK 0xB0 /**< Write ACK payload command */ #define NOP 0xFF /**< No Operation command, used for reading status register */ /* nRF24L01 Register Definitions */ #define CONFIG 0x00 /**< nRF24L01 config register */ #define EN_AA 0x01 /**< nRF24L01 enable Auto-Acknowledge register */ #define EN_RXADDR 0x02 /**< nRF24L01 enable RX addresses register */ #define SETUP_AW 0x03 /**< nRF24L01 setup of address width register */ #define SETUP_RETR 0x04 /**< nRF24L01 setup of automatic retransmission register */ #define RF_CH 0x05 /**< nRF24L01 RF channel register */ #define RF_SETUP 0x06 /**< nRF24L01 RF setup register */ #define STATUS 0x07 /**< nRF24L01 status register */ #define OBSERVE_TX 0x08 /**< nRF24L01 transmit observe register */ #define CD 0x09 /**< nRF24L01 carrier detect register */ #define RX_ADDR_P0 0x0A /**< nRF24L01 receive address data pipe0 */ #define RX_ADDR_P1 0x0B /**< nRF24L01 receive address data pipe1 */ #define RX_ADDR_P2 0x0C /**< nRF24L01 receive address data pipe2 */ #define RX_ADDR_P3 0x0D /**< nRF24L01 receive address data pipe3 */ #define RX_ADDR_P4 0x0E /**< nRF24L01 receive address data pipe4 */ #define RX_ADDR_P5 0x0F /**< nRF24L01 receive address data pipe5 */ #define TX_ADDR 0x10 /**< nRF24L01 transmit address */ #define RX_PW_P0 0x11 /**< nRF24L01 \# of bytes in rx payload for pipe0 */ #define RX_PW_P1 0x12 /**< nRF24L01 \# of bytes in rx payload for pipe1 */ #define RX_PW_P2 0x13 /**< nRF24L01 \# of bytes in rx payload for pipe2 */ #define RX_PW_P3 0x14 /**< nRF24L01 \# of bytes in rx payload for pipe3 */ #define RX_PW_P4 0x15 /**< nRF24L01 \# of bytes in rx payload for pipe4 */ #define RX_PW_P5 0x16 /**< nRF24L01 \# of bytes in rx payload for pipe5 */ #define FIFO_STATUS 0x17 /**< nRF24L01 FIFO status register */ #define DYNPD 0x1C /**< nRF24L01 Dynamic payload setup */ #define FEATURE 0x1D /**< nRF24L01 Exclusive feature setup */ /** @name STATUS register bit definitions */ #define RX_DR 0x40 /**< STATUS register bit 6 */ #define TX_DS 0x20 /**< STATUS register bit 5 */ #define MAX_RT 0x10 /**< STATUS register bit 4 */ #define TX_FULL 0x01 /**< STATUS register bit 0 */ /** @name FIFO_STATUS register bit definitions */ #define TX_REUSE 0x40 /**< FIFO_STATUS register bit 6 */ #define TX_FIFO_FULL 0x20 /**< FIFO_STATUS register bit 5 */ #define TX_EMPTY 0x10 /**< FIFO_STATUS register bit 4 */ #define RX_FULL 0x02 /**< FIFO_STATUS register bit 1 */ #define RX_EMPTY 0x01 /**< FIFO_STATUS register bit 0 */ unsigned char SPI_SendByte(unsigned char byte) { unsigned char i; for(i = 0; i < 8; i++) { if (byte & 0x80) MOSI_1; else MOSI_0; byte <<= 1; SCK_1; if (MISO) byte++; SCK_0; } return byte; } unsigned char NRF24L01_WriteReg(unsigned char reg, unsigned char value) { unsigned char status; CSN_0; status = SPI_SendByte(reg); SPI_SendByte(value); CSN_1; return(status); } unsigned char NRF24L01_ReadReg(unsigned char reg) { unsigned char value; CSN_0; SPI_SendByte(reg); value = SPI_SendByte(0x00); CSN_1; return(value); } unsigned char NRF24L01_ReadBuf(unsigned char reg, unsigned char buf[], unsigned char len) { unsigned char i, status; CSN_0; status = SPI_SendByte(reg); for(i = 0; i < len; i++) buf[i] = SPI_SendByte(0x00); CSN_1; return(status); } unsigned char NRF24L01_WriteBuf(unsigned char reg, unsigned char buf[], unsigned char len) { unsigned char i, status; CSN_0; status = SPI_SendByte(reg); for(i = 0; i < len; i++) SPI_SendByte(buf[i]); CSN_1; return(status); } void NRF24L01_Initial(void) { GPIO_Init(GPIOB, GPIO_Pin_2 | GPIO_Pin_7, GPIO_Mode_In_FL_No_IT); GPIO_Init(GPIOB, GPIO_Pin_3 | GPIO_Pin_4 |GPIO_Pin_5 | GPIO_Pin_6, GPIO_Mode_Out_PP_Low_Fast); GPIO_Init(GPIOB, GPIO_Pin_2, GPIO_Mode_In_FL_IT); EXTI_SetPinSensitivity(EXTI_Pin_2, EXTI_Trigger_Falling);//NRF24L01P CE_0; CSN_1; SCK_0; NRF24L01_WriteReg(W_REGISTER + EN_AA, 0x01); NRF24L01_WriteReg(W_REGISTER + EN_RXADDR, 0x01); NRF24L01_WriteReg(W_REGISTER + SETUP_AW, 0x03); NRF24L01_WriteReg(W_REGISTER + SETUP_RETR, 0x1A); NRF24L01_WriteReg(W_REGISTER + RF_CH, 0); NRF24L01_WriteReg(W_REGISTER + RF_SETUP, 0x0C); //0x08:-18dBm,2Mbps //0x00:-18dBm,1Mbps NRF24L01_WriteBuf(W_REGISTER + RX_ADDR_P0, RX_ADDRESS0, ADDRESS_WIDTH); NRF24L01_WriteBuf(W_REGISTER + RX_ADDR_P1, RX_ADDRESS1, ADDRESS_WIDTH); NRF24L01_WriteBuf(W_REGISTER + RX_ADDR_P2, RX_ADDRESS2, 1); NRF24L01_WriteBuf(W_REGISTER + RX_ADDR_P3, RX_ADDRESS3, 1); NRF24L01_WriteBuf(W_REGISTER + RX_ADDR_P4, RX_ADDRESS4, 1); NRF24L01_WriteBuf(W_REGISTER + RX_ADDR_P5, RX_ADDRESS5, 1); NRF24L01_WriteBuf(W_REGISTER + TX_ADDR, TX_ADDRESS, ADDRESS_WIDTH); NRF24L01_WriteReg(W_REGISTER + RX_PW_P0, PAYLOAD_WIDTH); NRF24L01_WriteReg(W_REGISTER + RX_PW_P1, PAYLOAD_WIDTH); NRF24L01_WriteReg(W_REGISTER + RX_PW_P2, PAYLOAD_WIDTH); NRF24L01_WriteReg(W_REGISTER + RX_PW_P3, PAYLOAD_WIDTH); NRF24L01_WriteReg(W_REGISTER + RX_PW_P4, PAYLOAD_WIDTH); NRF24L01_WriteReg(W_REGISTER + RX_PW_P5, PAYLOAD_WIDTH); NRF24L01_WriteReg(FLUSH_RX, 0x00); NRF24L01_WriteReg(FLUSH_TX, 0x00); NRF24L01_WriteReg(W_REGISTER + STATUS, 0x70); NRF24L01_WriteReg(W_REGISTER + CONFIG, 0x00); } unsigned char NRF24L01_RxPacket(unsigned char rx_buf[]) { unsigned char status; NRF24L01_WriteReg(W_REGISTER + CONFIG, 0x0F); delay_ms(2); CE_1; //while(IRQ); delay_ms(10); CE_0; NRF24L01_WriteReg(W_REGISTER + CONFIG, 0x00); status = NRF24L01_ReadReg(STATUS); NRF24L01_WriteReg(W_REGISTER + STATUS, status); if(status & RX_DR) { NRF24L01_ReadBuf(R_RX_PAYLOAD, rx_buf, PAYLOAD_WIDTH); NRF24L01_WriteReg(FLUSH_RX, 0x00); return 1; } else { NRF24L01_WriteReg(FLUSH_RX, 0x00); return 0; } } unsigned char NRF24L01_TxPacket(unsigned char tx_buf[]) { unsigned char status; NRF24L01_WriteBuf(W_TX_PAYLOAD, tx_buf, PAYLOAD_WIDTH); NRF24L01_WriteReg(W_REGISTER + CONFIG, 0x0E); delay_ms(2); CE_1; //while(IRQ); delay_ms(10); CE_0; NRF24L01_WriteReg(W_REGISTER + CONFIG, 0x00); status = NRF24L01_ReadReg(STATUS); NRF24L01_WriteReg(W_REGISTER + STATUS, status); if(status & MAX_RT) { NRF24L01_WriteReg(FLUSH_TX, 0x00); return 0; } if(status & TX_DS) { NRF24L01_WriteReg(FLUSH_TX, 0x00); return 1; } return 2; } I |
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