STM32F4 使用HSI通过PLL提供SYSTEMCLOCK，程序跑飞

vlinda5150 提问时间：2015-10-30 16:25 /

使用HSI通过PLL提供SYSTEMCLOCK，下面代码每次执行到RCC->CFGR |= RCC_CFGR_SW_PLL;  程序就执行不下去了。求各位牛人帮忙看看问题出在哪里？
void SystemInit(void)
{
uint32_t tmp = 0;
  /* Reset the RCC clock configuration to the default reset state ------------*/
  /* Set HSION bit */
  RCC->CR |= (uint32_t)0x00000001;

  /* Reset CFGR register */
  RCC->CFGR = 0x00000000;

  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR &= (uint32_t)0xFEF6FFFF;

  /* Reset PLLCFGR register */
  RCC->PLLCFGR = 0x24003010;

  /* Reset HSEBYP bit */
  RCC->CR &= (uint32_t)0xFFFBFFFF;

  /* Disable all interrupts */
  RCC->CIR = 0x00000000;

#ifdef DATA_IN_ExtSRAM
  SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
//////////////////////////////////////////////////////////////////////////////////////////////////////
#ifdef PLL_SOURCE_HSI
  /* At this stage the HSI is already enabled */

/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
               (RCC_PLLCFGR_PLLSRC_HSI) | (PLL_Q << 24);

/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;

/* PCLK2 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;

/* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;

/* Enable the main PLL */
RCC->CR |= RCC_CR_PLLON;

/* Wait till the main PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}

/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
/* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= RCC_CFGR_SW_PLL;
tmp = (RCC->CFGR) & (uint32_t)RCC_CFGR_SWS;
/* Wait till the main PLL is used as system clock source */
while (tmp != RCC_CFGR_SWS_PLL)
{
   tmp = (RCC->CFGR) & (uint32_t)RCC_CFGR_SWS;
}
#else
  /* Configure the System clock source, PLL Multiplier and Divider factors,
   AHB/APBx prescalers and Flash settings ----------------------------------*/
  SetSysClock();
#endif /* PLL_SOURCE_HSI */
//////////////////////////////////////////////////////////////////////////////////////////////////////
  /* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}