一、下载源码
下载ThreadX系统源码。
https://github.com/eclipse-threadx/threadx
二、添加源码
2.1、将下载的源码中下面文件夹下有关的文件添加到项目中
2.2、添加文件到工程
三、代码
3.1、复制tx_initialize_low_level.S到项目中，并修改
修改如下：
// by default AzureRTOS is configured to use static byte pool for
// allocation, in case dynamic allocation is to be used, uncomment
// the define below and update the linker files to define the following symbols
// EWARM toolchain:
// place in RAM_region { last section FREE_MEM};
// MDK-ARM toolchain;
// either define the RW_IRAM1 region in the ".sct" file or modify this file by referring to the correct memory region.
// LDR r1, =|Image$$RW_IRAM1$$ZI$$Limit|
// STM32CubeIDE toolchain:
// ._threadx_heap :
// {
// . = ALIGN(8);
// __RAM_segment_used_end__ = .;
// . = . + 64K;
// . = ALIGN(8);
// } >RAM_D1 AT> RAM_D1
// The simplest way to provide memory for ThreadX is to define a new section, see ._threadx_heap above.
// In the example above the ThreadX heap size is set to 64KBytes.
// The ._threadx_heap must be located between the .bss and the ._user_heap_stack sections in the linker script.
// Caution: Make sure that ThreadX does not need more than the provided heap memory (64KBytes in this example).
// Read more in STM32CubeIDE User Guide, chapter: "Linker script".
//#define USE_DYNAMIC_MEMORY_ALLOCATION
#if defined(__clang__)
@/**************************************************************************/
@/* */
@/* Copyright (c) Microsoft Corporation. All rights reserved. */
@/* */
@/* This software is licensed under the Microsoft Software License */
@/* Terms for Microsoft Azure RTOS. Full text of the license can be */
@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
@/* and in the root directory of this software. */
@/* */
@/**************************************************************************/
@
@
@/**************************************************************************/
@/**************************************************************************/
@/** */
@/** ThreadX Component */
@/** */
@/** Initialize */
@/** */
@/**************************************************************************/
@/**************************************************************************/
@
@
.global _tx_thread_system_stack_ptr
.global _tx_initialize_unused_memory
.global _tx_thread_context_save
.global _tx_thread_context_restore
.global _tx_timer_interrupt
.global Image$$RW_IRAM1$$ZI$$Limit
.global __Vectors
@
@
SYSTEM_CLOCK = 48000000
SYSTICK_CYCLES = ((SYSTEM_CLOCK / 1000) -1)
.text
.align 4
.syntax unified
@/**************************************************************************/
@/* */
@/* FUNCTION RELEASE */
@/* */
@/* _tx_initialize_low_level Cortex-M0/AC6 */
@/* 6.1 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@/* */
@/* DESCRIPTION */
@/* */
@/* This function is responsible for any low-level processor */
@/* initialization, including setting up interrupt vectors, setting */
@/* up a periodic timer interrupt source, saving the system stack */
@/* pointer for use in ISR processing later, and finding the first */
@/* available RAM memory address for tx_application_define. */
@/* */
@/* INPUT */
@/* */
@/* None */
@/* */
@/* OUTPUT */
@/* */
@/* None */
@/* */
@/* CALLS */
@/* */
@/* None */
@/* */
@/* CALLED BY */
@/* */
@/* _tx_initialize_kernel_enter ThreadX entry function */
@/* */
@/* RELEASE HISTORY */
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* */
@/**************************************************************************/
@VOID _tx_initialize_low_level(VOID)
@{
.global _tx_initialize_low_level
.thumb_func
_tx_initialize_low_level:
@
@ /* Disable interrupts during ThreadX initialization. */
@
CPSID i
@
@ /* Set base of available memory to end of non-initialised RAM area. */
@
#ifdef USE_DYNAMIC_MEMORY_ALLOCATION
LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer
LDR r1, =Image$$RW_IRAM1$$ZI$$Limit @ Build first free address
ADDS r1, r1, #4 @
STR r1, [r0] @ Setup first unused memory pointer
#endif
@ /* Enable the cycle count register. */
@ /* Not all M0 have DWT, uncomment if you have a DWT and want to use it. */
@ LDR r0, =0xE0001000 @ Build address of DWT register
@ LDR r1, [r0] @ Pickup the current value
@ MOVS r2, #1
@ ORRS r1, r1, r2 @ Set the CYCCNTENA bit
@ STR r1, [r0] @ Enable the cycle count register
@
@ /* Setup Vector Table Offset Register. */
@
LDR r0, =0xE000E000 @ Build address of NVIC registers
LDR r2, =0xD08 @ Offset to vector base register
ADD r0, r0, r2 @ Build vector base register
LDR r1, =__Vectors @ Pickup address of vector table
STR r1, [r0] @ Set vector table address
@
@ /* Set system stack pointer from vector value. */
@
LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer
LDR r1, =__Vectors @ Pickup address of vector table
LDR r1, [r1] @ Pickup reset stack pointer
STR r1, [r0] @ Save system stack pointer
@
@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */
@
LDR r0, =0xE000E000 @ Build address of NVIC registers
LDR r1, =SYSTICK_CYCLES
STR r1, [r0, #0x14] @ Setup SysTick Reload Value
LDR r1, =0x7 @ Build SysTick Control Enable Value
STR r1, [r0, #0x10] @ Setup SysTick Control
@
@ /* Configure handler priorities. */
@
LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM
LDR r0, =0xE000E000 @ Build address of NVIC registers
LDR r2, =0xD18 @
ADD r0, r0, r2 @
STR r1, [r0] @ Setup System Handlers 4-7 Priority Registers
LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv
LDR r0, =0xE000E000 @ Build address of NVIC registers
LDR r2, =0xD1C @
ADD r0, r0, r2 @
STR r1, [r0] @ Setup System Handlers 8-11 Priority Registers
@ Note: SVC must be lowest priority, which is 0xFF
LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM
LDR r0, =0xE000E000 @ Build address of NVIC registers
LDR r2, =0xD20 @
ADD r0, r0, r2 @
STR r1, [r0] @ Setup System Handlers 12-15 Priority Registers
@ Note: PnSV must be lowest priority, which is 0xFF
@
@ /* Return to caller. */
@
BX lr
@}
@
@ /* System Tick timer interrupt handler */
.global __tx_SysTickHandler
.global SysTick_Handler
.thumb_func
__tx_SysTickHandler:
.thumb_func
SysTick_Handler:
@ VOID SysTick_Handler (VOID)
@ {
@
PUSH {r0, lr}
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
BL _tx_execution_isr_enter // Call the ISR enter function
#endif
BL _tx_timer_interrupt
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
BL _tx_execution_isr_exit // Call the ISR exit function
#endif
POP {r0, r1}
MOV lr, r1
BX lr
@ }
.end
#endif
#ifdef __IAR_SYSTEMS_ASM__
;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Initialize */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_initialize_unused_memory
EXTERN _tx_timer_interrupt
EXTERN __vector_table
EXTERN _tx_execution_isr_enter
EXTERN _tx_execution_isr_exit
;
;
SYSTEM_CLOCK EQU 48000000
SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1)
#ifdef USE_DYNAMIC_MEMORY_ALLOCATION
RSEG FREE_MEM:DATA
PUBLIC __tx_free_memory_start
__tx_free_memory_start
DS32 4
#endif
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level Cortex-M0/IAR */
;/* 6.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is responsible for any low-level processor */
;/* initialization, including setting up interrupt vectors, setting */
;/* up a periodic timer interrupt source, saving the system stack */
;/* pointer for use in ISR processing later, and finding the first */
;/* available RAM memory address for tx_application_define. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* */
;/**************************************************************************/
;VOID _tx_initialize_low_level(VOID)
;{
PUBLIC _tx_initialize_low_level
_tx_initialize_low_level:
;
; /* Ensure that interrupts are disabled. */
;
CPSID i ; Disable interrupts
;
;
; /* Set base of available memory to end of non-initialised RAM area. */
;
#ifdef USE_DYNAMIC_MEMORY_ALLOCATION
LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area
LDR r2, =_tx_initialize_unused_memory ; Build address of unused memory pointer
STR r0, [r2, #0] ; Save first free memory address
#endif
;
; /* Enable the cycle count register. */
; /* Not all M0 have DWT, uncomment if you have a DWT and want to use it. */
; LDR r0, =0xE0001000 ; Build address of DWT register
; LDR r1, [r0] ; Pickup the current value
; MOVS r2, #1
; ORRS r1, r1, r2 ; Set the CYCCNTENA bit
; STR r1, [r0] ; Enable the cycle count register
;
; /* Setup Vector Table Offset Register. */
;
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD08 ; Offset to vector base register
ADD r0, r0, r2 ; Build vector base register
LDR r1, =__vector_table ; Pickup address of vector table
STR r1, [r0] ; Set vector table address
;
; /* Set system stack pointer from vector value. */
;
LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer
LDR r1, =__vector_table ; Pickup address of vector table
LDR r1, [r1] ; Pickup reset stack pointer
STR r1, [r0] ; Save system stack pointer
;
; /* Configure SysTick. */
;
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r1, =SYSTICK_CYCLES
STR r1, [r0, #0x14] ; Setup SysTick Reload Value
MOVS r1, #0x7 ; Build SysTick Control Enable Value
STR r1, [r0, #0x10] ; Setup SysTick Control
;
; /* Configure handler priorities. */
;
LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD18 ;
ADD r0, r0, r2 ;
STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers
LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD1C ;
ADD r0, r0, r2 ;
STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers
; Note: SVC must be lowest priority, which is 0xFF
LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD20 ;
ADD r0, r0, r2 ;
STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers
; Note: PnSV must be lowest priority, which is 0xFF
;
; /* Return to caller. */
;
BX lr
;}
;
;
PUBLIC SysTick_Handler
PUBLIC __tx_SysTickHandler
__tx_SysTickHandler:
SysTick_Handler:
; VOID SysTick_Handler (VOID)
; {
;
PUSH {r0, lr}
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
BL _tx_execution_isr_enter // Call the ISR enter function
#endif
BL _tx_timer_interrupt
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
BL _tx_execution_isr_exit // Call the ISR exit function
#endif
POP {r0, r1}
MOV lr, r1
BX lr
; }
END
#endif
#ifdef __GNUC__
@/**************************************************************************/
@/* */
@/* Copyright (c) Microsoft Corporation. All rights reserved. */
@/* */
@/* This software is licensed under the Microsoft Software License */
@/* Terms for Microsoft Azure RTOS. Full text of the license can be */
@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
@/* and in the root directory of this software. */
@/* */
@/**************************************************************************/
@
@
@/**************************************************************************/
@/**************************************************************************/
@/** */
@/** ThreadX Component */
@/** */
@/** Initialize */
@/** */
@/**************************************************************************/
@/**************************************************************************/
@
@
.global _tx_thread_system_stack_ptr
.global _tx_initialize_unused_memory
.global __RAM_segment_used_end__
.global _tx_timer_interrupt
.global __main
.global __tx_SVCallHandler
.global __tx_PendSVHandler
.global _vectors
.global __tx_NMIHandler @ NMI
.global __tx_BadHandler @ HardFault
.global __tx_SVCallHandler @ SVCall
.global __tx_DBGHandler @ Monitor
.global __tx_PendSVHandler @ PendSV
.global __tx_SysTickHandler @ SysTick
.global __tx_IntHandler @ Int 0
@
@
SYSTEM_CLOCK = 48000000
SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
.text 32
.align 4
.syntax unified
@/**************************************************************************/
@/* */
@/* FUNCTION RELEASE */
@/* */
@/* _tx_initialize_low_level Cortex-M0/GNU */
@/* 6.1 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@/* */
@/* DESCRIPTION */
@/* */
@/* This function is responsible for any low-level processor */
@/* initialization, including setting up interrupt vectors, setting */
@/* up a periodic timer interrupt source, saving the system stack */
@/* pointer for use in ISR processing later, and finding the first */
@/* available RAM memory address for tx_application_define. */
@/* */
@/* INPUT */
@/* */
@/* None */
@/* */
@/* OUTPUT */
@/* */
@/* None */
@/* */
@/* CALLS */
@/* */
@/* None */
@/* */
@/* CALLED BY */
@/* */
@/* _tx_initialize_kernel_enter ThreadX entry function */
@/* */
@/* RELEASE HISTORY */
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 Scott Larson Modified comment(s), and */
@/* commented out code for */
@/* enabling DWT, */
@/* resulting in version 6.1 */
@/* */
@/**************************************************************************/
@VOID _tx_initialize_low_level(VOID)
@{
.global _tx_initialize_low_level
.thumb_func
_tx_initialize_low_level:
@
@ /* Disable interrupts during ThreadX initialization. */
@
CPSID i
@
@ /* Set base of available memory to end of non-initialised RAM area. */
@
#ifdef USE_DYNAMIC_MEMORY_ALLOCATION
LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer
LDR r1, =__RAM_segment_used_end__ @ Build first free address
ADDS r1, r1, #4 @
STR r1, [r0] @ Setup first unused memory pointer
#endif
@
@ /* Enable the cycle count register. */
@ /* Not all M0 have DWT, uncomment if you have a DWT and want to use it. */
@ LDR r0, =0xE0001000 @ Build address of DWT register
@ LDR r1, [r0] @ Pickup the current value
@ MOVS r2, #1
@ ORRS r1, r1, r2 @ Set the CYCCNTENA bit
@ STR r1, [r0] @ Enable the cycle count register
@
@ /* Setup Vector Table Offset Register. */
@
LDR r0, =0xE000E000 @ Build address of NVIC registers
LDR r2, =0xD08 @ Offset to vector base register
ADD r0, r0, r2 @ Build vector base register
LDR r1, =g_pfnVectors @ Pickup address of vector table
STR r1, [r0] @ Set vector table address
@
@ /* Set system stack pointer from vector value. */
@
LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer
LDR r1, =g_pfnVectors @ Pickup address of vector table
LDR r1, [r1] @ Pickup reset stack pointer
STR r1, [r0] @ Save system stack pointer
@
@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */
@
LDR r0, =0xE000E000 @ Build address of NVIC registers
LDR r1, =SYSTICK_CYCLES
STR r1, [r0, #0x14] // Setup SysTick Reload Value
LDR r1, =0x7 // Build SysTick Control Enable Value
STR r1, [r0, #0x10] // Setup SysTick Control
/* Configure handler priorities. */
LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM
LDR r0, =0xE000E000 // Build address of NVIC registers
LDR r2, =0xD18 //
ADD r0, r0, r2 //
STR r1, [r0] // Setup System Handlers 4-7 Priority Registers
LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv
LDR r0, =0xE000E000 // Build address of NVIC registers
LDR r2, =0xD1C //
ADD r0, r0, r2 //
STR r1, [r0] // Setup System Handlers 8-11 Priority Registers
// Note: SVC must be lowest priority, which is 0xFF
LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM
LDR r0, =0xE000E000 // Build address of NVIC registers
LDR r2, =0xD20 //
ADD r0, r0, r2 //
STR r1, [r0] // Setup System Handlers 12-15 Priority Registers
// Note: PnSV must be lowest priority, which is 0xFF
/* Return to caller. */
BX lr
// }
/* Define shells for each of the unused vectors. */
.global __tx_BadHandler
.thumb_func
__tx_BadHandler:
B __tx_BadHandler
/* added to catch the hardfault */
.global __tx_HardfaultHandler
.thumb_func
__tx_HardfaultHandler:
B __tx_HardfaultHandler
/* Generic interrupt handler template */
.global __tx_IntHandler
.thumb_func
__tx_IntHandler:
// VOID InterruptHandler (VOID)
// {
PUSH {r0, lr}
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
BL _tx_execution_isr_enter // Call the ISR enter function
#endif
/* Do interrupt handler work here */
/* BL <your C Function>.... */
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
BL _tx_execution_isr_exit // Call the ISR exit function
#endif
POP {r0, r1}
MOV lr, r1
BX lr
// }
/* System Tick timer interrupt handler */
.global __tx_SysTickHandler
.global SysTick_Handler
.thumb_func
__tx_SysTickHandler:
.thumb_func
SysTick_Handler:
// VOID SysTick_Handler (VOID)
// {
PUSH {r0, lr}
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
BL _tx_execution_isr_enter // Call the ISR enter function
#endif
BL _tx_timer_interrupt
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
BL _tx_execution_isr_exit // Call the ISR exit function
#endif
POP {r0, r1}
MOV lr, r1
BX lr
// }
/* NMI, DBG handlers */
.global __tx_NMIHandler
.thumb_func
__tx_NMIHandler:
B __tx_NMIHandler
.global __tx_DBGHandler
.thumb_func
__tx_DBGHandler:
B __tx_DBGHandler
#endif
3.3、tim.c
#include "main.h"
TIM_HandleTypeDef htim17;
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock = 0;
uint32_t uwPrescalerValue = 0;
uint32_t pFLatency;
/*Configure the TIM17 IRQ priority */
HAL_NVIC_SetPriority(TIM17_IRQn, TickPriority ,0);
/* Enable the TIM17 global Interrupt */
HAL_NVIC_EnableIRQ(TIM17_IRQn);
/* Enable TIM17 clock */
__HAL_RCC_TIM17_CLK_ENABLE();
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
/* Compute TIM17 clock */
uwTimclock = HAL_RCC_GetPCLK1Freq();
/* Compute the prescaler value to have TIM17 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
/* Initialize TIM17 */
htim17.Instance = TIM17;
/* Initialize TIMx peripheral as follow:
+ Period = [(TIM17CLK/1000) - 1]. to have a (1/1000) s time base.
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+ ClockDivision = 0
+ Counter direction = Up
*/
htim17.Init.Period = (1000000U / 1000U) - 1U;
htim17.Init.Prescaler = uwPrescalerValue;
htim17.Init.ClockDivision = 0;
htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
if(HAL_TIM_Base_Init(&htim17) == HAL_OK)
{
/* Start the TIM time Base generation in interrupt mode */
return HAL_TIM_Base_Start_IT(&htim17);
}
/* Return function status */
return HAL_ERROR;
}
void HAL_SuspendTick(void)
{
/* Disable TIM17 update Interrupt */
__HAL_TIM_DISABLE_IT(&htim17, TIM_IT_UPDATE);
}
void HAL_ResumeTick(void)
{
/* Enable TIM17 Update interrupt */
__HAL_TIM_ENABLE_IT(&htim17, TIM_IT_UPDATE);
}
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
if (htim->Instance == TIM17) {
HAL_IncTick();
}
}
3.4、stm32c0xx_it.c
在stm32c0xx_it.c文件中增加以下内容
#include "main.h"
//#include "stm32c0xx_it.h"
extern TIM_HandleTypeDef htim17;
void TIM17_IRQHandler(void)
{
HAL_TIM_IRQHandler(&htim17);
}
3.5、fun_task.c
#include "main.h"
#define APP_TASK1_STACK_SIZE 128
#define APP_TASK1_THREAD_PRIO 6
#define APP_TASK1_THREAD_PREEMPTION_THRESHOLD APP_TASK1_THREAD_PRIO
#define APP_TASK2_STACK_SIZE 256
#define APP_TASK2_THREAD_PRIO 7
#define APP_TASK2_THREAD_PREEMPTION_THRESHOLD APP_TASK2_THREAD_PRIO
TX_THREAD app_thread_task1;
TX_THREAD app_thread_task2;
void thread_entry_task1(ULONG thread_input)
{
(void) thread_input;
while(1)
{
printf("task1..\r\n");
led4_tog();
tx_thread_sleep(100);
}
}
void thread_entry_task2(ULONG thread_input)
{
(void) thread_input;
while(1)
{
printf("task2..\r\n");
tx_thread_sleep(200);
}
}
UINT task_create(VOID *memory_ptr)
{
UINT ret = TX_SUCCESS;
TX_BYTE_POOL *byte_pool = (TX_BYTE_POOL*)memory_ptr;
CHAR *pointer;
if (tx_byte_allocate(byte_pool, (VOID**) &pointer,APP_TASK1_STACK_SIZE, TX_NO_WAIT) != TX_SUCCESS)
{
return TX_POOL_ERROR;
}
if (tx_thread_create(&app_thread_task1, "thread_entry_led", thread_entry_task1, 0, pointer, APP_TASK1_STACK_SIZE,
APP_TASK1_THREAD_PRIO, APP_TASK1_THREAD_PREEMPTION_THRESHOLD,
TX_NO_TIME_SLICE, TX_AUTO_START) != TX_SUCCESS)
{
ret = TX_THREAD_ERROR;
}
if (tx_byte_allocate(byte_pool, (VOID**) &pointer,APP_TASK2_STACK_SIZE, TX_NO_WAIT) != TX_SUCCESS)
{
return TX_POOL_ERROR;
}
if (tx_thread_create(&app_thread_task2, "thread_entry_task2", thread_entry_task2, 0, pointer, APP_TASK2_STACK_SIZE,
APP_TASK2_THREAD_PRIO, APP_TASK2_THREAD_PREEMPTION_THRESHOLD,
TX_NO_TIME_SLICE, TX_AUTO_START) != TX_SUCCESS)
{
ret = TX_THREAD_ERROR;
}
return ret;
}
3.6、main.c
#include "main.h"
void SystemClock_Config(void);
int main(void)
{
HAL_Init();
/* Configure the system clock */
SystemClock_Config();
init_led();
init_usart(115200);
tx_kernel_enter();
while (1)
{
}
}
四、程序运行
编译下载后，复位开发板，串口输出
