【经验分享】STM32 时钟相关函数和类型

[复制链接]

STMCU小助手发布时间：2022-6-10 20:14

技术帖
文章封面:
文章简介:	STM32 时钟相关函数和类型

01. 概述
在 STM32F4 标准固件库里，时钟源的选择以及时钟使能等函数都是在 RCC 相关固件库文件 stm32f4xx_rcc.h 和 stm32f4xx_rcc.c 中声明和定义的。大家打开 stm32f4xx_rcc.h 文件可以看到文件开头有很多宏定义标识符，然后是一系列时钟配置和时钟使能函数申明。这些函数大致可以归结为三类，一类是外设时钟使能函数，一类是时钟源和分频因子配置函数，还有一类是外设复位函数。当然还有几个获取时钟源配置的函数。

02. 相关类型
RCC_ClocksTypeDef

/* Exported types ------------------------------------------------------------*/
# d0 t1 q! D7 C; |# e+ W- V' e# D
typedef struct
% M+ g; I& c/ n e
{( S. v$ O- U( F7 j( f1 |3 K
uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ G' Z6 e) q) R& i1 l9 |) K
uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
' N8 E! o0 q1 S2 O! u. h
uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */2 ^0 W2 `" Z% T7 q
uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
6 o: e/ L; {, T4 ?4 g- B9 }9 m
}RCC_ClocksTypeDef;

复制代码

RCC_HSE_configuration

/** @defgroup RCC_HSE_configuration
0 q1 r, p% P+ y: W- N
* @{
; W5 W& U4 _ X- u
*/& ?, X0 S; i( Q3 d0 O
#define RCC_HSE_OFF ((uint8_t)0x00)
7 u& f- L- u( y3 r9 x
#define RCC_HSE_ON ((uint8_t)0x01)% C. m, W3 Q* M8 s% ^ R
#define RCC_HSE_Bypass ((uint8_t)0x05)
8 f9 o& Z- h4 n, o8 `! D
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \% {* j6 o' Y3 J) y" ^
((HSE) == RCC_HSE_Bypass))
5 g4 v/ i8 ^. A; j8 p

复制代码

RCC_LSE_Dual_Mode_Selection

/** @defgroup RCC_LSE_Dual_Mode_Selection) W1 Y# I5 Q% e+ T5 h
* @{
9 [3 Y g" y: r( \
*/
/ b3 ]- o g; X" W# ?2 w* n
#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
2 Q) r: Q$ g. R
#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)8 b) X; D9 ~. H+ y
#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \( K6 o- C! H2 b, v% X8 Y8 ], r
((MODE) == RCC_LSE_HIGHDRIVE_MODE))

复制代码

RCC_PLLSAIDivR_Factor

/** @defgroup RCC_PLLSAIDivR_Factor
5 o5 Q* G' L' ]: f
* @{
+ |6 o* ?+ G% {+ m" Z; @
*/
1 w2 G9 \% \; U2 E7 u
#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)0 i) ~- ]/ K" T; \. e8 a5 _
#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)2 M3 o4 V* c2 n' N' k/ m |+ b. D
#define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000), A7 E# O7 c c- V K3 F$ k
#define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)
: r8 M( n* N* B; u, ]
#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\4 R+ O3 _, e7 T0 e% K
((VALUE) == RCC_PLLSAIDivR_Div4) ||\, r# t7 e5 ]+ C# E @2 p& E5 v
((VALUE) == RCC_PLLSAIDivR_Div8) ||\
. A' K9 {1 v6 _+ [$ _, j
((VALUE) == RCC_PLLSAIDivR_Div16))+ M( j( [! E, S( \: C

复制代码

3 F. t) @% o3 T% |RCC_PLL_Clock_Source

/** @defgroup RCC_PLL_Clock_Source $ p {& n0 t; J$ n1 n+ f
* @{
5 K" O8 ~2 U' ^0 {. p# p
*/ }3 C* v4 A- `9 C$ k0 W
#define RCC_PLLSource_HSI ((uint32_t)0x00000000)' z0 k: {' W6 @2 z( o! X$ u
#define RCC_PLLSource_HSE ((uint32_t)0x00400000)' K6 a" {" y3 P0 c7 h6 Y% c: |
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
. R3 Q3 V O& _, b1 P4 ]
((SOURCE) == RCC_PLLSource_HSE))
% o* k9 d& F$ s8 \" f
#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) @9 I( r A5 s# Y/ n1 r3 v+ s
#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
& [& Q. {- f& [; M1 F
#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) ||
) J( ^% V. |0 B9 L
((VALUE) == 6) || ((VALUE) == 8))3 r/ e" m8 W* n9 c3 l9 G9 F4 a
#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
* m% p7 D3 `5 ]0 p! n0 f
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
8 Y$ a( P1 q4 C7 X' w3 _. d) M
|| defined(STM32F446xx) || defined(STM32F469_479xx)
) \$ T' j" n0 F5 c
#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))3 H4 O4 E. Z: V$ d6 v: X
#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx & h/ D$ h9 e2 q8 A4 Z
|| STM32F469_479xx */
8 u z @3 S- ]# O" s: @$ g
P1 D# b2 v: V
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))* D1 p" }4 X: i6 }# L
#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))" M6 y5 ]; Y* `: o1 \
#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
g0 H' P1 {2 _3 B
#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))2 d# `9 H9 D& [. Q4 d
#if defined(STM32F446xx)
. O+ P& T4 ^1 ?7 G3 ]
#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4)
' M& V" b9 b2 c, W8 I
|| ((VALUE) == 6) || ((VALUE) == 8))) \ u9 z9 `7 k9 X# l. }. N1 A4 O
#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
0 G( R j, G; P7 F7 |
#elif defined(STM32F412xG) || defined(STM32F413_423xx)
! Z/ x" |# f( ^, w5 N l
#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) 1 D7 H+ O9 p" f4 Q
|| ((VALUE) == 6) || ((VALUE) == 8))
9 }" X1 h+ ]% h( y
#else& i4 Y6 A( V8 E, u2 Q5 U ?. \! ?
#endif /* STM32F446xx */
/ `, O! H' Y% J( \9 |1 D0 {. h
#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
3 t6 z5 E1 f. ` U/ ?, l* ?
#if defined(STM32F446xx) || defined(STM32F469_479xx)3 J5 m+ l7 U% S
#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) 7 T. K, k% ~) M- d% o
|| ((VALUE) == 6) || ((VALUE) == 8))8 m7 w% o# _: G+ F: d* A9 L7 J" L
#endif /* STM32F446xx || STM32F469_479xx */( o6 x ~ a; r" A1 u/ K) |
#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
8 s: Y7 u# ~' q
#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
' v4 X2 \4 d( d3 x8 B
1 ]% S0 ]' [9 I% u" I1 X9 d7 N
#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
) L' |' c" M9 d2 K% W# D6 S% y' ~; f
#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
. x1 d4 O# t- C0 ~! c# ~
6 n) v. f: Q% w7 Q8 E: `
#if defined(STM32F413_423xx)
6 ^8 v" E) J" e, o
#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
5 i& y7 @. A: L
#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))% r3 l7 `. y3 P
#endif /* STM32F413_423xx */9 `# j) `& ^/ x! P! W

复制代码

RCC_System_Clock_Source

/** @defgroup RCC_System_Clock_Source % l( Z4 S) O: D; L7 h' l/ [
* @{5 L. b$ @0 Q+ t4 e( t a4 o
*/" X' n% }% H9 F' H4 N& f
# f# X- C" W$ d0 \
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)( K% T( Z2 ^7 L9 O H8 D H L9 O
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)" A, C9 |) y$ b
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)2 E) D4 T( f6 x e
#define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002)
8 {: j6 t$ [9 M% @( N7 c0 n
#define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003)9 P3 u) { [; x6 K
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \8 s0 u- T" [1 q' p9 m. ]/ v
((SOURCE) == RCC_SYSCLKSource_HSE) || \8 C5 o+ u' {5 c7 K' g! \
((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \9 l# X. n8 I5 R- o2 N) r
((SOURCE) == RCC_SYSCLKSource_PLLRCLK))/ l9 w6 s2 i) Y7 i
/* Add legacy definition */
0 V; K6 h9 R; v; w$ S( i% K
#define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK
, |9 b; `1 P0 P
#endif /* STM32F446xx */* r2 G6 ? [* l; O
w4 ^, b$ b# _$ X7 ?
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) , v0 m. G1 q3 L2 x
|| defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) \1 e; }) t' j' r
|| defined(STM32F469_479xx)
1 C" H& j8 f5 h* a
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
- R1 g. n' P3 Y; K$ _0 ?: _
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
# x7 T5 g1 |9 D% N
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)1 O3 S% f3 ?4 D {* A
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
9 p; g% K7 h0 j
((SOURCE) == RCC_SYSCLKSource_HSE) || \
5 V' m# p# R6 S9 k f2 K1 L* [
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
' H. r8 w b O0 Y* T5 j h' G
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx
+ Z& w( b5 p) T$ j
|| STM32F410xx || STM32F411xE || STM32F469_479xx */
- L) Q) ~6 N5 b# ?% ], N

复制代码

RCC_AHB_Clock_Source

/** @defgroup RCC_AHB_Clock_Source" f" A1 G. H: ^& Y4 E9 z7 O
* @{ n, } f& D/ b& n: k
*/
( b$ m9 b& ^9 F* `$ n
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
* c# q9 q2 D; k$ Z
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080), O% v N7 D) s6 i2 x7 b. T
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
# N$ F2 d- |( z9 S2 |7 q1 V
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
7 t' A/ G3 m2 W$ ?3 j7 X8 w/ a
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
$ Q l* A/ Z' }9 i% ?
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)8 J3 Q' H5 ~( v5 h
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
5 G' e6 U* X H8 \/ f
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
4 {, X- Q8 O3 f2 x- c7 x9 b) ]/ n
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)5 L |4 a$ [, W) L) g" K9 {' D2 m
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \2 |1 \- _0 H: @ I/ o+ `+ w
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \+ C. a# J0 `% D) k" ]
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+ @7 |( _- t; ~" i+ W
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \5 c3 a i/ x: Y. Q
((HCLK) == RCC_SYSCLK_Div512))

复制代码

RCC_APB1_APB2_Clock_Source

/** @defgroup RCC_APB1_APB2_Clock_Source) S! \* a0 R3 u6 M; P Q4 f1 e* ~& K
* @{
, e% ]+ }4 Q3 W
*/
" A" J8 R7 |9 Q) |
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
/ V$ B( f3 t4 }, ^: s4 f/ a
#define RCC_HCLK_Div2 ((uint32_t)0x00001000)! s7 s: ?9 B8 `
#define RCC_HCLK_Div4 ((uint32_t)0x00001400)
" D! Y7 I# Y3 y& m$ Q+ [) C+ I" N
#define RCC_HCLK_Div8 ((uint32_t)0x00001800)/ e2 M9 ~; K" o# p7 r6 X; b3 x
#define RCC_HCLK_Div16 ((uint32_t)0x00001C00)- u' |0 }9 |& N, A4 r: Y7 i) M/ U
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \6 m4 k7 C2 v6 [" `
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \$ J8 x1 Q8 d6 l5 t) f
((PCLK) == RCC_HCLK_Div16))3 r) h5 u+ m6 U

复制代码

1 Z' _; ]$ Q4 a4 ?: y
RCC_Interrupt_Source

/** @defgroup RCC_Interrupt_Source
3 I0 t; j6 }, Q2 Z
* @{* D4 W# c6 H9 U8 N9 n( t
*/
. G; _" N8 f: r. X% I8 q, h
#define RCC_IT_LSIRDY ((uint8_t)0x01)
7 G7 i" w7 S+ E7 c" o# Q5 D
#define RCC_IT_LSERDY ((uint8_t)0x02)/ b: M6 ~& |, B6 B7 W/ F1 ~* P
#define RCC_IT_HSIRDY ((uint8_t)0x04)
9 A9 W4 [$ m8 O- j* @ Q n
#define RCC_IT_HSERDY ((uint8_t)0x08)
3 A0 s, @. G1 C* B8 O( P e
#define RCC_IT_PLLRDY ((uint8_t)0x10)5 y5 @( l2 a! s
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
+ @+ _& A* E) n6 W; O6 \6 S
#define RCC_IT_PLLSAIRDY ((uint8_t)0x40); d l- [( V' q. w+ A+ P5 G% W4 E5 d
#define RCC_IT_CSS ((uint8_t)0x80)
8 `6 D6 ]" e: i) z/ p* D) L
( a8 c, F. X5 U+ D, O# H
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))8 v' m: N/ y0 u3 g+ o
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \2 `( G; |+ Z7 q; x0 w: r
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \# k4 [' L, F" ]* r2 V: w v/ A5 f
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \" E6 X+ n) j$ B% S. O" u* H$ q
((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
9 D- F) ^3 C0 p% a
#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)6 F @6 r* b+ W6 M: C

复制代码

RCC_LSE_Configuration

/** @defgroup RCC_LSE_Configuration
% W0 z" y& A; o3 ^7 X- y
* @{# N# }& f/ R0 T& j9 E6 M
*/
. \& K! _4 H$ I. f" K* Y; T
#define RCC_LSE_OFF ((uint8_t)0x00)( x2 O) d' V& O+ G0 e) z6 I
#define RCC_LSE_ON ((uint8_t)0x01)) t4 ^6 |1 d+ \- }! {/ Y* A4 e% w
#define RCC_LSE_Bypass ((uint8_t)0x04)
2 ], R7 p, o5 i: ^+ N5 W a
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
; x8 P) ], j% o! s& m
((LSE) == RCC_LSE_Bypass))

复制代码

+ B4 S9 d9 C; Y3 ?! F- T
RCC_RTC_Clock_Source

/** @defgroup RCC_RTC_Clock_Source$ ~& y. s3 y2 A9 ^, @. p" k
* @{" `3 _- |+ {; ?# F0 o, C
*/+ n+ `1 S5 p2 J
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
5 ~8 l2 X0 R" |6 u# f# r
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200); ]7 d( m* ?' p3 t1 Y: W" Y
#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)0 K4 [8 e( p* g1 _/ O& }) w5 E$ G
#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)' L7 }# D: y7 q# G" [
#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300), t0 A0 x+ {7 ~3 Q" D9 P
#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)
% P. b; r3 W% Z5 T3 D/ {
#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
+ a, g" C9 z% g! v
#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)
' b) _8 z$ Z, u7 O5 @ J, u) _2 C
#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)% X* [4 f: ~( Y- E; [6 P- \
#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)
' }5 R! E# x) G$ ?$ Y" a! L
#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)4 L& p7 |% B1 F) }$ @
#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
+ }5 J5 `# Y9 K5 [* E$ h. y3 L' j
#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)9 v, e$ H1 z0 H; U: V9 U
#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)1 l0 N& O. P0 a. S9 M
#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
/ f% F& _7 F; h7 a, o# q+ X
#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)1 V+ l' w& [# c
#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
( y8 B) w8 }6 x
#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
4 E/ [, I/ t) D4 k" _! E
#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
+ D" v8 C- w2 |- H5 L2 f+ K* D
#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)) q; H. Z8 P8 d
#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)7 J+ H. Z4 j0 g- r
#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)
& j7 ^: t# ]/ F; ?5 c8 A
#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)9 \1 @4 x) S B7 [
#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)- D( r1 C/ O8 k }2 D# ?9 t
#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)1 o, e4 [) P& u0 A! J/ ]
#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
, Y5 A! p1 }7 c+ S/ p
#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)6 E7 b3 h+ P, T. p- g
#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)
) a6 E- t8 i5 l8 V" g# f
#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300), @% L, L' C7 J/ a$ G+ @2 a
#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)% ?4 V3 W; N8 A. a& G/ b4 Q
#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)
# y! f' ?* e. @; P! g
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
$ O+ p. G! N; n1 n
((SOURCE) == RCC_RTCCLKSource_LSI) || \( T j* @- h) k& k- G0 N' }
((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
5 G0 `6 k0 }5 t
((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \+ D; n! U V' H# W$ _# Z
((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \8 P: q8 s2 \6 ^/ I) c0 p# j2 p$ J
((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \7 b; z" v1 H, Z, ?: f5 i9 ^ Y9 e2 P
((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \1 E! S' ^/ i1 w7 D
((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
; F, w9 ~# P, B. H
((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \/ v/ s( y' y. f/ {) m# N2 x8 q8 d
((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \* U# ? A6 M1 R4 k2 s
((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \+ w; V2 m5 I7 u: s: t8 I) I
((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
V J$ t9 Z) G/ x) O$ E
((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
6 O. A, ]0 h5 k# C
((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \8 e: _3 S) M1 `% n. B" \+ Q$ {) f
((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \0 O7 D& f% z7 p/ o
((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
; @4 |, y5 N. i# R0 G) D$ k( X
((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
( J- h# L. v4 n# Y; d, T
((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
' T5 h* {4 v$ x$ \2 l' M6 [
((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \9 A, g2 J4 t- [1 D/ T
((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
) r0 i, L8 S" B# W7 T
((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
- p1 {7 y. }9 s. O9 L: r$ Z0 }
((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
6 T1 X/ T F+ O+ A- Y5 l
((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \! z* M7 k7 E8 \6 f( }
((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
# l5 e8 Z; a9 z% b- Z1 p4 j4 ?
((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
1 G) p% V$ e3 {9 v
((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \# H- D% `& s! H$ O3 @
((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
$ R* A9 Q, B& X8 [
((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
5 C& |" h( G( H+ c% s& h" J h
((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
" a1 O( e. [; L% q8 d5 j
((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
/ a* s/ f, N1 e, K
((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
0 T2 e/ i' u! g
((SOURCE) == RCC_RTCCLKSource_HSE_Div31))& ?; q% U9 r; i ?

复制代码

RCC_SAI_BlockA_Clock_Source5 J* o( [: x2 }) `! _

( b- |) x. [0 T: g
/** @defgroup RCC_SAI_BlockA_Clock_Source# ^* @/ X, l6 H: o8 `
* @{7 H8 W4 Y( p* r& i
*/: }, j; n6 i# Q$ o d
#define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000)
, z( _$ i0 G: C. X( c; W& e
#define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000)/ U6 ]" i3 S+ W$ D. ]# ~
#define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000)/ Z" b: ^* ]$ U' t3 d' E
% j0 Z" G( s8 w9 e) T6 E8 h
#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\
0 D R; s' d; K" s
((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\
% \$ A& L; d8 b) g9 @, J- B
((SOURCE) == RCC_SAIACLKSource_Ext))" p# W% M& ?9 v

复制代码

RCC_SAI_BlockB_Clock_Source

/** @defgroup RCC_SAI_BlockB_Clock_Source6 q# t) r- q; k5 `# z
* @{" {4 Y! Q- c' [- ?
*// d5 O# ^9 t2 t
#define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000)
' O0 _' L" r0 y4 u4 D. u
#define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000)
: E; M! j0 d# Z7 [- k+ \& Y) v! u
#define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000)$ D U, Q0 {1 E. W9 p! d
8 J. q! D: C/ [
#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\
+ T q7 S4 e4 K9 V6 r4 g' T2 J0 D
((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\
- l9 N1 Y$ H* r
((SOURCE) == RCC_SAIBCLKSource_Ext))

复制代码

RCC_TIM_PRescaler_Selection

/** @defgroup RCC_TIM_PRescaler_Selection
* x; e- e/ S7 D% o- l% y
* @{( p8 h/ Y6 j3 T( V6 d2 e: f# @) z
*/! d/ P Y7 K* z9 Q
#define RCC_TIMPrescDesactivated ((uint8_t)0x00)
( k- O, N( j' H* M
#define RCC_TIMPrescActivated ((uint8_t)0x01)" R$ m9 E* u! ]4 j& F2 G& q
' Y t" M" [; E) i2 j: @
#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated)
! g4 I7 X2 R' W3 _. v
|| ((VALUE) == RCC_TIMPrescActivated)); ?) I# d0 f# ] g$ j' e9 \

复制代码

+ I0 r+ g6 r! f% ]RCC_AHB1_Peripherals

/** @defgroup RCC_AHB1_Peripherals
% o/ ]8 q5 Z2 k% |1 r5 c) f* h
* @{
; \- n" L" j! r! E# D; q- T, K
*/ 6 X$ d2 T/ V) r5 J7 d) s: z
#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) y9 }0 b% A5 d" F1 ^5 z
#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)% f% g: X2 h$ M, _0 { b
#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)7 E: p! a4 Y) ?) H
#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)
4 c( E8 d+ f( j9 ^1 [
#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)
4 A: n) s7 @! f& K& m9 A
#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)" n" f0 \) \% l H) [
#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)) _ Q6 I9 {% ` r3 @% X7 d3 W
#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
, \1 W! j5 R' i) r7 s B
#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
& l( s" w4 U3 z7 p/ Q4 u% a; \, x) t
#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200)
. e' u, F( \" |
#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400)' f d8 h1 v; A& H
#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
4 b V) `9 I/ B9 _* k0 P$ u9 `
#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
& Q$ N$ i T2 B" z6 ]! n
#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
. r* g+ u5 y$ A! l0 y2 n) U; M' e0 z/ U
#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000). }. a3 e s: O3 K
#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)- I; G: z$ d( u% m# y; k- F" e/ M" \
#define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000)- h7 O! |# \' B$ `. {. v: v
#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
1 x) Z9 C+ b( |
#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)# F( O3 j7 E7 ~, U! B( O" W
#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
9 K' x" O3 ?$ O* D
#define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000)
; o) e3 C+ d4 n$ e8 D
#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000): V' H1 t; x+ k0 Y2 q( {& ]
#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)( l) l" p! E1 w$ W! o. \9 M1 ]
#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)5 c2 Z. v8 T/ K3 B [: A: o* M
#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)% G* H- j! \3 M2 ~
#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)( g/ d6 a0 K; C9 y; W% @0 C5 c$ g
#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)$ c$ ^* E4 N! H# d, T+ b8 @
8 v9 l6 [7 w$ K9 g0 O
#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH)
9 B, J+ o [/ V) R* e
((((PERIPH) & 0x010BE800) == 0x00) && ((PERIPH) != 0x00))% O7 G( c% S/ i
#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) " P, S+ R6 J9 l: i7 r. q8 N
((((PERIPH) & 0x51FE800) == 0x00) && ((PERIPH) != 0x00))
3 h3 q1 v6 }! s
#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) 8 t0 J+ |6 V5 D# r7 f3 c( s- z) {
((((PERIPH) & 0x01106800) == 0x00) && ((PERIPH) != 0x00)) R I; v$ T& Y( _/ ]. _

复制代码

RCC_AHB2_Peripherals

/** @defgroup RCC_AHB2_Peripherals
2 q* |7 s- @. J* y" b8 J
* @{: u* [5 V9 z, A. B( T; @+ r" ]
*/
+ a, H8 |1 Y Y: L1 @, `
#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001). O" m# s" A! F4 [. x
#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)5 ]5 L; E# R1 [+ ]
#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
8 q( P q6 ^* B3 x2 W& r W, N
#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
6 ~( V! w: c( }4 V6 Y4 p
#define IS_RCC_AHB2_PERIPH(PERIPH)
8 m% H0 ?" q, h# E9 M
((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))

复制代码

' m# c9 V; _8 j/ FRCC_APB1_Peripherals

/** @defgroup RCC_APB1_Peripherals
# N f% b- P6 o& e: X* g3 |
* @{" ?$ u' ^" h7 q/ y( q/ x. e% m
*/
1 d6 u9 S* `$ A) l/ P% Q
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)6 l- c! `$ I/ o8 g# l
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
/ ?2 u; |7 W: H# I' r7 L
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)" {' w, J0 G, q' l$ u. O
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)$ t9 x! X5 v: o& A; S
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)* m6 q9 Q% R) A( z9 q
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)4 [* F$ Z. S" i* `
#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)+ S6 H, p) `4 b- p* {
#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
6 D0 ^7 k8 m; C& p
#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
: z' \# G" ` ^9 {: d3 ~7 ?
#if defined(STM32F410xx) || defined(STM32F413_423xx)
$ M( H5 E5 G" r7 j& @
#define RCC_APB1Periph_LPTIM1 ((uint32_t)0x00000200)$ j1 \, {- l' f# w/ K+ f l6 m
#endif /* STM32F410xx || STM32F413_423xx */1 c0 v5 e: ~6 N3 p' `7 z$ c7 W
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
1 V' t4 r M) F9 X+ [1 A- ~
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
6 R0 C) r9 D: W/ l' ^, S$ o7 [
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)' x7 A4 u" T. E0 U! a
#if defined(STM32F446xx)
0 N) h& h( C B: ]4 M
#define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000)
& Y% P# F5 S4 N
#endif /* STM32F446xx */
$ v; q. G4 A+ b1 m+ e
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
, Z6 Z: l' z2 Z: }+ |
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)- H$ e3 n7 u' ~8 ^0 i. [
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)( M! f+ `7 T, D T' t
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000), o1 }3 V* B& t
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
5 F$ O! V3 M/ |, M- g
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)! X2 X! \' g, e& Y
#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
/ i2 B3 D% V. }( f$ R
#if defined(STM32F410xx) || defined(STM32F412xG) / ?2 i2 Y$ [$ u0 g( l
|| defined(STM32F413_423xx) || defined(STM32F446xx)$ |' F; |/ O, a3 G
#define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000)
$ m) y" z6 z3 p* F) u. D
#endif /* STM32F410xx || STM32F446xx || STM32F413_423xx*/ 0 q; N& V1 A* p/ M0 c; Z8 m
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)% ?/ W w' ]) P( j- Q
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)4 R6 r% F5 f- H; g8 o, m
#if defined(STM32F413_423xx)
/ i/ p6 J2 W& O7 o, C9 p
#define RCC_APB1Periph_CAN3 ((uint32_t)0x08000000)
: d7 W0 A' |6 O) w6 c
#endif /* STM32F413_423xx */7 ?! i9 X6 Z. r% }" L! W
#if defined(STM32F446xx)8 J7 i; E2 L- g" Q( ~
#define RCC_APB1Periph_CEC ((uint32_t)0x08000000)
+ U1 W) h5 t1 ~6 C: H! p
#endif /* STM32F446xx */ # @4 v+ I4 N1 W$ M- b; T( Z
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
* l; \$ J. A- R% Z" g% \' a1 u1 W1 _
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000). I F5 Y( v! @3 A$ Y, R
#define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)
' R B! l9 d3 _6 [, q
#define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)
- ?) Y, q8 L, v" J9 S) G
#define IS_RCC_APB1_PERIPH(PERIPH)
* s4 m, U/ C' t4 E3 H8 R5 H
((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00))$ w2 j7 o8 S! f4 a4 ^' I% ~; T

复制代码

RCC_APB2_Peripherals

/** @defgroup RCC_APB2_Peripherals ( X6 u+ T6 C7 ?8 ^6 D( F ~( m
* @{3 Q5 S0 U& \3 X( |* v
*/
1 k2 J$ S. o+ q* Y2 T }9 Q$ ]
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)) L" I, }8 _. y5 \/ J
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
* X s; o M3 g0 w
#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)3 `* w+ Y: R5 l. l
#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)
1 H, p# {& U/ Z% R3 I* d5 f
#define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
T$ `* g) V# E, W" }" ^) I
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100): i2 h3 Q: ^ \, I; L5 H
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)
9 D% l D" I2 p6 k# O" E
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
/ ]. Q6 H! Z6 H* C! f% F3 d
#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)5 Q" }' I; I, l0 b/ i* ]0 }
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
. O5 N0 A) q# p6 X
#define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000)
5 {7 ^8 d6 q9 O. {' h9 U
#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
/ q2 ?! v2 A7 @1 B
#define RCC_APB2Periph_EXTIT ((uint32_t)0x00008000); d9 |) c+ w5 g; }
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)$ R% o1 k( }9 S5 Q6 U( ^& G3 z8 y
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)6 y1 m z* p5 ]5 ]
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)) I! w" m2 b% g7 Q, Y& N- B
#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)
' A2 d) n% b7 g/ ^; H
#define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000)+ G/ K( c/ }: e0 @- W: p( g' ?
#define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000)2 i9 _- @+ i( h
#if defined(STM32F446xx) || defined(STM32F469_479xx) W2 o# s+ F3 E, P
#define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000)
4 T3 a& E6 t7 x! P
#endif /* STM32F446xx || STM32F469_479xx */9 [& R) a' W% G* m" I
#define RCC_APB2Periph_LTDC ((uint32_t)0x04000000)
# @$ g, ]- t% ]; O b
#if defined(STM32F469_479xx)) \" K) N, l1 A( A' i
#define RCC_APB2Periph_DSI ((uint32_t)0x08000000)8 y& @: @9 I- A3 m/ E
#endif /* STM32F469_479xx *// u x" _ q9 \( `6 E
#if defined(STM32F412xG) || defined(STM32F413_423xx)
' I; U8 [ h, o# c4 T
#define RCC_APB2Periph_DFSDM1 ((uint32_t)0x01000000)
4 Z. e4 X A1 B5 K% X
#endif /* STM32F412xG || STM32F413_423xx */
2 D, N/ t& [7 ]* T. i
#if defined(STM32F413_423xx)
6 B1 V7 Y7 r; \5 w0 K n1 c, w- N
#define RCC_APB2Periph_DFSDM2 ((uint32_t)0x02000000)+ t0 ~' }0 n. T
#define RCC_APB2Periph_UART9 ((uint32_t)0x02000040)
9 O3 y9 t. D2 b
#define RCC_APB2Periph_UART10 ((uint32_t)0x00000080)' J4 \+ ~1 d$ i! p, u/ X; l/ p
#endif /* STM32F413_423xx */0 d- `2 S2 b0 X
; ?9 D& ]. e* X3 d t" X# x
/* Legacy Defines */1 j. w0 G+ {6 i
#define RCC_APB2Periph_DFSDM RCC_APB2Periph_DFSDM1
" l2 S, J- Q+ N* w
#define IS_RCC_APB2_PERIPH(PERIPH)
9 O8 O6 a% Y) b# x' m+ S
((((PERIPH) & 0xF008000C) == 0x00) && ((PERIPH) != 0x00))( x- e) d* F5 ], X9 L
#define IS_RCC_APB2_RESET_PERIPH(PERIPH)
! s6 C- c p" S8 G) b8 A
((((PERIPH) & 0xF208860C) == 0x00) && ((PERIPH) != 0x00))

复制代码

RCC_MCO1_Clock_Source_Prescaler

/** @defgroup RCC_MCO1_Clock_Source_Prescaler4 h4 O' k4 n/ g& O( A8 ?
* @{
, }3 p9 b/ j+ y7 x# i U
*/
# l9 f" G4 k$ O; x
#define RCC_MCO1Source_HSI ((uint32_t)0x00000000); E4 _7 u6 e9 D8 O: a* c( X. M
#define RCC_MCO1Source_LSE ((uint32_t)0x00200000)
. c+ ^) ^" D) L' d% h
#define RCC_MCO1Source_HSE ((uint32_t)0x00400000)" O; n# }* ~& w
#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
4 w s( x- e9 k6 ?: X% L8 z
#define RCC_MCO1Div_1 ((uint32_t)0x00000000)) L& {/ W% C1 g4 O
#define RCC_MCO1Div_2 ((uint32_t)0x04000000)8 Q. B) I9 l1 f V7 n# \/ ?, I7 `
#define RCC_MCO1Div_3 ((uint32_t)0x05000000)9 q/ l9 D0 N8 w2 u* C0 z
#define RCC_MCO1Div_4 ((uint32_t)0x06000000)6 _. H J1 I2 X; n& x6 U. o
#define RCC_MCO1Div_5 ((uint32_t)0x07000000)
, g% t' {9 l" x9 N3 c4 r
#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) 5 z/ v/ Q! m7 [% c7 E7 H; n
|| ((SOURCE) == RCC_MCO1Source_LSE) || \2 \: V0 Z" F( e1 k3 X* L# O, M. N# X0 @
((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
; F2 k% C7 K, c% b3 [6 Q
* i0 o- t# ]7 C) R! Z9 D1 m
#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
; K1 J5 T( p4 Y- D
((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
, Y5 [. A5 t: w9 v0 H; C: [
((DIV) == RCC_MCO1Div_5))

复制代码

RCC_MCO2_Clock_Source_Prescaler

/** @defgroup RCC_MCO2_Clock_Source_Prescaler
5 D! x# x5 Z8 b) d d, R- {+ v
* @{
* m# y3 n) b# S9 P
*/6 q A8 ?; L8 H( F' a7 K5 w
#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
( J/ C; N _ U1 D9 I' _
#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)
2 v0 Z: ^, F, k
#define RCC_MCO2Source_HSE ((uint32_t)0x80000000)6 p( }) I; l" _4 d4 f
#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)
; s( P0 Z1 D) L, z7 Q5 Y
#define RCC_MCO2Div_1 ((uint32_t)0x00000000)# q3 K" @: x& M2 H; T. l
#define RCC_MCO2Div_2 ((uint32_t)0x20000000)
1 L1 |* m7 }) W
#define RCC_MCO2Div_3 ((uint32_t)0x28000000)8 j3 @& v: Y1 _, n5 e5 q) a
#define RCC_MCO2Div_4 ((uint32_t)0x30000000)
1 f H9 `9 S* r/ f2 q9 n( H7 i
#define RCC_MCO2Div_5 ((uint32_t)0x38000000)
5 o/ O' {* b' z6 u, G
#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) # M5 T" @7 W0 `" c6 \, _( X* K9 ^
|| ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \3 v4 E# G3 g$ R- l0 H% A O/ m( H; o
((SOURCE) == RCC_MCO2Source_HSE) % @" ]+ K- i. y& q
|| ((SOURCE) == RCC_MCO2Source_PLLCLK))2 d* ^6 S& P. V7 L3 _, Z
# q6 ]( O% p* W# ~# j6 c
#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
2 z1 L' R$ p% J1 L7 h2 V, C
((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
?& s4 s$ t' }; m3 V, f
((DIV) == RCC_MCO2Div_5))
( N- A9 }3 }7 C4 B# e

复制代码

RCC_Flag

/** @defgroup RCC_Flag
& S9 F6 B |" W; G( C: b7 m
* @{
; S3 H4 G1 j1 q2 J) q$ `& U
*/3 m) B' @' Y6 p( i$ S! B# [
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)/ L7 m9 |6 z2 x, W% L, `
#define RCC_FLAG_HSERDY ((uint8_t)0x31)$ Q* ]; [8 ^* M4 ]- g& i
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)3 A; W' b+ ^2 F/ v2 a
#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
- a w! R) z% f4 ~! {( b5 `
#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D)' D4 M; J8 Y3 a
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
) o( {) q q9 S
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)$ K/ x8 ?# E& V* h
#define RCC_FLAG_BORRST ((uint8_t)0x79)
4 J% u$ N1 J4 B2 ~$ Q
#define RCC_FLAG_PINRST ((uint8_t)0x7A)6 P' A W$ d, _6 J8 K8 o; ]& M/ ]/ J
#define RCC_FLAG_PORRST ((uint8_t)0x7B)4 g0 Y# u. v9 _1 m
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
/ R4 A4 z( }/ t( b& Z$ \9 T' R
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)9 f; d" E9 m2 o# F" ]# w T h, x/ ^
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)3 \. |! @( n% P" Z# o9 I! F% O0 n
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)/ ~& Y4 U; r3 ] U
3 ]2 w W+ h; N S% F$ j
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \7 s8 [' p$ \6 [1 y: p
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
2 N" A: I a6 H) W* Y9 [/ g
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
1 n0 T7 @" l$ G$ C# D& M+ o
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \* x8 k9 t3 v; P3 \1 [
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
9 D" J. y# q8 [6 n' e( k t, t) J3 w
((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \5 N0 D: X) l1 c _
((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY)). P, T4 @2 }3 p
% j m/ G0 |* K2 i- L, i" U
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)

复制代码

2 {. D7 g9 @, E, Y6 E+ y03. 相关函数

/* Function used to set the RCC clock configuration to the default reset state */. H( A1 f, }0 N c, `( ?9 X! ]
void RCC_DeInit(void); ^" o3 r X0 X0 C& U9 ]; q7 p/ }
& g2 `$ U5 j' D7 L( B( d' t, C7 b
/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
; D: K+ E; C7 ~5 H0 Z0 ^5 R O' E
void RCC_HSEConfig(uint8_t RCC_HSE);
+ H2 B/ o5 |3 J l
ErrorStatus RCC_WaitForHSEStartUp(void);
! Q2 U; |; f, x8 |5 M
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
0 x" k8 G8 T; I2 Y# G0 ?
void RCC_HSICmd(FunctionalState NewState);' }. _2 X5 A+ A
void RCC_LSEConfig(uint8_t RCC_LSE);
% \4 d+ ^1 V7 m/ }" b
void RCC_LSICmd(FunctionalState NewState);
. I5 @) }' S* O! \
7 y* g$ `- S) t8 B% l( j k$ i7 q
void RCC_PLLCmd(FunctionalState NewState);
( w6 a( V$ a G7 H
& l8 ?) u* v# k# j
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN,
: F6 B5 P) x$ Q, ?' ]
uint32_t PLLP, uint32_t PLLQ);/ h& i) |9 j) Q' k$ \1 d7 l
. c* q0 [# H; r0 I5 c" P: k
void RCC_PLLI2SCmd(FunctionalState NewState);
5 u' [$ J" y9 q- C6 `- {8 g9 O3 W
1 s. ]! R( U" K. E% _: M
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
; ]7 Q* {# I; z% z
1 R B, o5 M9 D- u3 P, E
3 Y: w8 A+ D- f, S4 w; a5 E
void RCC_PLLSAICmd(FunctionalState NewState);
5 e. p0 P2 ~: A$ C Q2 P" D
; L. @1 `' K; I
void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);3 o0 N' T$ I+ e4 b6 l! R
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);6 I% O; f$ a5 h8 _! W* T
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
% T- c% I' I0 G
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
3 Z: A9 d8 B" n9 p1 S& y
. {3 I+ m5 k. }! o. t3 g
# K a J) O# j! k
/* System, AHB and APB busses clocks configuration functions ******************/4 d6 o3 g7 q+ g# c/ @; q$ b
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
. D% N& Q! x# z6 Q9 p1 ^6 z
uint8_t RCC_GetSYSCLKSource(void);
3 ]$ R" n3 w3 c- q! ^
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
) d* [* y2 E% W
void RCC_PCLK1Config(uint32_t RCC_HCLK);
. r$ r. b0 H: C2 e
void RCC_PCLK2Config(uint32_t RCC_HCLK);
3 V- ?8 [% W4 {& k) h
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);4 J1 Y. H9 ]. b( J! O( M _3 D
6 D2 h3 w# ^ c; {5 P+ b
/* Peripheral clocks configuration functions **********************************/, r, m d. K1 Y6 L: s. b
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
9 l0 K+ z6 F* y+ u1 G* ~% @3 s
void RCC_RTCCLKCmd(FunctionalState NewState);4 O& d: V1 B' }0 s2 |* ^
void RCC_BackupResetCmd(FunctionalState NewState);3 F- z1 V' n# K3 T6 N0 J: d
% o; J4 c+ Y1 c8 j6 g
A0 m* L! n9 p2 _' `- E
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);) H' X2 p0 _5 J- h% v3 z) j
5 Z: ^) }; T( C( l) {, y' U
2 n) K% T# l# F0 j* Q
void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);7 D& h* n: l) Z( T
void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
% }3 [1 E9 @* ] j
9 D1 N* h- k' x3 z
( e$ a! c/ { \% S' S, D
void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);9 f5 g5 C. l$ h: u; u3 K6 y
void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);- r% O9 l' Q9 q7 I) x' n, D
3 x2 `7 N2 A2 T% P$ P5 p3 F. k9 L
( a) h$ ]" s. A% I; x7 w
void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);
8 }( a5 G+ N$ y! ?4 z5 [& a2 F( J
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);: I8 \! L5 h- q. C& J' h
7 W' c8 z: s6 \
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
6 K1 ~0 W% \- \' O
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);# t1 t3 b. `% D6 q! r. B; f" m, ]
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
: z5 L0 C% K- ]. b/ [3 y6 O
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
1 k& q( V0 D" D. ~7 r
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);/ \5 x5 c" M& i+ {* |0 e
]* o9 f, Q/ g* `
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
6 e, Q, k2 p7 X R" Y( s, m' e
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
( P* u# V' K9 {
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
7 C/ W- T( N3 a% M9 V
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);* |) t7 z& a x$ T7 \2 B, _. A# S
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
' @' h& e5 u3 n$ @( J
, o# u. G+ I+ g
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);9 l/ ~ t9 R3 x4 O4 I
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);$ d9 p! {7 ^6 N+ E8 v
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);0 n# R1 U& Q) c& `& a a
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);0 {% [( S* c4 E: c' h4 s0 |# K
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);- I# p6 c+ ?8 M& t! [# s. X
5 G. Z+ i; }* i
: l) Q' U* \+ ^4 q2 B$ _% F$ h
/* Interrupts and flags management functions **********************************/
7 Z* A4 M) ~. f" e) @# A
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
& U- y4 a V$ h+ ?. _; P
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);2 m% O U" A; ^
void RCC_ClearFlag(void);% i7 K: a6 N) S% C! ^! ?$ O
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
( c" `# j2 f) [9 x* D3 X
void RCC_ClearITPendingBit(uint8_t RCC_IT);4 K$ c3 Q3 c9 {" H/ U1 W

复制代码

04. 结构体封装

/**
0 i/ j/ a, r% e) K1 j
* @brief Reset and Clock Control B& \$ m# K# s5 L h. v
*/1 D* Y* o. Y+ E; m
% c+ }$ p- r4 ], E6 n
typedef struct
# M/ ?: e4 b' ^7 p2 A
{
5 u- o1 ~$ F) _; P! H
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
6 J4 R- [- c0 j3 A
__IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
6 B, _. S7 }+ O* M! H
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */- e" u. j$ C3 P, c( `9 [# g. D" s
__IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
: w% m; @; v. V
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
1 I2 r& z( x) T8 g8 u7 _
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */5 k! w( v; x: o
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
# B0 g3 a7 E8 U1 A# q
uint32_t RESERVED0; /*!< Reserved, 0x1C */; V& c6 @& P' N
__IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */' E+ B- S! \* n3 [
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */2 c& z1 U3 q! m. q- w2 I
uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */% W$ T9 B3 ?4 z; p$ L
__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
# Y! T; C) d0 |
__IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */* b7 q* m& V# i9 T# m6 B
__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */, x, O. d! k* ^' s
uint32_t RESERVED2; /*!< Reserved, 0x3C */: W) S2 g8 I3 r: K
__IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
1 U! ]' r) M* D, v
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
% y2 p' c7 E' o; n
uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */3 T' {4 y' c; Q4 }( {' U$ c
__IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */- W6 s# c' H% d0 {. T$ }
__IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */8 @0 J, h9 M6 u, }* I
__IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
1 u$ u3 F2 F" C1 g7 _
uint32_t RESERVED4; /*!< Reserved, 0x5C */* F! D2 O4 ^6 Y
__IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
; i* m2 B6 {1 n7 z: A) N% f
__IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */. h, o, a, O& ^& |
uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */# b' z1 P3 f% m+ a3 T1 G
__IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */- x& W2 I$ d8 W- W
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
- p+ p( o( p0 p8 l( d; B: R& A- i* I
uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
7 y+ K! l8 [6 Z
__IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
7 K" H+ m$ J0 n* z4 Q0 X! y
__IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
1 q4 G+ [& _ d- X+ Y
__IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */" [$ M, v% Q1 E& ?8 {- n
__IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */; O1 l- C" G* F. T5 P. B6 L
__IO uint32_t CKGATENR; /*!< RCC Clocks Gated Enable Register, Address offset: 0x90 */ /* Only for STM32F412xG, STM32413_423xx and STM32F446xx devices */6 J1 X, {. Y+ j+ _
__IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */ /* Only for STM32F410xx, STM32F412xG, STM32413_423xx and STM32F446xx devices */9 x! l% ^. Z( n) O! s+ Y, W
3 C% | R$ r+ |; \- H9 R2 e
} RCC_TypeDef;0 O1 J7 a. V, V1 Z Z. }

复制代码

05. 其它

/******************************************************************************/
2 V8 {5 T+ ?7 V: Y3 [5 B. A$ F
/* */ x ?& b" s" m: M
/* Reset and Clock Control */
% h8 }4 F5 ~ W, Y0 u
/* */# c$ M5 s, u7 @- J
/******************************************************************************/6 K. B5 `2 g) m' L
/******************** Bit definition for RCC_CR register ********************/; e1 u: j9 ]; p+ ?0 D
#define RCC_CR_HSION ((uint32_t)0x00000001)
( o) G3 y/ c. M: ?: n
#define RCC_CR_HSIRDY ((uint32_t)0x00000002)5 L2 v* n/ D* `+ F
) O! {4 L* b& m( y% b. H' K1 P! u
#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
- Y6 S2 s# \% l- k' z
#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */& X7 \4 ~( u* Z% ^+ n
#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */8 @! q( z/ W# ~
#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */" w0 f" a1 d( M4 w4 U2 H( q
#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
9 s8 s8 \1 N9 x* l7 q
#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */, ]6 i+ U/ n# n* M% r6 z* H) u
7 K$ q' S' d) ~
#define RCC_CR_HSICAL ((uint32_t)0x0000FF00); I* {' ?# Z* F" n
#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */- t4 _. q8 Z# o2 O- C
#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */$ ^1 \& D l5 P
#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */% j2 J8 _$ f& ^. K! o3 T0 W
#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
' b9 E8 A( F+ b
#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
# i, K( j' P' Z: S8 J
#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
2 z7 j P! N* d0 R1 k
#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
4 C* x7 G, ?2 K* P: r( b: R
#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */: B" n4 Z1 \4 g4 a2 R0 @! }
/ A( R8 {' N) t2 `
#define RCC_CR_HSEON ((uint32_t)0x00010000)& f2 g' w- c8 }0 S- b* {
#define RCC_CR_HSERDY ((uint32_t)0x00020000)
3 v; D3 T/ I( u i: {. i- ~/ h" |) E
#define RCC_CR_HSEBYP ((uint32_t)0x00040000): z5 J' K, y# l
#define RCC_CR_CSSON ((uint32_t)0x00080000) B3 [. i* D6 b; x
#define RCC_CR_PLLON ((uint32_t)0x01000000)3 B+ G5 h, V) W+ R. v
#define RCC_CR_PLLRDY ((uint32_t)0x02000000)& C: c7 D$ x" v, Z' U/ f
#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
. u7 { k4 G: Z# v
#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)2 u- ~, n# h' J' [. i
#define RCC_CR_PLLSAION ((uint32_t)0x10000000)
( m" Q* E9 L) B8 w
#define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
. Y! e1 R' _( O' ^
4 H$ t# N6 d4 C% [' j- D8 Q
/******************** Bit definition for RCC_PLLCFGR register ***************/
" C9 U) G* I* j( @7 `
#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
3 b* |/ w6 I, t1 v; ^7 B, F" E5 a4 f
#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
( H- [. k0 i) Q+ [
#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)6 v9 D4 K" @1 E: R
#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
5 @' t. I4 N$ y$ F. o( y% i; j# `- p9 u
#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
, S& ?1 q' J" c5 }7 P
#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
$ F! a' \4 F2 A4 M; ?4 L! ~# v
#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
' ?2 G$ R0 l- C
" a; s$ ]' `- P* m3 ?
#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)3 d( s$ R; W9 O, b
#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)( L, d( E. i6 ?5 ]3 V" j
#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)/ T, H0 r7 t2 U H2 z1 B( B" j$ R
#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)( `1 s0 j( i' T0 ^4 ^' j
#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)$ Q3 ^; [1 \( O" \, e
#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
9 o( E. p/ p2 q+ q% f. B \
#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)! y, A E& m9 T6 b7 d2 H8 E
#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)# F$ P5 S9 ~/ ^' h
#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000), l6 O9 x4 }* H0 Z. D
#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)2 e* L0 U3 ^$ r% V
0 }3 {; u W3 z& h u
#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
1 p: h+ Y4 Z( A+ G- Z
#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)+ ~/ s& r5 F" d8 X
#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
- ?+ _ R# k+ B* K7 e
; @& S v$ Q J1 B% D& G
#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
( _3 U. T+ [7 W7 O+ R# L- V' v
#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)- B' A9 H2 v" q9 ~5 c" x
#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
4 X' u( i5 f1 t; Z) l0 w
4 G* \9 n8 V% {6 \9 s! X
#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000). L& D7 {) [/ Q* H9 }
#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
`% G. h' C$ _& }2 O) W' K D
#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
3 X: v7 L8 N5 w, Y, n
#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
% J5 P7 D$ M! }! b# ]
#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
, u4 R4 e4 b% P# {. F" C |& o
' w5 g! b' W7 F! y l: V
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)! s: a" ?8 B$ T! J" u/ B$ _
#define RCC_PLLCFGR_PLLR ((uint32_t)0x70000000)" P6 Q- c+ L9 \& R6 D
#define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x10000000). @: j1 k) T# D4 r2 x5 z
#define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x20000000) y9 i# ?8 \: j6 F; p. m
#define RCC_PLLCFGR_PLLR_2 ((uint32_t)0x40000000)
& z1 i `: v0 ?$ E6 L4 ~* Q
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
6 U( z& u$ K: y" P8 c
+ w" X+ Z- y5 c4 t. [
/******************** Bit definition for RCC_CFGR register ******************/ s6 A7 _* K+ V2 M
/*!< SW configuration */
) h$ t0 `( w! u4 S; c* C
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
7 f& M7 X( d% a' m6 a$ l
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */+ }- h) ]4 z0 b ^& \, R
#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
) X& q+ l) o4 Y" k
( I( D; H: Z. f7 w9 k2 _
#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
9 N+ ^; s% z5 h2 v9 b
#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */5 |; E4 Y( i; p Y% b/ i1 T- A) [
#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL/PLLP selected as system clock */" I/ _7 c) J0 \& l
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
4 z; z) D2 J; b# A/ M3 z
#define RCC_CFGR_SW_PLLR ((uint32_t)0x00000003) /*!< PLL/PLLR selected as system clock */) h+ L$ N3 z" B0 b9 C6 g
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */1 z9 L$ r3 z: s# a2 m
1 r8 c5 S: X l; d0 R
/*!< SWS configuration */( |" l$ @& r x8 b
#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */( h+ x9 \2 Y; m2 I( t8 |
#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
0 E+ x( T3 Q+ T
#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */0 D" y7 _: {0 f9 q& D* n
/ Y7 g; V+ r- t* B6 C7 I l
#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */3 [/ f, n# o7 J$ C: b' w9 S
#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
' |7 d2 Y( X4 D8 d8 T) [
#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL/PLLP used as system clock */
3 D8 d& G( L' I; M! I+ e( o$ o
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F469_479xx) || defined(STM32F446xx) m6 K% ~7 ~6 e- o6 p' \6 h
#define RCC_CFGR_SWS_PLLR ((uint32_t)0x0000000C) /*!< PLL/PLLR used as system clock */
. y6 z% @7 @* {! `. b
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
/ |9 Y- W$ B2 ?
; B+ D% `! f" M( j! l; {
/*!< HPRE configuration */
e" f$ w d6 o" {) |* f5 @8 D
#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */- C* E6 S: {8 j* A
#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
/ e. g9 H1 N- O
#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 *// u% h( T, w9 o1 K7 e' a. m; E
#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */) F3 ?1 W0 Y2 D0 g" M: \! v
#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 *// `4 U l5 l. j/ n! X' [
( F- ]+ u6 c3 n, Q p# X/ A0 {$ B
#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */7 P/ r, Z! C" F
#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+ _* p2 r- K1 G/ R
#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */5 ^- T7 @( y( e5 X( j/ c8 x
#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
" `# B7 V+ S: `3 J$ w2 T! n
#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
% R- P) l) I- N
#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
/ W0 X/ v4 \6 q& a0 M
#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */: R0 \" z# s! K" d- I1 u
#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */( V2 D* N( T+ I% L
#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
( e( m: _# h4 F! g5 x
" i4 T0 _: e7 \# R! c4 l1 n2 e7 [
#if defined(STM32F410xx)
$ M' b9 U9 L: S+ d" k: ]; z
/*!< MCO1EN configuration */
2 C N+ i3 [9 Q
#define RCC_CFGR_MCO1EN ((uint32_t)0x00000100) /*!< MCO1EN bit */- V& z# f$ D4 q! A* y% t) r. A+ G% I7 N
/*!< MCO1EN configuration */
1 @" L3 c6 x+ [3 j5 V7 h9 ~: o' P
#define RCC_CFGR_MCO2EN ((uint32_t)0x00000200) /*!< MCO2EN bit */
) R* ~& _, [0 \# h5 I/ P
#endif /* STM32F410xx */
6 |* L7 J; d" I) ?! l% `
/*!< PPRE1 configuration */( d: H* _% Z1 h/ `& D2 Y7 ?
#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
8 o! A0 m! v0 C% h: e* \$ p
#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+ F7 \. M$ v# ]. v+ O& X$ w6 z& `
#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */3 F7 S: N7 X! C0 V v
#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 *// Y3 {+ K4 V& y/ a9 L4 j! P; f h
#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+ X4 d& z f: B s0 ~* c
#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */! J0 ?" f5 g2 l
#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */9 |% O& _& s( M9 H, W
#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
9 z. J" i2 i' S) }5 Z" M# h
#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */; b; f+ Y3 Z8 O# h! b/ V% A
& o8 Q0 C& v4 r% V
/*!< PPRE2 configuration */
0 @! E; @ Q: C
#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
8 o! n- B& Z% T7 J9 r/ S: i
#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
# T$ }, E1 N# k
#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
4 G) l7 f2 ]9 S. m
#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */0 O: \4 Q# P) e
7 E# ^: a+ _) X% S; w& R6 P; {. t
#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
. |- l% x" k( O* G1 D
#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */# E! t: W' j, @
#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */) s& y9 e1 w, F# Y1 d$ H
#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */% l z7 K- b9 l/ n
#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */% c& W* ?- E. i$ ~
( l% r' U$ Z/ ?: x% X' J
/*!< RTCPRE configuration */
) |' ~7 Y# O: Y
#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
0 X& f8 ^ z1 B/ A \) D0 j9 C
#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
& b" U; n6 |+ z# b# u
#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000), z7 W" L+ t% A5 W
#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
, }% V) f1 y& K0 B- G$ I2 D
#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
# R( o6 @/ v+ V: A" z1 X$ P8 K
#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
1 _, k; f/ C7 v+ l( W6 i2 F* W, N
6 Y2 y8 ~) m1 d4 ]) y0 R" `
/*!< MCO1 configuration */0 G# \; m- g' F1 u/ e3 ^
#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
& l( I/ U& x; W$ K( S& ~0 z
#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)6 ]0 X$ k( b; g" `6 D) G- d
#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)8 O, N/ D3 G: \8 P/ w# |% B
, G4 K% G1 W, Y
#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
; M! M0 i+ G+ V; R3 _2 ?7 f8 g
$ s: {/ |/ R, |' D, q/ k
#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000), O/ H: M+ u) ]1 g, Y
#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
* ^; j" v4 [+ T7 S: s! B
#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
- N+ _. l8 m- h; ~( Q4 z& G
#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)8 H: U, y- k4 ]( E* k. q4 G
( }2 {- R. O/ h2 u7 Z" {2 M
#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)3 @% v6 @$ y! d% c. S5 O( S
#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000), n; x! w9 y9 M6 T; y
#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)5 X6 {# l% G4 F& a! K
#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
6 d; l- }# r6 p5 M# R8 `" Y
4 g/ D/ Y" S, M" a4 ^: R' P* W& S+ N
#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)5 f: A4 j5 o8 a( }
#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)) W, Y. C6 S% \+ }( E( [% n
#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
' E& a4 a4 S8 ]3 k, k7 c
9 e; d) ^; C. k/ @$ L
/******************** Bit definition for RCC_CIR register *******************/+ Y' {. g( T/ r6 v6 I6 A: G& ^
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
% v* v9 M/ T5 ~8 k' f3 X8 Q
#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
* S# ~, f1 E( S
#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)# ]/ A% f$ k! i$ Y% |! Z8 X1 w4 H# q
#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)& }4 V+ o( { A. z: w0 T* Y' a
#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)& x+ |; ^3 s! R" c0 M6 V; Z- a
#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020), d+ I' S' i( [" r: l1 g+ ~) y; G3 V2 e
#define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040); r5 K- Y6 B2 o! g5 p0 i
#define RCC_CIR_CSSF ((uint32_t)0x00000080)" V" r/ g4 S! y
#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)( F" D# p: u* _
#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
8 P4 b' K3 F0 }
#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
8 L- g: l6 ^0 J. I4 j+ D
#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
! [+ Q1 K& o) k9 V7 M4 |# \3 j
#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)& c3 A" x0 N$ p* c2 X0 Z
#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
5 `( K- ^ A+ j
#define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
6 s4 \3 n# j2 g- c
#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
# t3 y( v- |7 ? P
#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
) I: b. i8 p$ w
#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
, M$ z" Y, B( p, b, J7 |
#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)5 f% ^) ?0 ~. A: d2 y
#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000); U. I7 L k: ^
#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
) F0 O0 X' {2 S
#define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)1 n t) U- q8 l# c- {- {
#define RCC_CIR_CSSC ((uint32_t)0x00800000): P( v9 j! c$ P) j
9 M4 r/ J, j& X: J# u# I
/******************** Bit definition for RCC_AHB1RSTR register **************/
6 d5 b! V' B- R! C z) W( f
#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
' w% B0 d5 v' P B7 X8 O3 V
#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
! P, k% b4 d. t* t9 f1 c+ v; G
#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
7 s9 \# J0 }4 V. t4 N) O
#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
/ t# G, I$ Q9 Q2 b' ^
#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010), ?# s. |" M( V& j
#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
1 M+ K! p3 c x) h
#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)! e/ |8 t: s( F" i o" M
#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
2 D3 V) b) n5 v
#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
; j( u" ]! A9 J0 ~& d
#define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)# e+ X! D/ ~3 E6 U
#define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
8 V# W# ^0 q" b6 S4 ^4 _ ^
#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)$ S+ g$ v7 j4 |: F) w1 Y/ S; j& [
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000); W- E* O9 b- y5 D# a8 W6 m: f' K/ o% Q
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
5 X# P% |; Y$ U; Z- w: r
#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
# @; \& G3 G9 u$ z" \5 U+ R
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000). A. d- K0 J( |3 B
#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000), t8 J+ o/ d0 I; r% L1 X9 J0 U
2 p x7 P' T4 ^7 S, U
/******************** Bit definition for RCC_AHB2RSTR register **************/
* r" O: u8 U, N$ _( l8 x
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
( O# z2 r& `6 c% W% e0 k- j. R
#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
7 I2 Q! i, J- ^- r
#define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)- P9 u% Y! a% o5 R; R
/* maintained for legacy purpose */1 ?3 c% n: [9 E8 T% S4 L4 z
#define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST' `$ L/ k. R0 n. [
#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)) y# x1 C- h* G$ k* O1 y1 @
#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080); v0 S B; p0 W8 s6 n. Y
7 e/ v, H8 ?0 E) l
/******************** Bit definition for RCC_AHB3RSTR register **************/" m+ A0 f4 ]6 R2 `3 k2 W: ^) r
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)' k8 t$ B! V8 r9 d* c; d, Q% E
#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
, I2 O0 m- r, w3 B
#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */) q) ^2 `4 E8 s. P
! g2 i5 y* P6 B- [( Y
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
; H' ]$ u/ r* B p% K& R2 _
#define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
. ]" _0 H0 G6 {+ |1 r7 I
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
- D( W, k+ g$ M) H5 a5 q* t
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)+ t) _, R, _8 Y2 Z1 @# T
#define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)
$ Z3 J+ t; P3 h S9 \0 m
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
9 u* e0 U6 _* S9 k: Z* h- x4 _( r
+ v% d8 D, |+ x
/******************** Bit definition for RCC_APB1RSTR register **************/2 _/ Y! b2 `$ I( P0 F! X
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
3 A/ ?0 l+ q* u% {: z' g3 Q
#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
: k2 {" ]$ R. j
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)- R% P. k% V6 X' i9 }
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)1 q* C9 g" [3 X" h9 p
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)- q/ F/ ^) B/ D2 A
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
+ H2 j) E! E! ^% L A5 P
#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
7 G9 \3 Z/ j8 V* L
#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)5 P& |4 v0 Z5 [$ F" J. z3 m7 Q
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100), T, A& K. C: g7 D
#if defined(STM32F410xx) || defined(STM32F413_423xx)
+ c: u& K5 a) M
#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x00000200) }! |5 `( {- I: o6 K0 o
#endif /* STM32F410xx || STM32F413_423xx */
' N$ T# {5 N) L. c" s* r
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
6 R5 q4 {, m0 e5 b' c o
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)' M. B5 y- @. n3 C
#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000), n5 ?- O6 X' p9 |% w- [9 N5 a/ u
#if defined(STM32F446xx)7 R4 R! N0 R9 W" ^/ |. z
#define RCC_APB1RSTR_SPDIFRXRST ((uint32_t)0x00010000): t2 f [. x' f
#endif /* STM32F446xx */- H0 a* L" c( X. P5 n( Q/ @" i7 G
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)4 Q7 ]! a0 ~% ^6 `/ b
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
# S& F* o1 ]& t o3 q' s; y
#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)7 C- [1 g4 ?" c6 l
#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) K5 g5 `: p+ Y% m" V9 y
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)+ k# F7 E2 x1 P) Y! p
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)& m8 _* v8 x Y$ t. @
#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000). @& ]1 _' T1 a
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
3 M4 ]0 r/ T e/ r' e8 d
#define RCC_APB1RSTR_FMPI2C1RST ((uint32_t)0x01000000)9 v. R, Q, N+ {1 L" |
#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */" R2 K) p5 v7 a) f6 i# p% J% `7 W
#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
& `2 H* L! n1 ~! U0 f$ O' f# t
#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
! T. Z% Z% L% [$ L$ H
#if defined(STM32F446xx)
. W+ L% |9 d8 }, h C% j
#define RCC_APB1RSTR_CECRST ((uint32_t)0x08000000), O0 b# A' S: m) e
#endif /* STM32F446xx */2 c" P) P w5 A/ v/ D3 k3 _% V
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)! @* M/ Z3 `; w3 j( r3 k, s9 ]
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)+ n& A) y4 S( |( e1 Z' D2 Y3 a! b
#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)5 o3 P! p& H- j
#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
& w- u3 G$ k% P) J' Z# S& B
, y8 W$ J) Q* F5 a6 B* t
/******************** Bit definition for RCC_APB2RSTR register **************/
* h! i5 w6 b I* {2 n5 G
#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)6 z, ^$ q; t' v) r8 F- f
#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
1 C% s" l! H: U5 T5 L f, L
#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)# D. b7 B! P' P: O* i" R
#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
5 g/ L6 e2 ]% c6 R/ \0 A% C
#define RCC_APB2RSTR_UART9RST ((uint32_t)0x00000040)9 S- V0 P M& N$ u0 w' v9 U
#define RCC_APB2RSTR_UART10RST ((uint32_t)0x00000080); m* k; S: Z, \. ?8 \
#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)( k0 u( s( w. k/ l8 ]7 U* D) h
#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
. J3 i3 Y0 q$ B0 b. Y& y+ ?
#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)! a2 u- X0 V: I# |
#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)/ A7 T7 ~9 M! {4 ~* W9 l
#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)2 Z% r5 L. H) D+ @- k
#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
; u+ ^+ a" l! T% s1 V0 C
#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)/ G, b- V& v4 }6 _
#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)! @) J) D; h# k9 o6 k
#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000). f. s. i7 T' X5 {6 N
#define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
" [9 t* g( r$ x1 ~- V9 k
#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
$ X2 A% _& z4 Q* d7 u3 t
#if defined(STM32F446xx)- u+ _; l4 u C9 G# h0 ?% ?
#define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00800000)/ G( x3 F( D* ?& j
#endif /* STM32F446xx */
/ Y0 y4 x: ?% D
#define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
2 @9 G/ O& G, _/ z$ J/ G
#if defined(STM32F469_479xx)
% @/ v. E) F0 m) |
#define RCC_APB2RSTR_DSIRST ((uint32_t)0x08000000)
+ |, }% n0 o& V$ w
#endif /* STM32F469_479xx */
; K) H6 P/ k5 ]6 b
#if defined(STM32F412xG) || defined(STM32F413_423xx)
9 R2 a3 n' s9 F
#define RCC_APB2RSTR_DFSDM1RST ((uint32_t)0x01000000)
1 ]1 N6 i9 z$ Y1 k5 n8 e
#endif /* STM32F412xG || STM32F413_423xx */
6 j8 p0 j1 h- o6 ^
2 t" q9 M- z9 p1 Z( t4 S& D$ \
#if defined(STM32F413_423xx)
: t' W! n3 b9 \8 V6 Q
#define RCC_APB2RSTR_DFSDM2RST ((uint32_t)0x02000000)
/ c I' w# { y# \, w
#endif /* STM32F413_423xx */# s, [" B3 ~0 W+ g+ l
/* Old definitions, maintained for legacy purpose */- E+ G; E/ [, o( j8 r1 n4 G7 B
#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
4 J, \' Y9 ?8 V6 L% p
#define RCC_APB2RSTR_DFSDMRST RCC_APB2RSTR_DFSDM1RST' g3 t6 g% B* w$ ~: I& Q' y
! a3 p9 }. J! O4 K9 L
/******************** Bit definition for RCC_AHB1ENR register ***************/8 b) x% Y4 D, q5 K5 n& w7 }
#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
! K* M. }' j4 J) W
#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
, ^4 w$ h" p2 ]" t' F3 f0 c' ]
#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)8 K! W p8 j, }2 s# M! g4 N1 z
#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
8 G1 j$ ]& P. e( x/ |. Z
#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010) r$ A" w6 _0 h L8 c$ N
#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)5 g# l) z2 O' r+ U' J- M
#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)6 V+ Z) N$ `! Q4 H; ~# G
#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
2 a9 L6 S& [6 s
#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)4 ?/ j4 a9 ~/ ]8 p5 \( X
#define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
1 H0 n. S& q" Y5 t! u
#define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
7 n# x. l: ]1 M- V( I! M" Y
#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)% Q; a( l' A/ C. s( M
#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
% T1 H6 |. r" R: ?2 [6 q, [
#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000), [1 H# @6 v. i/ K |
#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000), i1 m5 k2 ?* X: @- K! ~
#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000); X5 M. v8 H8 [, \! H
#define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)) C! c! l: G# _1 i
#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)4 r0 S8 A. H' Z) ` n
#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)' ~/ W) I* V$ C% ]% t1 G% J
#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
, T% d. x2 p: C' k1 N5 q
#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
i9 g: D) I7 D& {& C! E% z
#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)! ]% L& E" J& e0 W5 ~. t/ r4 W
#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)$ ^" X% ^3 v6 a6 q3 O# B( O1 S
5 E. ]2 ~- c- ?9 O! H
/******************** Bit definition for RCC_AHB2ENR register ***************/
3 _# W% V3 m* a2 Y' }
#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001): e% X7 V3 c& x6 e8 _
#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
) m! j6 r/ \+ }+ }) N
#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
4 ^& Y% r# Y, t% _
#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
& y7 h2 `$ i" U5 i2 Y& I
#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
) {( k0 X* J1 P8 g/ ~! a
' x' f% O1 ?# ^6 v" U
/******************** Bit definition for RCC_AHB3ENR register ***************/% k" {7 Q( v1 o. K! k% c5 v
: q" H' f* \/ e8 c& M
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)( m- X& m/ z: h: o, f1 j' W! ~. D
#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)" b2 f; A. ^3 Z: I( O
#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */0 E6 Y; D# r1 x
: m) m, o. }: z; i' ~ ^$ A L6 e
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)4 B8 |9 Z" a+ Y; S% c/ C$ H
#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)) Y% i3 N5 C% E! r+ C: u% P4 c8 U
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
- M# u3 o% [- Q- r% H
6 f; H5 P7 h% B4 b5 ~& ^( i
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)' `3 q6 E6 ^7 E6 {7 d- s% G' I4 B
#define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)
o$ y- e* g! q
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
. m# N- m; y5 G" P+ R' E. F
m* R: ^& p( ^( D. A
/******************** Bit definition for RCC_APB1ENR register ***************/
4 Q; _% v5 d1 S+ V3 h2 O
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
7 T7 f! q! q; F( K, S' I1 B3 T
#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
7 b, R5 h2 d, Y
#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
U T: j" t( Y" ?; N
#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
( k% N! W6 `. ^2 d$ w. H1 K+ \
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
M* N6 F4 D s+ p( ~1 M4 |$ e
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
4 x8 x- T, U7 X5 \( z- q: t2 y
#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
{7 c. h& C; [3 }
#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) ^8 Q7 {- t0 @
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
7 K6 O- k1 \ E' [9 S
#if defined(STM32F410xx) || defined(STM32F413_423xx)
% S! g' A/ l& P, G* w% P- z M
#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x00000200) N- ^! o+ T/ y# [
#endif /* STM32F410xx || STM32F413_423xx */. L; b7 c1 S4 a5 h$ i0 Y0 ?, V
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)$ g* |% O; i5 G% _8 C
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000): o6 f& w: ]/ S2 S# X2 D' d
#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
( d# t' L# @: W
#if defined(STM32F446xx)3 p/ v0 O X/ V* n7 b. J
#define RCC_APB1ENR_SPDIFRXEN ((uint32_t)0x00010000)
( _7 o" b% K+ I3 @( M% |. P6 s; W
#endif /* STM32F446xx */
+ p9 I/ H+ }0 Y% G- m
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
/ R8 a4 n: I) F3 W- A' x
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
% \. a3 i8 N& r: Z1 [
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)6 j8 C f0 @0 h
#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
- W: T9 S6 w" Y1 A4 K$ B# W
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
& W- V) b+ f$ L
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)' U8 n# v" R; m" Y5 Q4 ]
#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000). T: F x" g" T/ F( D v* d
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
0 L- E1 x; i7 y6 T6 w) D% `5 p
#define RCC_APB1ENR_FMPI2C1EN ((uint32_t)0x01000000)3 W" u3 }: ^7 A2 m6 W! |
#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */# v+ h6 V+ F. I+ D
#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)% S7 Y; ~- R. E. s9 l
#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
' K' e8 s3 J$ h
#if defined(STM32F446xx)
$ L9 Z0 C* S5 J) v6 e( V2 e/ m
#define RCC_APB1ENR_CECEN ((uint32_t)0x08000000)5 l# b V! h- Y1 ]7 V: p) w
#endif /* STM32F446xx */
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
! k, Y3 p! U. _& B
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)) N: T( Z/ M: n5 {
#define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)/ X7 x- j$ ~- p9 q9 u
#define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)7 { {( M( C8 R& d; H( P
. J/ a* U' w* `' R: \
/******************** Bit definition for RCC_APB2ENR register ***************/6 }" Y0 C" F1 o0 ]' ]
#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
) Y/ G7 v5 T1 B6 \
#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)! b# x$ v: N- r" l& c( s" U( M
#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
& A' ^/ r" v3 H4 L( E8 p
#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
% t+ G, C4 v+ _! x$ n7 W$ Z. p
#define RCC_APB2ENR_UART9EN ((uint32_t)0x00000040). V0 H: B- k2 m! T6 f' a) A
#define RCC_APB2ENR_UART10EN ((uint32_t)0x00000080)
: b9 |9 ^5 h7 r* T
#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
5 I( p4 [( l [8 h9 U. ^. j
#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
7 H" z3 W5 X0 }- n9 i( ^( }: J$ y
#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
* z9 M) N7 a0 o G' Z
#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
8 d: |3 g3 P2 ~
#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)+ A/ s9 ~9 l- u* F( o
#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
$ g5 S$ t+ c6 {# J, e% |! P
#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)5 P/ x7 S5 n9 Q7 A" j
#define RCC_APB2ENR_EXTIEN ((uint32_t)0x00008000)( |' U! A$ v1 m- T {
#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)0 ?5 J! b0 M% f& j8 W4 Z
#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
0 ^1 \$ a# S8 j9 Q U3 l
#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)% [. Y4 t( a& E9 ^. r% j
#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)* m2 _0 h# U! ]6 V/ q$ W
#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)9 d2 H: u6 L( N6 f9 V) m% |# \1 ?
#if defined(STM32F446xx)& ]: d* n- m' G, N% L
#define RCC_APB2ENR_SAI2EN ((uint32_t)0x00800000). _2 S0 B# S7 m2 H
#endif /* STM32F446xx */4 V1 |5 F: p( X) h' n
#define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)" W1 B/ Q& q: o
#if defined(STM32F469_479xx)' _$ U9 h. i; H2 n/ x! {0 h
#define RCC_APB2ENR_DSIEN ((uint32_t)0x08000000)
S: ^; s; L9 T8 `/ [+ h
#endif /* STM32F469_479xx */
& D0 d# ^7 w! i" i
#if defined(STM32F412xG) || defined(STM32F413_423xx)$ B: d6 E0 f" A0 ?; @
#define RCC_APB2ENR_DFSDM1EN ((uint32_t)0x01000000)
# U" |9 ^7 J" I. n3 p
#endif /* STM32F412xG || STM32F413_423xx *// S; m- Z7 m& f' h/ D5 f$ _* S7 z
#if defined(STM32F413_423xx)
+ z! e1 ~; i! S+ ^
#define RCC_APB2ENR_DFSDM2EN ((uint32_t)0x02000000)
( Z4 ?" A5 D. N# ?/ w
#endif /* STM32F413_423xx */
0 @8 z" l" j2 O' z: x* c4 k# v- }
/******************** Bit definition for RCC_AHB1LPENR register *************/
( ?# K$ @' U. _( ]$ Y& O2 n
#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)$ _7 f: j2 ^; q5 `0 w; ?7 ^
#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)6 ^1 ` D v2 r
#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)- Z- F* f1 Z: L2 f
#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)- n0 n7 }9 M/ d
#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)* C. E) P- S4 s8 |' ?1 E* r
#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
, C& V+ t1 ~1 K1 Z$ b6 m
#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)( S4 S: s, \0 o
#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
7 m# f2 c1 [2 \; ^ M
#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
7 ~) H: Y/ g |7 A% B3 ]- ^
#define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
" ]+ a. `2 l2 k/ X* {& i5 b3 K, E
#define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)0 O/ I2 r) E9 L0 y5 v( o1 j
#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)+ H G D4 k; W& b
#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)* o% f. P! ^9 L2 K B" d) G
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
. C4 M; K% Y+ x! k7 e# N1 D% C: _
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)/ p2 Q% r' D2 U6 ^: b6 |3 n
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
& q2 b$ ^ U# _5 a& @: h
#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)( ~2 T8 O$ I/ M% D/ [
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)! y( y a( F6 D8 L+ C( @
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)$ i2 ^ M: {' b
#define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
5 I, H9 Q% Y6 A( q
#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
6 n4 q( k3 M5 K- @: ~
#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
8 e" M* e+ }, P4 W+ ^
#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
1 t' X( e G4 Z
#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)( L) \" ^- x( z6 [- i G% o- p4 n! b
#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
* W* w6 t3 `, f* [& R& W: I' `
#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
& r$ Z! B/ f+ l0 ~4 v1 f; N( l
1 O. K* H" I: A- R% r$ `+ Z
/******************** Bit definition for RCC_AHB2LPENR register *************/
% m7 M% \) K" v1 y
#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
4 X. k2 x7 J( B; e+ H* E O
#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)8 P* [4 y# t7 T1 h: K, b2 }
#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
$ L6 J9 M. P" w$ V* z3 Q
#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)5 E5 T" n6 u4 B. {+ N
#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)2 A; n) {& G9 @
9 m# t4 G1 N# }2 v
/******************** Bit definition for RCC_AHB3LPENR register *************/
5 i$ l: m9 D5 R$ Q% n
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
% J+ o M5 n4 W k. Z! u
#define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
8 P$ R' n9 O! p0 S3 j$ Y
#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */4 @* m4 j, V6 Q
5 }! U: w: l9 W# n' @; Z \
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx). z* ^) y# e* k3 s$ I, `; H
#define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
( j6 x5 t7 W& g- y6 N: x
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */9 o" Y8 z, q) q" s1 C
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
- y! }* k1 m ?: F" {# g4 [) [7 `2 [
#define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002)
b& V( d3 a- m5 n0 X3 d6 \
#endif /* STM32F412xG || STM32F413_423xx || STM32F469_479xx || STM32F446xx */
) L4 T( H& Q! l4 W/ A, M
( b+ `1 P; u' H, S0 ~9 M5 J8 k
/******************** Bit definition for RCC_APB1LPENR register *************/
) X8 [( P6 x' z+ d6 z5 A4 U
#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
* v- ] `2 r- S
#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)# U. n, {2 p3 s! b
#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004); L1 R/ i) U0 P6 z7 y; h% O: ~4 f
#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
0 o9 } F# N: @0 { ~5 Q
#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010): f6 ~5 Y# @; a3 ~3 _
#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020), D) k2 v- O3 ?7 o2 Y, E# U
#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040). Y3 s9 Y- d* ~4 C
#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
! h5 o+ c( L% {+ ]$ b: j
#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)+ F* o' Y0 y g7 R
#if defined(STM32F410xx) || defined(STM32F413_423xx). O1 V0 ?% N# s2 z# j
#define RCC_APB1LPENR_LPTIM1LPEN ((uint32_t)0x00000200)4 X: S3 I3 B* U2 b9 S
#endif /* STM32F410xx || STM32F413_423xx */
, H8 b; W0 O. f, Y6 C
#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800). B* d- H6 m( O$ W- d( p
#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
$ K2 e( j; B7 H: m( [% T* z+ B% n2 `
#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)1 e9 ^. F( p3 K7 [* r6 x- B
#if defined(STM32F446xx)
6 q3 q9 }3 e, @$ E" a; N- P# O2 L
#define RCC_APB1LPENR_SPDIFRXLPEN ((uint32_t)0x00010000)
5 d/ m& a2 [5 S, Z( ]
#endif /* STM32F446xx */
/ a) _8 t, o, c6 k* I' ?
#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
R: ]; P0 ~# \7 M( l! t
#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
g* J1 S* t& G: U4 `
#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)! p$ Z' V( M: j, C, }# e2 S* J; Z
#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)/ j# v$ `4 [8 D" e4 q: m% ?
#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)# ?) U0 y0 [4 T
#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)8 A8 v! ^# t. W4 K, Y; R
#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
1 ^6 R. X& W! a9 Y! E
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
7 w P, H+ I+ Y6 L/ j0 {4 q) O# r
#define RCC_APB1LPENR_FMPI2C1LPEN ((uint32_t)0x01000000)
( S3 q) i3 O1 {
#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
8 Y, h! Z2 n& b0 N. J9 | ?' s1 ^
#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
- K% E I( Y. [5 L, \
#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
& i& g! e1 P& _+ { |% ]$ D# e
#if defined(STM32F446xx)8 d0 f5 J! r9 F
#define RCC_APB1LPENR_CECLPEN ((uint32_t)0x08000000)1 s, x0 t1 c! d
#endif /* STM32F446xx */0 M! a) _& |7 Y3 R9 o" H2 `
#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)5 _( `( p- B* j1 ?8 C
#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)' `4 }3 ?4 ~6 S" x9 c
#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
" z' s# w ~$ B( q. @. e
#define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
8 g( d1 k7 w& H- G7 @0 r1 k- K
) L6 b& B1 t$ J
/******************** Bit definition for RCC_APB2LPENR register *************/8 t1 ^/ H# T* K f
#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
( ~" C' Y7 Z. } U3 C
#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)! G! u' n% U( r* l' f' K% o6 i! F2 o
#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)# x% M: A5 a/ ^) V0 N3 c5 q
#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
8 P5 ]4 m' o X2 ~' g1 w' p
#define RCC_APB2LPENR_UART9LPEN ((uint32_t)0x00000040), v( A9 Y9 Y1 g6 F5 c/ [% H; x2 ^
#define RCC_APB2LPENR_UART10LPEN ((uint32_t)0x00000080)
9 z" L; \6 n% ]* J+ s6 ?3 \
#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
* |" Q4 c: C9 Y2 n# s$ D2 g; V$ v
#define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)
5 q0 _ r u' N( |6 C
#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
V) p% t1 H5 ?2 j6 [
#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)% S% m: W( [5 Z. _" c# u0 v3 M
#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000), }4 G3 l2 Y* a+ a; j, c
#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)4 _ }: Z" q5 H% l. l% W
#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
( \" F" u: C, ?& ^3 c) G
#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
8 G' e& u" C) s d4 N/ u/ J Z
#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)# V! l4 A/ k6 M3 l v
#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
( y) \% q" j3 F: r( o5 D2 Y& _ }3 q
#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)) d% g" {! a/ M4 o; c
#define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)1 J ]3 Z0 I" n$ L% B2 O
#define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)' m4 D% Z M: {/ }& W* D
#if defined(STM32F446xx)
' S4 |: a7 }- F5 A" ]# q/ X; l, z' \
#define RCC_APB2LPENR_SAI2LPEN ((uint32_t)0x00800000)7 t7 g. N% F5 ~
#endif /* STM32F446xx */
$ i- M/ l3 L7 j/ @( n0 b/ I
#define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)3 N9 K5 q7 P$ p
#if defined(STM32F469_479xx)9 f" _+ l3 p" |& h
#define RCC_APB2LPENR_DSILPEN ((uint32_t)0x08000000)+ a( c: g8 n% g- y& m- ^+ K" q
#endif /* STM32F469_479xx */
: v( C5 C* b, T- P$ ]( K
#if defined(STM32F412xG) || defined(STM32F413_423xx)
$ ~: D7 r6 D: r0 H& k
#define RCC_APB2LPENR_DFSDM1LPEN ((uint32_t)0x01000000)
5 h0 t& u1 L* C+ q4 z. i \/ z
#endif /* STM32F412xG || STM32F413_423xx */, u" G8 C. y. E; |" q
#if defined(STM32F413_423xx)# u! x) j1 L* E6 v x, r5 G
#define RCC_APB2LPENR_DFSDM2LPEN ((uint32_t)0x02000000). Z" `( _0 r& `. R
#endif /* STM32F413_423xx */8 I+ r4 T, J- C6 b8 S8 W
3 ?( Y6 w7 w i! A* `+ V
/******************** Bit definition for RCC_BDCR register ******************/
+ G* X8 ^ ?+ _( s6 O
#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
. |* d5 w6 {$ p/ r* W7 A
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)2 N: H: @0 ^5 L6 A7 Q7 e
#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
4 K# v- F1 [+ h' F6 I& s" o
#define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
- p1 b( S" g0 R4 V/ _0 G7 C
! Z% M6 M6 h' a% y) `
#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
+ h) ^# ` n* T+ m+ p
#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100). U' ^" B8 k& f+ ]
#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)$ K+ B3 d$ ~) G1 m" }5 M
1 {; P/ [* |; C2 f, C2 z8 f
#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)8 x2 B% B( G+ u( J( ?0 P* F" A
#define RCC_BDCR_BDRST ((uint32_t)0x00010000)$ S6 i0 b; z2 c3 @" d5 t6 H5 l+ a
7 m2 w6 b! x7 ~# a8 N9 W6 ~
/******************** Bit definition for RCC_CSR register *******************/
+ X+ P3 e& X, k- `/ U9 c8 s
#define RCC_CSR_LSION ((uint32_t)0x00000001)
; @1 I# G+ A, |* d
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002): j' t7 |1 U. H, Y( r! S) b
#define RCC_CSR_RMVF ((uint32_t)0x01000000)
4 v- z& e" q+ t9 p0 m* u1 H0 [
#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
) P C* O2 m/ e9 `/ ]
#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)! j3 M* Y- |; U4 ^: Z5 b" p3 j
#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
% x, K* C! b! u; N2 X1 K& w9 `
#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)4 D4 ?- v$ x' G
#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)7 @/ R' Z g8 C( H% o6 Y
#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
& ~1 ], ?6 T( U2 X4 m n
W [' l: W9 L# W+ S& W
/******************** Bit definition for RCC_SSCGR register *****************/7 Q3 |! v- d& E
#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
+ T8 s7 C- @% k! _( u9 m
#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)6 G* a& _2 X$ z' n( W+ [) c: o1 |
#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
2 O/ c) L8 [2 y# H
#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
S/ J9 |! V4 [) g- _3 \. i( U
. M1 ]& b6 E6 f' h% P
/******************** Bit definition for RCC_PLLI2SCFGR register ************/
. q! ]' M2 c: T5 E; J
#define RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F)
+ V* a' x3 U4 ~/ W; F, D
#define RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001)8 R5 r3 g- |4 P$ @$ l4 ^
#define RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002). Q b9 e( [0 `+ V
#define RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004)
8 \ w2 s4 m6 [9 m. X, J
#define RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008)
8 P3 s, v5 I/ |/ m6 J
#define RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010)
$ m `% n1 T0 s& @4 a
#define RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020)
# `4 _2 q* d& |
, L! t. p2 }- N% U4 l
#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
5 z4 d8 t% Z3 F4 c+ J0 C) \
#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040) ~- B8 {: j8 b* j' [5 |
#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080). d6 j) r9 f; B, t, f1 V1 ~
#define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)& b4 T' `1 q. N
#define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
: t, Q2 `! ]7 l/ d( j
#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)& X6 b9 G, w3 O
#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)1 u) X3 Z3 e9 q. n
#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
6 D* x3 [! {" k; x6 Q
#define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
8 k) C+ m/ R) ~' e+ z. K7 f
#define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)* ~5 \ W# a" q8 ]" M! D' Z9 a
+ G% h) n7 ^# o! P, t# {
#if defined(STM32F412xG) || defined(STM32F413_423xx)
3 k8 J. u% I; k
#define RCC_PLLI2SCFGR_PLLI2SSRC ((uint32_t)0x00400000)
3 `' p% o, Z- U6 W0 j) h+ o
#endif /* STM32F412xG || STM32F413_423xx */
V% G; Y6 D+ b1 l; [: F
! P; O9 j% y# n* Z5 S; @
#if defined(STM32F446xx)
% Y6 h g5 H, N4 V- F* x: R% C+ _
#define RCC_PLLI2SCFGR_PLLI2SP ((uint32_t)0x00030000)
; o$ i! f9 f3 |8 [# H: V) O
#define RCC_PLLI2SCFGR_PLLI2SP_0 ((uint32_t)0x00010000)
0 n |5 m3 o) ?3 x5 W) M
#define RCC_PLLI2SCFGR_PLLI2SP_1 ((uint32_t)0x00020000)1 H# w- i8 T2 ]. f/ M0 m/ Z
#endif /* STM32F446xx */
; w1 C- y" Y9 D x: n5 G" h% ^- d0 Z
) [7 t- J! ^3 w$ o' Y& b
#define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
9 t/ q/ b: Y3 c) j
#define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)2 D4 m V' d" ]
#define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)* B% F( @8 V% ^- G
#define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)5 @' \. n0 I) C" K7 z- L6 n
#define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
" x( p5 P- ^5 W2 u/ P9 ~ h
. P3 T1 L( ~+ f1 B# g$ i- k' C, u
#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
5 w- K# n9 f7 |
#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
# w0 t0 H" G3 W3 X* U' F7 {9 b9 y
#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)6 k! O# i% K% ?3 Z6 J0 l+ S
#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000). i' M5 ~$ ^- x% K2 K6 l
) J8 D+ t l3 }
/******************** Bit definition for RCC_PLLSAICFGR register ************/
$ B% T9 n$ N0 | j
#if defined(STM32F446xx) H' \: A6 _; y9 B# T% E9 q
#define RCC_PLLSAICFGR_PLLSAIM ((uint32_t)0x0000003F)( @" Y$ x/ I7 m6 ~+ M2 a
#define RCC_PLLSAICFGR_PLLSAIM_0 ((uint32_t)0x00000001)5 b- l8 I" b- q8 n2 U' M0 C
#define RCC_PLLSAICFGR_PLLSAIM_1 ((uint32_t)0x00000002)
|+ F; X& g' @& O H3 D: ^
#define RCC_PLLSAICFGR_PLLSAIM_2 ((uint32_t)0x00000004)
, l. t8 P! X# _& B
#define RCC_PLLSAICFGR_PLLSAIM_3 ((uint32_t)0x00000008)
* q; t2 s* z) z0 A, U) e2 Q+ N @
#define RCC_PLLSAICFGR_PLLSAIM_4 ((uint32_t)0x00000010)
3 L- w1 f' F' w) f1 Y- \
#define RCC_PLLSAICFGR_PLLSAIM_5 ((uint32_t)0x00000020)
7 `7 ^- {9 T, H
#endif /* STM32F446xx */
9 u. z" D5 ?4 K5 M$ o% z! u) D
1 ~) c/ p: G5 |1 G' V! N
#define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)0 I& u. R+ f Y% F3 [7 h
#define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)8 X- T2 _$ i) e6 I2 M- y" V$ H
#define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
5 E! a/ j: I8 l# L$ ]
#define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
Z3 |7 ?0 Q: s2 R; {$ w2 U, B# j
#define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
; M8 W9 c& H& R! E, h
#define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400), c& i C0 c. U& l+ }
#define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
* Q2 {, Q2 Z A3 ]' S0 k' W
#define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
5 H/ C( J9 o) D% y9 C
#define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
, O, J* V2 |# h' L
#define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)4 e" C* i" C5 u
0 f8 D/ P3 f& i( L- W, Y: Q# R$ y
#if defined(STM32F446xx) || defined(STM32F469_479xx)
9 U6 D4 m; |$ |5 {. O6 }
#define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)" r1 j, q: V( O# ~( n }
#define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)
% A( V* Y7 G; P" f1 Y! T( Z
#define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)9 s9 |. o8 S2 v& e9 d0 p
#endif /* STM32F446xx || STM32F469_479xx */
1 ^( q: k$ {, ?
9 X! U/ p% Q# i7 `2 q2 y
#define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
5 S! |: p! |" ?+ b
#define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
$ H; V; N' U8 ]3 b
#define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)# j. q: k: m' j$ W; Z; k) c0 c( D
#define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)5 n: A" P! H$ a+ O, ^5 y
#define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
2 }9 A9 G0 D- [" q
" Q9 Y3 {, ~# \$ V
#define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)2 t2 x. C) M4 z/ \8 a) W
#define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)
7 B$ e% r" {3 Y
#define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)
5 |. P6 x; s9 _
#define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)
. m( {; }% }% S. n
* d& S+ s- L& O' P
/******************** Bit definition for RCC_DCKCFGR register ***************/
& c' U$ `- c" @+ `9 L2 _5 M
#define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)
6 K9 o5 j. ?; b5 T* |
#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)0 o# H. F) L2 v* }- v7 p& ]1 q
#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
$ d/ _, ?8 G' W8 v- r6 }8 w0 q
( V, M, {: x9 f& ?, {, y1 d7 O
#if defined(STM32F412xG) || defined(STM32F413_423xx)
0 V9 w1 T+ V0 t d; i4 `# F
#define RCC_DCKCFGR_CKDFSDM1SEL ((uint32_t)0x80000000)
6 k+ |5 ^7 v% B3 {
#define RCC_DCKCFGR_CKDFSDM1ASEL ((uint32_t)0x00008000)* ~. Q" G4 e4 y) S
#endif /* STM32F412xG || STM32F413_423xx */& g/ J1 ?. {1 N% q8 g) T
# o X& r8 o8 V- f0 X
#if defined(STM32F413_423xx)
5 E% i$ u9 L4 C0 s: q
#define RCC_DCKCFGR_PLLI2SDIVR ((uint32_t)0x0000001F)
' L2 C* Q; V6 k, G" a
#define RCC_DCKCFGR_PLLI2SDIVR_0 ((uint32_t)0x00000001)6 D( J v$ C# {% h" v% M4 f3 k' \
#define RCC_DCKCFGR_PLLI2SDIVR_1 ((uint32_t)0x00000002)' w9 Z1 Z& N" ~+ B b
#define RCC_DCKCFGR_PLLI2SDIVR_2 ((uint32_t)0x00000004)
H+ H3 |# }! M& L. j+ z+ |
#define RCC_DCKCFGR_PLLI2SDIVR_3 ((uint32_t)0x00000008)6 I/ _& P3 [/ g; Q" {6 Q
#define RCC_DCKCFGR_PLLI2SDIVR_4 ((uint32_t)0x00000010)
\1 K% A. P$ s R. |
2 f( n- L3 P8 V3 p% y4 E6 c9 v
#define RCC_DCKCFGR_PLLDIVR ((uint32_t)0x00001F00)6 n9 ^0 r+ C0 N+ G3 T; o
#define RCC_DCKCFGR_PLLDIVR_0 ((uint32_t)0x00000100)$ {1 B. Q" }+ \2 w
#define RCC_DCKCFGR_PLLDIVR_1 ((uint32_t)0x00000200)2 z4 T5 {1 v/ ]9 O. q, ]+ x3 J
#define RCC_DCKCFGR_PLLDIVR_2 ((uint32_t)0x00000400)
$ G% D8 G. ~8 z) v: D7 ~
#define RCC_DCKCFGR_PLLDIVR_3 ((uint32_t)0x00000800)- j9 P( R, g& d7 P
#define RCC_DCKCFGR_PLLDIVR_4 ((uint32_t)0x00001000)+ K8 D& ?5 M0 P
#define RCC_DCKCFGR_CKDFSDM2ASEL ((uint32_t)0x00004000)
: G: [. G, u6 P8 n) X/ V
#endif /* STM32F413_423xx */( Z0 p1 O# f F- ~, }
2 B- q P, T* }0 O1 b
#define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)& j) v3 y+ p$ I; Q% @5 R! E1 `# p
#define RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000)
) t$ h$ i) e5 ^+ C# `: T, x
#define RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000)
3 a3 u; G% `& Y/ d( J# u* N
#if defined(STM32F446xx)
5 q: p' f+ x. ~* K
#define RCC_DCKCFGR_SAI1SRC ((uint32_t)0x00300000)
' q5 i$ ~% o/ F/ U
#define RCC_DCKCFGR_SAI1SRC_0 ((uint32_t)0x00100000)
" M$ U) `7 ?2 d$ ^& ^
#define RCC_DCKCFGR_SAI1SRC_1 ((uint32_t)0x00200000)/ N' @6 r$ r5 M
#endif /* STM32F446xx */' G9 }& Q3 I* c: x0 h/ T: R
. e$ h% B1 R" s* C% |
#define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)" S5 O m& G1 B
#define RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000)
) N9 z. B- a: q- k+ H6 b; u8 i2 K
#define RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000)
. L( X& Y: i( L, E, R9 C
#if defined(STM32F446xx)) o+ \; N. ?5 A& I( w' d
#define RCC_DCKCFGR_SAI2SRC ((uint32_t)0x00C00000)5 _- h% |" q0 s1 g) A
#define RCC_DCKCFGR_SAI2SRC_0 ((uint32_t)0x00400000)
$ R- z# P/ w; B0 C
#define RCC_DCKCFGR_SAI2SRC_1 ((uint32_t)0x00800000)+ i" }. Z: S" B6 a
#endif /* STM32F446xx */' ~ y* y2 {7 t' c q i
7 A% L6 A/ U7 k+ z
#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
& C8 F; I' A# ^) F- a5 r3 t
#if defined(STM32F469_479xx)
! h7 A$ D6 D v+ z4 H8 x. S
#define RCC_DCKCFGR_CK48MSEL ((uint32_t)0x08000000)
' l* ?& V7 y# V
#define RCC_DCKCFGR_SDIOSEL ((uint32_t)0x10000000)- T7 G& B, l+ y8 F+ |
#define RCC_DCKCFGR_DSISEL ((uint32_t)0x20000000)' S6 f I) h( }4 o) z
#endif /* STM32F469_479xx */
: l' d, ~% E+ N3 R) v2 C. f! i" J
) N" }/ Y- N- z, J2 X) J
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
4 U2 D5 q# |9 t F3 E5 u' l$ U
#define RCC_DCKCFGR_I2S1SRC ((uint32_t)0x06000000)
( |( a; R" R/ Y# y5 A
#define RCC_DCKCFGR_I2S1SRC_0 ((uint32_t)0x02000000)4 o' @& ]. T9 Y3 q- e
#define RCC_DCKCFGR_I2S1SRC_1 ((uint32_t)0x04000000), Y& ^( O' ?" U. Y
#define RCC_DCKCFGR_I2S2SRC ((uint32_t)0x18000000); @! V$ e; W( \4 a3 g6 V
#define RCC_DCKCFGR_I2S2SRC_0 ((uint32_t)0x08000000)
5 E( |5 J9 N ]+ H' |4 q O) U
#define RCC_DCKCFGR_I2S2SRC_1 ((uint32_t)0x10000000)
' M0 s# b' x: {, z6 k$ @# M
{) K, q4 O* N. w! H- A
/******************** Bit definition for RCC_CKGATENR register ***************/3 |( C1 |1 @ X# r+ o
#define RCC_CKGATENR_AHB2APB1_CKEN ((uint32_t)0x00000001)
+ I% V' e& {6 h4 s! p
#define RCC_CKGATENR_AHB2APB2_CKEN ((uint32_t)0x00000002)
6 B8 A& _! Z. M5 I8 N) w! N
#define RCC_CKGATENR_CM4DBG_CKEN ((uint32_t)0x00000004)
* x6 P" s1 s% X% I6 u! c
#define RCC_CKGATENR_SPARE_CKEN ((uint32_t)0x00000008)
" w7 y/ x! w3 T2 z: ?! P% j$ O
#define RCC_CKGATENR_SRAM_CKEN ((uint32_t)0x00000010)
/ ]7 c, _8 G9 |, \1 i
#define RCC_CKGATENR_FLITF_CKEN ((uint32_t)0x00000020)! \5 Q I3 C9 L7 t; W' V) H
#define RCC_CKGATENR_RCC_CKEN ((uint32_t)0x00000040)3 \3 Q" I' J# f0 e% }5 @: m5 T6 u
#if defined(STM32F412xG) || defined(STM32F413_423xx)
, Q% b5 O1 S6 {, [
#define RCC_CKGATENR_RCC_EVTCTL ((uint32_t)0x00000080)
+ ~! b \( |! y. ]) x1 T5 x- r
#endif /* STM32F412xG || STM32F413_423xx */
7 x3 R0 j3 s0 J+ V/ ~! R7 l. R
1 `- j4 o! h! {5 x( X
/******************** Bit definition for RCC_DCKCFGR2 register ***************/- t. s# H! W8 W
#define RCC_DCKCFGR2_FMPI2C1SEL ((uint32_t)0x00C00000)
" r8 p7 m) D+ G: T1 @5 b- A4 ^
#define RCC_DCKCFGR2_FMPI2C1SEL_0 ((uint32_t)0x00400000)! `. G5 V, g/ X, r) U
#define RCC_DCKCFGR2_FMPI2C1SEL_1 ((uint32_t)0x00800000)% ~! L2 V! j+ j
#define RCC_DCKCFGR2_CECSEL ((uint32_t)0x04000000)
! t# @5 v+ L7 \1 q2 l
#define RCC_DCKCFGR2_CK48MSEL ((uint32_t)0x08000000)( [& G- t; L% V/ Q) L9 q
#define RCC_DCKCFGR2_SDIOSEL ((uint32_t)0x10000000)
/ k9 |9 I0 v8 y$ O# d
#if defined(STM32F446xx); W" D) ~& [' Q4 e' F6 F0 M, Q- P
#define RCC_DCKCFGR2_SPDIFRXSEL ((uint32_t)0x20000000)
4 E0 V8 n1 ?+ C% m* D! i5 U
#endif /* STM32F446xx */
3 y4 }, q5 ^ o" A. m9 d
#if defined(STM32F413_423xx)
4 B3 f! N2 D- i
#define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0xC0000000): p) G# M( I2 I" Q
#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x40000000)
& G$ v3 t5 d. e/ z
#define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x80000000)
# R' |" j, J" d. s; D; @
#endif /* STM32F413_423xx */5 Y6 p0 ]. ?( N- Y0 v! L( o
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
z# R( W% i% M3 [; L% ^
8 W$ }# V" @, R
#if defined(STM32F410xx)$ K2 O: a# I4 z; M. d) j
#define RCC_DCKCFGR_I2SSRC ((uint32_t)0x06000000)/ L# f- T$ a J- ]$ ?) H
#define RCC_DCKCFGR_I2SSRC_0 ((uint32_t)0x02000000): f5 n0 e# b. s4 n" g# J5 L
#define RCC_DCKCFGR_I2SSRC_1 ((uint32_t)0x04000000)( W) l; O/ e; A, }
#endif /* STM32F410xx */
6 A$ L1 y# P5 [7 |) O
$ n# |7 P" b, i% X S! J
#if defined(STM32F410xx)1 {% ] g3 Z( o& s" g! Z4 I
/******************** Bit definition for RCC_DCKCFGR2 register **************/
* Q2 e/ p- ]5 c9 m6 R7 d
#define RCC_DCKCFGR2_FMPI2C1SEL ((uint32_t)0x00C00000)
+ o, A* c6 y& A- c+ ]
#define RCC_DCKCFGR2_FMPI2C1SEL_0 ((uint32_t)0x00400000)
9 a2 u/ ~" X/ R) _: i
#define RCC_DCKCFGR2_FMPI2C1SEL_1 ((uint32_t)0x00800000)
/ X2 w' V* c1 q, x3 g! W k
#define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0xC0000000)
" }' P% I- O5 ]' E7 y6 g$ Y/ C, k, Y
#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x40000000)
6 j, F, X6 V4 h5 P* e
#define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x80000000): Z$ E4 G+ u8 I P" p
#endif /* STM32F410xx */# e) q+ s0 x6 Q X