【经验分享】STM32 时钟相关函数和类型

STMCU小助手 · 2022-06-10T12:14:21+00:00

01. 概述 ' z9 G- h. D& U5 u; h+ O& Y在 STM32F4 标准固件库里，时钟源的选择以及时钟使能等函数都是在 RCC 相关固件库文件 stm32f4xx_rcc.h 和 stm32f4xx_rcc.c 中声明和定义的。大家打开 stm32f4xx_rcc.h 文件可以看到文件开头有很多宏定义标识符，然后是一系列时钟配置和时钟使能函数申明。这些函数大致可以归结为三类，一类是外设时钟使能函数，一类是时钟源和分频因子配置函数，还有一类是外设复位函数。当然还有几个获取时钟源配置的函数。 5 j3 n* Y7 ^' u9 w$ z( ~0 e ) W) T) r, t) c8 B" l. b0 u . B6 T+ d' R0 A. P7 M0 `' I02. 相关类型 . u5 w3 P+ L5 mRCC_ClocksTypeDef/* Exported types ------------------------------------------------------------*/$ x9 T# {1 n2 c4 O7 H( y8 ?# G typedef struct : S/ q' C! y- y* b3 S& |" ]{ ' E+ s5 |! c5 ~% S8 e, e uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ ( e& c0 u. w! I% X/ M uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */; t% p+ ~+ X+ t; T: b uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ ! t7 Q( y" F2 w7 l& Z uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */6 Y5 M. w/ ?! Y7 {- _ }RCC_ClocksTypeDef;复制代码0 y' {& N. |/ X: R7 J b0 r& P S @+ n RCC_HSE_configuration3 L$ u' F9 _- M% u5 f/ I, Q /** @defgroup RCC_HSE_configuration : l! k/ q$ H& }2 B Z, a" M * @{ ; m* d% N# z# ^, l; i! V */1 [% x2 F2 e' J3 O# ~ #define RCC_HSE_OFF ((uint8_t)0x00); ~7 u; }1 d: b G3 v" ^7 q. c #define RCC_HSE_ON ((uint8_t)0x01) ! I! o! N4 [+ d#define RCC_HSE_Bypass ((uint8_t)0x05) 2 o5 L! R* \0 H#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \+ j5 H2 ^1 _, q6 a; V% W. Z ((HSE) == RCC_HSE_Bypass))5 f# M6 [4 w) d" ~) U! J( O 复制代码 - t( F R' {. X) B& bRCC_LSE_Dual_Mode_Selection" G1 x* v* {, k$ l- @ /** @defgroup RCC_LSE_Dual_Mode_Selection 2 P2 q0 _& U7 w9 F * @{7 J6 {5 g% E- `: z1 R2 s( x */ t: Y$ i! K% b& |#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) ( d c/ V* [. z! V#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) ( Q" M5 @& a, p3 f1 @3 w, S/ \#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \8 ?8 k' n: v. K- S+ p9 ? ((MODE) == RCC_LSE_HIGHDRIVE_MODE))复制代码 . m: m$ x0 A, M- pRCC_PLLSAIDivR_Factor% M# y3 L8 V; p) n4 K /** @defgroup RCC_PLLSAIDivR_Factor, b7 g: r4 u) b3 I# X& k * @{ % G: j6 y K+ [& z6 j) q, y+ f */1 n2 ]2 ? @! r( p! u5 j9 R& b #define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000) 9 a* r0 q9 s! [9 c8 U#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000) X" |; T- ~& `: c #define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000) ) E9 ?6 [ \8 X R# z! u8 E# P#define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)) s, e/ Y/ a+ f$ v. Y+ g #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\) S& R4 F4 y% g5 |: ^ ((VALUE) == RCC_PLLSAIDivR_Div4) ||\ ( `# x- O9 _6 H# h$ C ((VALUE) == RCC_PLLSAIDivR_Div8) ||\ 2 W# e% \. t H7 k0 K8 f ((VALUE) == RCC_PLLSAIDivR_Div16)) : U3 k% t6 g6 [. Q. F复制代码1 `# f; X( |6 C, u6 N* e+ x& b5 b 5 Q& @( e: F3 ]* V; S$ uRCC_PLL_Clock_Source . b6 E- J1 q5 O7 l0 Y/** @defgroup RCC_PLL_Clock_Source h: U% h) A* c3 I9 u, [' \: v' @1 k& Q * @{' O( n" s) z5 Q8 j( j/ j */6 {2 v. ]+ _5 w #define RCC_PLLSource_HSI ((uint32_t)0x00000000)/ x$ ]3 p( T" I, t. M( B. p #define RCC_PLLSource_HSE ((uint32_t)0x00400000)/ a1 X8 u+ d6 j7 x8 g8 y #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \4 t$ ]5 G" H* J& Q- a ((SOURCE) == RCC_PLLSource_HSE)) + z* R" a; F; I/ R#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) 7 Z' x+ f) n8 W* m' t#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)), ~8 t0 P4 N+ @9 _ #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || + v' h8 c" a8 P/ [% a ((VALUE) == 6) || ((VALUE) == 8))- ]( q; s' |1 Z2 N7 H #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)). C$ S) [3 Q+ d; a+ K# ^. f& D3 w. Q8 c #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) 7 k2 i* c' Z* ? || defined(STM32F446xx) || defined(STM32F469_479xx) 2 |' x1 h% k2 Z# W* V1 l' b#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 7 {/ E2 r- Y- _ V$ {8 }9 g0 B#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx - @8 b9 T5 A! q% ]; m* i|| STM32F469_479xx */6 i) t) o1 A$ M% J) z) C: { # e5 t2 e1 Q* C#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) % t% D( D9 ?: d+ E4 A#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) , H8 d) w% Y, D! J+ j6 D) D- z#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))/ `$ b- t1 i6 l7 s: w+ ?$ j- a( a; v/ w #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))% X$ U0 r H W+ b1 g, f+ P #if defined(STM32F446xx) ) a9 V4 ^0 Q9 r. ?& G #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) 8 `# X0 M% ?' D) X4 q || ((VALUE) == 6) || ((VALUE) == 8)); [- f9 u: {. _1 x8 ]1 Z #define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63) ( K5 D# I$ H) C/ b" w/ \#elif defined(STM32F412xG) || defined(STM32F413_423xx) . H1 j/ Z3 i4 W2 F#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) ) b" H; d: o$ n& M || ((VALUE) == 6) || ((VALUE) == 8))2 D% O& \' \/ w% v #else 4 D! Y. i l$ T: }* N#endif /* STM32F446xx */- ?/ g {6 d8 y, m #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) $ Z' L9 Z( N9 x( H8 R; ~& U#if defined(STM32F446xx) || defined(STM32F469_479xx) - j3 W' [# W9 k# j! K* U#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) % p3 X3 }" `1 x% T || ((VALUE) == 6) || ((VALUE) == 8))7 U2 a4 l( }! ^ #endif /* STM32F446xx || STM32F469_479xx */$ w* ?) e4 o" w8 _ #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) ' l( C6 k- ]7 b* @#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) # q! V$ H1 U) q, d) q) ^ ; A* |- Y( N) s. K5 o" q#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))4 S# G3 |- I8 m; ~8 H* O #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) " v, T4 m& H; p& }1 s" n6 Z 6 C" Q) [) G5 R9 e#if defined(STM32F413_423xx)0 I/ V" Z0 ~ `6 k0 H: [9 o/ z9 \ #define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) 1 {1 O2 `+ R6 q- c; ?* T5 f#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) & f* o4 F* D/ p ]#endif /* STM32F413_423xx */# ?7 O' C1 g# |& ~1 C 复制代码" ]6 h4 O4 u! g1 M RCC_System_Clock_Source ( S' w& P8 f* i- h* d/** @defgroup RCC_System_Clock_Source n6 E7 d! m" r, M9 D * @{ . f0 F+ I( F8 A) b. M! s( h */ # B% x% P) a9 {! L' d8 `% M w0 I/ }3 p! O, h' G& v! N: h #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)/ @4 m+ r; e3 N: q0 i #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)- J% I, J4 f% q5 I* L. `1 k% R4 N #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)6 s$ ~. |; E/ \8 q9 R. l/ U0 ~/ a #define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002) 3 }( r) V2 Y$ t' A( [#define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003) # ]' S Y8 U9 K0 o* A9 l#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ ) r6 d' ]! _: x9 k* h ((SOURCE) == RCC_SYSCLKSource_HSE) || \- ]9 p! P3 x% u1 U4 Z# M4 v. c8 C ((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \ * J& P6 J) l) w9 X0 F ((SOURCE) == RCC_SYSCLKSource_PLLRCLK)) }5 @/ r; T3 \( a /* Add legacy definition */! K/ {/ b& z+ O0 ? #define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK : a- M# \7 z; y k- _, T #endif /* STM32F446xx */. p) n1 C L! @ 8 u9 P# @: @% [ #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) a$ |. v3 p) b, c || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) 0 X; A5 t7 X& t* k0 F5 k! H6 a || defined(STM32F469_479xx) : U1 ]/ P0 P' h1 q6 g#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)- P _8 I/ q7 C+ p2 J+ L #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)9 O4 x. k7 a7 g6 B6 a; z8 I #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) ) X# F: L; b+ L2 E/ r, e8 }: Q#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \9 c! i: K# W6 w ((SOURCE) == RCC_SYSCLKSource_HSE) || \' Q4 x/ D/ F) T% k" g ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) ' f0 `& u3 w9 ]& H. M#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx . @5 u0 d, [7 R# }' W- p|| STM32F410xx || STM32F411xE || STM32F469_479xx */ 7 {) R, V, [) C! W/ X/ G& L' n 复制代码$ K1 _; Z2 ]$ f1 y3 T; v) v1 c9 K RCC_AHB_Clock_Source # l" D7 x) R/ E1 z4 U/** @defgroup RCC_AHB_Clock_Source 9 y. X/ }2 Q" _+ I& W. O, P# n1 F g2 C * @{( {7 a: x X ^ */1 z0 D; |) k6 ~7 P6 F- ] j z #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000): P5 q2 k& a6 T, |& T/ _ #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) - m( t! R1 Z8 x#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) ; J7 Y: W* ^' v2 N4 t4 q, z#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)" q; v$ R* u! B8 y. k! L# j #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) 8 q/ e3 A s& f2 H- g#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) 3 q# i' k* U) d6 _! S, u# U#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) 7 M. C) [8 ?! G; k5 N! E0 e#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)4 U) V- d" w2 A( F3 O/ S$ j #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)8 o7 }1 I, p! G5 F- W #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ ! o) O [& \5 r+ G ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \' ^! O/ e3 P8 B' D/ C4 }2 `, | ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ |. a; r0 @$ {. Q8 Z2 f$ J4 w8 Y ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \( x3 [6 @' d7 ~, p/ |3 I. X$ M ((HCLK) == RCC_SYSCLK_Div512))复制代码% z" j& B" _8 o: T$ e' e% _2 Y RCC_APB1_APB2_Clock_Source $ r; q/ H/ T% @5 t/** @defgroup RCC_APB1_APB2_Clock_Source [. ~- ? i% K& w3 j * @{ & t$ R! E4 X9 g3 ]" z$ t, B$ ~ */. S3 I2 ~/ V+ d) Y& I4 w' Y: Q2 D #define RCC_HCLK_Div1 ((uint32_t)0x00000000) . V7 E3 w$ Y3 F2 f5 I5 Z#define RCC_HCLK_Div2 ((uint32_t)0x00001000)1 Z: t* R/ v7 l #define RCC_HCLK_Div4 ((uint32_t)0x00001400) " w$ H* Z% o. x1 s2 ~4 V0 c#define RCC_HCLK_Div8 ((uint32_t)0x00001800) - j: Q( k9 n% P#define RCC_HCLK_Div16 ((uint32_t)0x00001C00)1 w0 V% N6 N% b #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \5 Y& C$ O% B5 u" O ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \2 A# @& w8 u4 u" C) k ((PCLK) == RCC_HCLK_Div16)) ! W- a' \" J. s; n6 p* c复制代码- [+ f8 U! [& O0 Y6 G6 r* q: p RCC_Interrupt_Source0 d( _- Y* @2 T H. h* a /** @defgroup RCC_Interrupt_Source " e* f6 g) r* Y * @{ & x. i+ c+ w" c */ + ^9 c- I7 Q. F. b6 B#define RCC_IT_LSIRDY ((uint8_t)0x01) / K# y/ n' M5 X- S0 ~, p A" f; ~$ O#define RCC_IT_LSERDY ((uint8_t)0x02) v# g ?* X4 m+ q) e6 e! U% Q- A #define RCC_IT_HSIRDY ((uint8_t)0x04). F# F& E+ A8 O) K #define RCC_IT_HSERDY ((uint8_t)0x08) 3 ?( S, U" o1 @$ t$ t#define RCC_IT_PLLRDY ((uint8_t)0x10) " |; K( K; g4 X9 c5 j$ W#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) ! _& K3 `+ [& `. G1 m #define RCC_IT_PLLSAIRDY ((uint8_t)0x40) 3 I9 f; k' u$ F8 D, o7 O) J#define RCC_IT_CSS ((uint8_t)0x80)' l1 g0 m1 Y) R0 y, H3 x5 R 4 J8 G# Z% X* j3 A2 G: H/ ] #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) ; r" R& H: {# ~0 q- P/ V#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \4 h0 `0 W( s$ d; P1 X9 l# d. m8 U ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ . U! E* e0 L5 w# b! {* V% ? ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \! t- }, h( n5 e K: R ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY)) ) g+ D! B! P# m6 d( L! g# P#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)6 ?' ?% c+ l( I- { 复制代码! Z2 N0 I) v4 U RCC_LSE_Configuration 6 A0 C& h% C8 b0 R( I5 N$ e7 t/** @defgroup RCC_LSE_Configuration . Q6 W% ^9 z. C) @! p- a' \- r * @{ ' b- [, b0 k2 U9 Y- l */ / y1 L+ b3 e" v1 y6 m: K! T#define RCC_LSE_OFF ((uint8_t)0x00) , M R3 `! n0 o( d# Z% b9 n#define RCC_LSE_ON ((uint8_t)0x01) 7 @. M* _& s, \: w/ F#define RCC_LSE_Bypass ((uint8_t)0x04) ! E5 ?# P# m' F7 i3 P" y#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ / d) _; a" \: u) n5 r# H( R( l ((LSE) == RCC_LSE_Bypass))复制代码* U, {" y+ N( R3 f: q$ F% ?- @ RCC_RTC_Clock_Source7 ]+ n% _) C7 K /** @defgroup RCC_RTC_Clock_Source - ~$ Q& Y0 V& ]" f0 B8 U4 c * @{ ; {7 l, \! R8 [+ {3 B: ^! p */ 2 d3 T1 P+ a6 O$ x#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)$ i8 r. U7 a0 \ ^8 P #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)$ Z" v+ ?& g8 c #define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) - d! Y* J5 @. ^: U, V# e: @+ ^#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)* }, ?- h: p3 S8 m #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) 9 \; l" o# d$ }, J" G) m#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)3 J# C, }9 z; H #define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)' Q% J. J. M* _$ ^2 J4 f6 ?4 u #define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)3 E6 A" L$ ^( a/ n6 z8 e #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) ! @' U0 Z3 J. c; Y, U$ [#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300), K9 T8 {3 a' F9 n3 N #define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) , y8 u1 n# b. J* c2 l4 C* p; Y#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) * Z( y( \- {; J, @ c9 }+ P. L#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) / @. j; R# H: @# y8 ^9 z4 y#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300), z; n4 l* f# m2 r #define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)" u j& Y" N; h0 j2 q #define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)& t$ Z2 A) d! D' k0 g #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) * d- T& B ^' A: q: g% P6 m8 R6 c/ _#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)+ }; a0 y- r1 J5 F$ K #define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) 9 {+ w# y' ~5 e" T4 c( ]# ]#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)" T* l7 ~: z" b5 H' h #define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) / s( o4 p% O/ Z* ^: [3 M8 _#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)4 z1 C, L' M/ Q3 y9 o% V #define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) 6 k8 Y0 O9 [2 U3 s1 ?- u#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)$ l, m0 j2 [% }9 H9 H& n. x #define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) 2 x9 e1 h" n) y: L1 X" a# H#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) $ U$ \; k& {* D6 c4 ?% v#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) 2 W# m* e- k9 S. Z. c! @#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) ! a, s( b! ?1 [2 O* S#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)- m- S* u1 R3 L& c8 ^ #define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)6 l* g2 l; O4 X- ]9 Q% H #define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) ; x2 `) j+ w& q* d' B( E# [#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)* f8 A) A$ _ Q #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ 9 e w) `: _- ` ((SOURCE) == RCC_RTCCLKSource_LSI) || \, E1 l7 z3 t# u' R0 i/ ` ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \- ~9 d1 ~# A$ a' _) M ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ ) T3 ?* l' M, {) e) Y3 \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ - I& I+ H% |5 D- k% j% s, R h ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \8 V& t* N# e- g/ j4 q ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ 4 m- ?5 c0 O- t& X/ W ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ 0 ?: q7 `/ j) m8 p) @$ b- [ ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ e5 m3 q4 j5 s0 C ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \/ }- R! g( r6 K ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ # ~# H0 @0 f5 C4 v# w1 g8 o: j6 B ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \- H% B! v# ]4 C: V ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ - K; X6 ~5 V. f! |0 X7 n; r m* J6 n. q ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \; O. s( r' K6 U ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ $ S: x& R, {( y+ q ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \( q5 O. ^) g5 }9 E3 g ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ - M1 d5 d9 [2 { ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ $ e. `6 N0 \4 z- o: ~6 a9 E9 ]. A7 F ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \2 X( O3 P" F) \3 ? ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \. `' a7 Y$ K, ]& k: v" B8 m ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \1 t4 q. u- L6 Z, w% g ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ $ x7 B1 n" p' U) r! D ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ , m. X6 `1 ?) _* A! U ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \& x# v F3 K( p) B ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \2 M' N4 ~5 P' K- O0 g* D- i; s ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ - C/ K1 @6 E2 F+ B& C ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ ( b# h, f' \; g, q ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \& I, c3 }" V% J, ~& V. I0 r ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \4 v7 j- u, X" d ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \" L+ C- W: b0 ~$ S W1 ^+ ?4 F ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \7 |2 a- v( p/ V ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) ! E. M4 L) ~$ z3 M, F4 V复制代码/ x/ O5 y A2 @ RCC_SAI_BlockA_Clock_Source. u# \* U* {$ {! o3 F; U5 D R' D4 P+ [# e* S; ~- m* P7 C/** @defgroup RCC_SAI_BlockA_Clock_Source * d2 }& A) j- t+ t7 n * @{ , h9 p% n! R$ A8 J+ d$ o2 Q2 r. a) @+ w( S */ ( ~' q2 j. a2 m- z6 r#define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000) 7 k3 V: m1 w* X& g2 t1 a7 y#define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000) " U/ A5 M: l( v4 N) A/ |: e& i#define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000)0 g6 O0 i0 v& b6 N: g7 c z8 t a! A/ d! ?! A#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\6 A- E5 z3 g1 E+ ^3 ?0 ?% H ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\9 _( N% D5 Y O: m1 O/ o. v ((SOURCE) == RCC_SAIACLKSource_Ext)) , Z9 f6 f. A2 [7 q* `) v复制代码 , H9 N7 O# m: ?1 k3 b" Q $ U! Y, i; f! W0 k! d/ [RCC_SAI_BlockB_Clock_Source/** @defgroup RCC_SAI_BlockB_Clock_Source2 @& {, S& m) F; k6 t * @{ 9 x% l8 C% L" c/ u% q */3 M6 E7 ?0 r) M* S& A! ? M #define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000)* u. z. ~, P( K2 _- H0 W #define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000) 1 a+ } q: m* z#define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000) : E0 |- @& e% u$ W7 Q / A O5 r3 q. c; n' f#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\ $ g2 Z/ t5 b: N9 f ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\ 5 s- Z6 e6 Z% M9 p ((SOURCE) == RCC_SAIBCLKSource_Ext))复制代码8 Y7 U: t) G0 }5 _. Q RCC_TIM_PRescaler_Selection1 u( S/ x) k) w /** @defgroup RCC_TIM_PRescaler_Selection 0 Z9 R x2 e7 _1 Z- X * @{7 l0 o; K. M- q: \% T+ E */& a5 }0 |0 j4 A" F #define RCC_TIMPrescDesactivated ((uint8_t)0x00)' D5 |: r5 L' F1 Y- c0 q. b3 O #define RCC_TIMPrescActivated ((uint8_t)0x01) ! D E+ s4 t. x% M; O# ~5 V# U. @$ c; V V #define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) : O Y/ }1 A5 l' U' q || ((VALUE) == RCC_TIMPrescActivated))6 _0 y8 F* S x# y4 s7 C5 B 复制代码5 s2 M/ w% F% i$ }. `1 N( V2 R RCC_AHB1_Peripherals 7 d5 F4 o& y b1 K/** @defgroup RCC_AHB1_Peripherals 6 Q3 ^/ ]& G& z" h * @{" u3 I) O, h! k W; p: D* V */ " h- `7 |$ m, N* K #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) - S) c9 H. u; ~& O$ L5 `" ^#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)# [& U& I# l' x: t+ ^( R; S( _ #define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)0 W7 I" z0 W" N m #define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)% m j! r. E2 S, @$ @ #define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)4 P4 E3 u2 e* ^ #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)3 x1 S2 L: t, g/ n #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) ; o7 j: u/ c5 x#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080), Q% @8 x( T+ r' i. I$ W #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) 1 U1 Z- X, i: u3 \6 D' q" |) F: ~#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200) 4 z$ k1 `" o7 O: g4 ~#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400) . }9 _# e' k6 d+ R#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) 0 e& R j u3 j#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) # ^: Q) i2 E# i( p Q#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) ; r3 l& b5 O- m* d#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)* ^; `4 r& Q- n% } #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) ' f5 v" M$ H" h/ H4 N) ^' a( v#define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000)( {4 O! G$ Y, Z #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)! s _8 f$ c% {- D2 _- V. `# l #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) L7 f( Q: l. f J# p #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)9 Q+ O4 d. ]& B" W i+ O6 E #define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000) * y. n/ d% u7 _% F6 K#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) % P2 Y9 { W. p+ N' y6 \6 o, ~+ |3 Q#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)! D! O! J7 U/ L8 q; \& L9 s #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) , D! l2 f u' z$ }( e7 @* }#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) ! Z7 q8 R5 p) t4 O#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000): j+ V/ _5 B, @ #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) * G) r' b, [+ u8 D8 q * D( y3 k D" }9 U2 _% ~8 B9 ^#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) + h0 ~- I+ `5 V; n ((((PERIPH) & 0x010BE800) == 0x00) && ((PERIPH) != 0x00)) & p0 k& X" P( L2 ]5 S! }" X#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) * m$ [' ]" [" N8 Q1 @2 p ((((PERIPH) & 0x51FE800) == 0x00) && ((PERIPH) != 0x00))0 [ |! \/ M& A( ?' i7 U #define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) $ j: Y1 p- {0 h( e; e2 R, u ((((PERIPH) & 0x01106800) == 0x00) && ((PERIPH) != 0x00)) $ v+ U, C( h3 Q. P* ?: Q复制代码: z' H1 U' K3 w' i1 L RCC_AHB2_Peripherals 7 z/ ]* L- L6 A/** @defgroup RCC_AHB2_Peripherals % k- h, I+ h/ x- B( w& x& D. P, m * @{ 0 a, P* u* @2 x */ ' T5 X. I* v& i5 M4 f( V. q #define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) : A6 ?5 L. g, c$ n' y#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) + m. Z* X( ]" K2 ^! ]: O! Y; [1 Z& i#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) ; P) d$ i2 r. r& i# @& A#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)4 |! |3 A, m, [* L0 ~0 @ #define IS_RCC_AHB2_PERIPH(PERIPH) ' V7 L6 X* h% \5 z ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))复制代码 H, C. F$ X5 l8 P- w" } RCC_APB1_Peripherals 8 G- w4 d, ~/ v7 O, [/ I$ ^/** @defgroup RCC_APB1_Peripherals / H, l9 v% J. \* D * @{ ; |( u8 e4 X# {! Y% e) s9 M */ ! j6 c0 r" J6 v$ h, t1 @( t#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) & O% T2 E2 n4 M: n& m0 U: `" E#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)$ K* o a4 @% k #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)) J+ \! R% n/ N% @% d4 J3 a( E5 G5 ~ #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)$ c5 @; _/ I G$ y( Q& n #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010): O- V/ b, u) }8 z [; `+ | #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) 3 I! N; p2 P% S/ ]7 p4 y#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)( D8 w8 d( `3 v, i #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) ! K+ ^; {! @# W5 i6 |( l# j0 e#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) ; ?- I' Y- i F) A- U4 N6 v/ z#if defined(STM32F410xx) || defined(STM32F413_423xx) ' B5 z8 N( f( k) q3 W1 n; a& [4 Y#define RCC_APB1Periph_LPTIM1 ((uint32_t)0x00000200); z" ^, n; Z0 p7 r. c #endif /* STM32F410xx || STM32F413_423xx */ " |/ k' I5 E6 }, z u; n#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) 3 `6 Z, F* a# o& K0 i" X2 V#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) 0 B7 s7 p, g- F1 d) J6 p#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) 7 |; Z P% K2 i$ e0 q) W#if defined(STM32F446xx)+ |/ D* G2 g2 ?6 m$ @ #define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000). C$ o/ F+ `, [/ R# i #endif /* STM32F446xx */ * ]* d \* f% @2 D" r f& k #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000). p2 `! U' K2 b4 F #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)1 m) U- w z& b, P7 I #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)2 {7 }7 V e4 V3 P( G #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) 9 s! M6 T+ D2 l3 Z! I! g#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) , z1 t, T; n# T' |#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) 2 E$ y" K* {: Z#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)3 d# P, A) N1 X. f3 z. Z0 O. Y3 p #if defined(STM32F410xx) || defined(STM32F412xG) & Z" ]' }8 \' c5 q) d7 G || defined(STM32F413_423xx) || defined(STM32F446xx)1 |6 e& i8 u) S/ U, S #define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000) 0 v" C1 p9 s2 U% E' k1 Z7 F" y" x#endif /* STM32F410xx || STM32F446xx || STM32F413_423xx*/ + V3 V; i* o+ p+ T$ I4 T. E4 ]* ] #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) 3 J9 x6 R: s( I4 t: B! y4 |4 J0 e, H#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) + z$ s: [; C8 c' V, E" B#if defined(STM32F413_423xx)8 v' W8 D0 l. u& ]; e6 G$ j/ e' A #define RCC_APB1Periph_CAN3 ((uint32_t)0x08000000)+ E2 X7 m( {5 O% Q# s& t& j6 q& W #endif /* STM32F413_423xx */ 3 G8 ?: [$ `6 G( L# [! K( f#if defined(STM32F446xx) / H8 ?. _2 S, t S) Z1 B#define RCC_APB1Periph_CEC ((uint32_t)0x08000000)) F8 _" u0 {0 j( @6 p& }3 P. O #endif /* STM32F446xx */ 5 _8 ^4 N" K0 H+ T#define RCC_APB1Periph_PWR ((uint32_t)0x10000000): Y0 ? V: y( E1 X D #define RCC_APB1Periph_DAC ((uint32_t)0x20000000)9 E+ I8 Z0 R- H- f #define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)3 f5 q2 L8 ]6 r& ?' y* k #define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)2 L# c! w7 `/ w #define IS_RCC_APB1_PERIPH(PERIPH) 8 R1 @; A# k. V/ \2 | ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00))4 k1 z" x4 u6 c0 a0 t% _ 复制代码 3 V; o8 [% r- M( `# g% ORCC_APB2_Peripherals! ?0 n+ [) m# t* Q1 l1 L7 h /** @defgroup RCC_APB2_Peripherals - Q' H, I- ]: p" I A6 x, p* m * @{) B) h: b7 J/ ]; P8 r" s7 q */ 4 N4 h8 G+ i0 Z4 o% l: X3 N$ q #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)- x7 t' `2 v9 L4 o% O2 d: h. ~# X! M #define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)# e! p: l" h5 p( W3 s* s0 Y #define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) # E. D D& \4 E3 V; B* x#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) " \ o3 s; K A* [# A#define RCC_APB2Periph_ADC ((uint32_t)0x00000100) 7 Q7 H) f6 x; \* R#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)* w/ R6 q# e' q/ n/ [ #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)( x# l4 j" p9 V- T #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) 0 h# G4 u2 s$ d1 n. s#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)9 M+ k9 K5 k' ^! \- Z- e #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) 0 j( x; v) k, E- H7 ~/ E% g( m#define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000) 5 ^/ \& `4 o3 b0 ^6 ]#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)% R6 x2 `. l' E# c% ]; @6 W #define RCC_APB2Periph_EXTIT ((uint32_t)0x00008000) 6 V6 Z. a& u7 L! ~8 E#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000); l9 \* Y( p: u- F+ N0 C5 A( X #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) # C9 n& v% N! |% r+ }#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) $ \5 E7 \6 J. a: a: U6 W#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)1 V8 a1 b. M7 \ ]( m& N #define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000) + x8 {* U- F. d8 n$ S#define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000)3 ]: i$ _: q2 Q. z4 m #if defined(STM32F446xx) || defined(STM32F469_479xx)1 } b* Q: L0 t3 f #define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000)( }" E1 }1 Z! f Z( e #endif /* STM32F446xx || STM32F469_479xx */ & r7 Z7 @/ B3 g. t# L+ G#define RCC_APB2Periph_LTDC ((uint32_t)0x04000000) * p; ~. f h4 U* K0 {: w#if defined(STM32F469_479xx) 2 X, i+ ^; j8 g; r0 D7 G3 f#define RCC_APB2Periph_DSI ((uint32_t)0x08000000)) G2 G: v+ A/ S #endif /* STM32F469_479xx */. ~8 x: p: K/ ]6 Z #if defined(STM32F412xG) || defined(STM32F413_423xx) " V/ O1 A# J9 J% M0 p6 w- k2 e* {#define RCC_APB2Periph_DFSDM1 ((uint32_t)0x01000000) * ^4 [/ X) K- f. ^#endif /* STM32F412xG || STM32F413_423xx */# b8 V# E9 _+ u# S& W. p #if defined(STM32F413_423xx)) `% S5 k1 G: X7 ] #define RCC_APB2Periph_DFSDM2 ((uint32_t)0x02000000) 9 |, m& M) X) }* J {#define RCC_APB2Periph_UART9 ((uint32_t)0x02000040)) t) F' r* ?6 J! c& T #define RCC_APB2Periph_UART10 ((uint32_t)0x00000080) 7 R" J- x# P; L# V. F" [0 u#endif /* STM32F413_423xx */ 6 t! m7 m( |5 a9 j) T / ]1 ^" r9 a: Q/* Legacy Defines */+ e7 T" c- S; o+ D$ [# K: ^3 t #define RCC_APB2Periph_DFSDM RCC_APB2Periph_DFSDM1 ) e$ x1 J$ f( `7 b& k5 m: Y% c1 D 5 p* ]& n. k9 F J* q( t' ?" @#define IS_RCC_APB2_PERIPH(PERIPH) 5 p: l% u/ g+ e8 [7 ?" H6 I ((((PERIPH) & 0xF008000C) == 0x00) && ((PERIPH) != 0x00)) " W6 c7 z& S9 x' b7 T$ B+ d5 V. W% n#define IS_RCC_APB2_RESET_PERIPH(PERIPH) - V( k! T% c- U$ z9 ~ ((((PERIPH) & 0xF208860C) == 0x00) && ((PERIPH) != 0x00))复制代码9 f% ?: `- N% N7 T# l RCC_MCO1_Clock_Source_Prescaler4 G# d0 ?0 X" r( R8 u( N /** @defgroup RCC_MCO1_Clock_Source_Prescaler8 j1 f" b" _4 Z3 l8 z * @{ 0 m! C8 C5 }5 l, j4 j */ , q9 x0 @) d$ x% V( Z7 D$ a#define RCC_MCO1Source_HSI ((uint32_t)0x00000000) ! g1 `7 q# x4 B) o#define RCC_MCO1Source_LSE ((uint32_t)0x00200000) 6 s% w6 z6 u$ k6 r6 }#define RCC_MCO1Source_HSE ((uint32_t)0x00400000) 3 r$ {) H* X: X. V, b#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) $ K' u9 Q _. b# ? c( ^#define RCC_MCO1Div_1 ((uint32_t)0x00000000), T( ~4 I, p# {1 i! h. ^8 x7 Z+ I #define RCC_MCO1Div_2 ((uint32_t)0x04000000) ) s) n, A1 |" N6 [#define RCC_MCO1Div_3 ((uint32_t)0x05000000)% J* x0 B: f9 |7 E; o #define RCC_MCO1Div_4 ((uint32_t)0x06000000)9 c8 x% d1 P6 C: G #define RCC_MCO1Div_5 ((uint32_t)0x07000000). P4 f8 S. k# {, x+ p #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) 7 m/ D+ d4 D1 K3 G|| ((SOURCE) == RCC_MCO1Source_LSE) || \& Y' R1 Y6 H. Z4 h; ~& t$ y. k ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) 8 J. S- w6 T4 @ + P+ Z5 S) F+ U! x- D; w. H0 W#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \- d. e9 b5 u7 ?& r& _ ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ & H/ K" ` _& h/ x7 { ((DIV) == RCC_MCO1Div_5)) 复制代码 ! d$ Y, f7 w" Z! W3 Z$ zRCC_MCO2_Clock_Source_Prescaler6 `- p% e. u) l /** @defgroup RCC_MCO2_Clock_Source_Prescaler & S2 m' h" p0 f" b7 M1 U * @{ 4 H( i- o2 O1 N( t */ ) f+ _( N0 a) u& x M% k0 k9 D9 s#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) $ Q. ?% z8 S2 o3 ^" w. V4 n#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)9 X! I- c+ v% B( O5 ^ #define RCC_MCO2Source_HSE ((uint32_t)0x80000000) ( |& Q, ~7 [/ t+ k* p, x+ i& ^& m: d#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)2 U8 H, O. o$ u; Q #define RCC_MCO2Div_1 ((uint32_t)0x00000000) ! _1 ?& ]6 m6 ` V, T( T8 q" R#define RCC_MCO2Div_2 ((uint32_t)0x20000000) % x9 @* X! Q6 ?#define RCC_MCO2Div_3 ((uint32_t)0x28000000), H( k" T" q5 ]6 a #define RCC_MCO2Div_4 ((uint32_t)0x30000000)4 |6 R: N( P0 b2 A0 u1 B; G& z #define RCC_MCO2Div_5 ((uint32_t)0x38000000)7 y, f$ B9 J3 o3 B #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) 1 U h" C- ?! F# h) K7 ^|| ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ 9 w4 S9 c$ L- e8 `; H' b ((SOURCE) == RCC_MCO2Source_HSE) , f0 o8 ^6 V2 e# S* g || ((SOURCE) == RCC_MCO2Source_PLLCLK))5 \7 z$ U' r; L3 @* u, w $ N3 p C9 e; i$ T- Q$ b #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ & v: `5 ?3 \% l/ v0 T4 B8 y; K ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ 7 @5 Z2 L" i, u% e ((DIV) == RCC_MCO2Div_5)) 9 H% [. H. r9 z5 a 复制代码6 g) K7 n# p2 u' c" X) t' C7 j RCC_Flag ) d" h3 H+ P4 Z( O- r5 U/** @defgroup RCC_Flag 6 w6 M) M0 `9 b5 n' ^, c+ q * @{* c5 S; \8 _9 q1 s, `/ A5 ^0 q& l* x */) u& G# i s/ G' j- b4 c #define RCC_FLAG_HSIRDY ((uint8_t)0x21)' k' \: I9 s2 u, D. P- b Y: a% v #define RCC_FLAG_HSERDY ((uint8_t)0x31) ! R# e" n; `2 P ^3 X! i& s- t2 P#define RCC_FLAG_PLLRDY ((uint8_t)0x39) - r, B9 {" d: G/ h#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)2 s: w) G$ t4 m2 P #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D)0 l! \" }, P' f0 U( \9 X: r: }4 ^9 \ #define RCC_FLAG_LSERDY ((uint8_t)0x41)% P& N; U8 a% c1 k #define RCC_FLAG_LSIRDY ((uint8_t)0x61) + `$ {! w$ [% \! t4 ^#define RCC_FLAG_BORRST ((uint8_t)0x79) ' S0 C, U3 [- \* C7 t#define RCC_FLAG_PINRST ((uint8_t)0x7A) 4 N' u: m: g. a6 {#define RCC_FLAG_PORRST ((uint8_t)0x7B)9 K7 O/ p" m( _# p) @ #define RCC_FLAG_SFTRST ((uint8_t)0x7C) 2 N) {& }( H! V. Y8 ?% p#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) , W+ m! h ^1 V* R#define RCC_FLAG_WWDGRST ((uint8_t)0x7E); e5 w8 J2 V$ k #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)7 r: g2 J5 q, f7 p % R% N, g/ U3 P0 N #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \& F J& i6 w# K- c9 [, q( z- p8 @ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ $ v3 u) R9 Y& I4 u ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ 1 M' e2 J6 A$ l" c' a" E% e ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ 2 f6 q8 X( c* J1 X$ f: o5 K' M6 T( n ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \% I' W) i$ _1 ?. n5 P ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \ 8 ~ U' f# S2 P& ~: R! _( S ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY)) : C/ U. h$ ~% h6 Q5 d * l# i( u7 ?: N, W1 ~#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)复制代码: P$ ~1 F8 V8 _* t% r1 I 03. 相关函数, Z: ?- F ^6 G /* Function used to set the RCC clock configuration to the default reset state */7 v+ a- D" n8 i5 ~* d6 `$ f void RCC_DeInit(void);7 C6 D! G% W& F6 T3 Q& o # v ^& h3 n2 U% I3 i, H /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ 9 W- }3 {8 y) hvoid RCC_HSEConfig(uint8_t RCC_HSE);# I0 E2 e- L- u% D ErrorStatus RCC_WaitForHSEStartUp(void);0 w1 Z+ @* ?( f: u void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);0 D5 s1 [1 q- h7 Y void RCC_HSICmd(FunctionalState NewState);- G1 H6 [& l: I7 @: P void RCC_LSEConfig(uint8_t RCC_LSE); u) U# q. d) S" cvoid RCC_LSICmd(FunctionalState NewState);4 \& m; s; _1 M+ s |3 x" P1 L: d% T; D" I. y* Ivoid RCC_PLLCmd(FunctionalState NewState);0 k/ L: C1 B/ T+ N" B8 o $ _6 ^0 b6 {( Q1 ^% D3 A void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, ) t2 y) D7 a4 w uint32_t PLLP, uint32_t PLLQ);" _3 \" c. `- u; o3 H . l) x6 h! s0 e% X" gvoid RCC_PLLI2SCmd(FunctionalState NewState);8 X" }2 n" ~( L+ c! N( ` * X& z5 @! h2 d% j void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); m- E0 `. [" N. L2 ] * N$ P; ^) R+ b( l% J5 F + H& Y* r6 f2 j! ^4 r% D void RCC_PLLSAICmd(FunctionalState NewState);7 P1 _7 j+ W9 i: a6 u# R5 f $ K& @) A/ l6 `' Yvoid RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);5 |5 Z- }2 F+ |" _, Z void RCC_ClockSecuritySystemCmd(FunctionalState NewState); ' B- ^& T7 Q0 Z6 Uvoid RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);, h; o6 \+ l8 ^1 {$ c9 ? void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); / N" N2 o5 @/ t# @, Y7 j; R1 {' j3 ?8 t9 c& t- b. K( s ' A: x6 V8 P9 t /* System, AHB and APB busses clocks configuration functions ******************/ $ x! n" K: M* i: Kvoid RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);. b% \7 J/ ^1 B8 a/ T uint8_t RCC_GetSYSCLKSource(void); 6 h5 ^: C# ]# |5 z/ o! }* [void RCC_HCLKConfig(uint32_t RCC_SYSCLK);7 t4 a6 B9 ?! E9 u8 q" h3 { void RCC_PCLK1Config(uint32_t RCC_HCLK);& ]: l& j/ o6 I, i( Z# b void RCC_PCLK2Config(uint32_t RCC_HCLK); 7 b' O, F* v$ Rvoid RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);) }5 H8 L/ V4 M# A( R% g7 e 8 a9 p% b. H- a4 X8 K/* Peripheral clocks configuration functions **********************************/ A$ i" Z, ]; G+ F( Y# C5 h" dvoid RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);8 V5 k% c7 I8 K6 @ void RCC_RTCCLKCmd(FunctionalState NewState); + l+ I. Q! e+ t+ \3 E0 S- v* bvoid RCC_BackupResetCmd(FunctionalState NewState); 5 n: E- e* F) X8 Q2 g7 X+ ?4 S# @6 j" y& o 7 S$ i4 C0 m) Z: `. Rvoid RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); : Y3 x9 q5 T4 } 7 K. \; g2 o* ^/ G% L( s& l4 X- K0 T1 |) X- D void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);; q0 O* C8 ~0 L( `. H% u3 \ void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);2 D! `: m% \- C! b2 i2 k 9 t, ~1 g! Y$ a) c Z! G @' K& k' G' Q+ P void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);- ?2 B2 J2 S% A; Q- W; n" x void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);, R' `) h ^ i/ T: d8 r / p' G( H. C8 L5 u+ L - O* \( d1 z; U void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);. i2 o/ K5 F" i' e+ u5 V void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);6 U! }. S4 _, h3 Y9 r4 s& y0 ] ; J" t% s/ J; |9 {/ r; U void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); ; A$ l0 R8 p! ~0 P* Yvoid RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);- S4 U* X0 o& L" g/ m- U void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); + K) n. H% s9 T bvoid RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);6 G9 U) ]6 M2 K( I# ]; e7 r void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 8 e3 Y& Q& O. t* L) X" q 8 T3 w4 b7 j, P7 ]' E8 a+ zvoid RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); 2 J$ H& f5 ?' s7 G, q) ^7 u3 F: f1 Gvoid RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); * y1 X+ y+ q( S! Y& Xvoid RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); , w. g- i* l" [; {3 h- vvoid RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 5 S4 Y# C8 C7 Y" P) ~void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); : \6 j0 D8 Y) ?9 G' z1 _. {' x4 J) [' s# v' n' O1 x void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); 9 \$ {, {3 c5 ?6 D3 k( dvoid RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); & I/ ~% y$ Z2 [6 ]- bvoid RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);" F" z9 J; \$ d z5 Y' { void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); * S" L# p* k& y) E0 o7 }void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);) z# }9 {" J. T9 u5 E / |0 L& d1 w- T n0 q' ` 3 P6 Z" o, I" \7 m: G" B1 ^3 `/* Interrupts and flags management functions **********************************/ 2 x' r# M- b8 T3 H% I2 Bvoid RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); : u2 D x+ S, j0 a6 nFlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); , m- N$ z! b* u4 d: A* uvoid RCC_ClearFlag(void);7 {) M" }, @! r( W {( H ITStatus RCC_GetITStatus(uint8_t RCC_IT); * m$ j0 S1 L. I9 {* Zvoid RCC_ClearITPendingBit(uint8_t RCC_IT); 2 O, |3 m/ Z2 k/ `9 s复制代码 # d9 [" j- p8 ^" ~ 0 d: C2 J0 d5 x: J2 h; Z04. 结构体封装 + Q# a7 y* Y, b2 {9 B% G/** $ c4 i- _5 L+ \4 h * @brief Reset and Clock Control * S6 J5 i1 o Q */ + }8 T' e+ A1 _# B3 k! e ?; {9 A: a typedef struct $ \0 e: F! @8 I, g8 y{ z# F# ~ u3 @9 Q* z8 S __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ 1 W. X: s0 r+ g+ K* ^ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */' K6 j/ m4 W* L9 b% F- f __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ 6 p; y; C: ~/ {$ c$ m" A __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */$ R; y" _( m/ P G7 w2 v9 f __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ , L: P ^" T* ]0 x __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */8 \0 }2 |" @0 E- X; {4 `. P! h) D% X __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */9 l4 E8 \! E; S b- ?. a uint32_t RESERVED0; /*!< Reserved, 0x1C */ + M/ x: g( G1 O2 c' ]+ D __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */5 v8 B" A% t: Q+ ]# z+ o! y: X2 P __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ , {1 D9 l; f4 O/ L+ ]0 D uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */. ]+ t4 q1 L4 w __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */" g) B5 [( R! J0 A __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */2 R: e3 X2 Z( n8 M+ u0 C: F% @ B! w- A __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ 3 p% ?/ O9 {# n5 J uint32_t RESERVED2; /*!< Reserved, 0x3C */ * \& z3 g. \4 o9 b. N+ q __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ 7 i; M( x) d: ~' s$ _# `2 z- g% N' b __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */8 z' i6 b7 Q. X' ^# ^ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */: T" r- k: \4 S) N! n+ s5 C/ r) G1 n __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */% m/ t2 p) a/ |1 u' ] __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ $ j/ m" h* B3 ^# A+ m% G5 ` __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */' U1 F/ c4 g% h+ z- F! h( ` uint32_t RESERVED4; /*!< Reserved, 0x5C */7 _3 S; g4 H7 f; l# ^/ @' d __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */: w9 A1 { p; M9 U __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ * R5 g' ^( ]3 [6 D: T+ z uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */8 h. a1 k( ^8 J- k* [3 W __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ 1 ]5 P; f0 |8 B7 t* E2 t __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ " \5 x8 _; d) @5 l uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */% A$ Z, B9 W' e1 d( G __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */2 c9 V5 A. k4 d- X4 b" M6 Q6 S7 y __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ ! R/ s) V' u @- L" G: g$ v7 D! K __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ $ n9 P6 h" C/ _* L, D9 {" @' F __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */8 B2 r+ S* ?& M( x9 a8 F& R __IO uint32_t CKGATENR; /*!< RCC Clocks Gated Enable Register, Address offset: 0x90 */ /* Only for STM32F412xG, STM32413_423xx and STM32F446xx devices */ ) S5 Y( z9 t# U! I9 ^+ V __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */ /* Only for STM32F410xx, STM32F412xG, STM32413_423xx and STM32F446xx devices */: f* [: [' a% k) P * x% e3 H( b5 y, B" z+ S: T} RCC_TypeDef; 1 O, [0 P" M `& c/ A9 B复制代码" Z) v( ~+ a/ _ v# F$ Z) ]! m . J& I+ G+ S; Q0 D5 A 05. 其它: \" l1 T4 D- G/ l2 y /******************************************************************************/ ! D/ i/ o# A/ \! X( A& I/* */ ' K; D; ^, L3 c- q3 l! d/* Reset and Clock Control */ + i8 `7 I* N. N) `8 O) {/* */% {9 T) ~6 T( D* N" }2 `& Y" A; b /******************************************************************************/+ `9 o. G+ @# ~3 p' y7 N2 ^ /******************** Bit definition for RCC_CR register ********************/ 2 D6 ?( ~4 l# j#define RCC_CR_HSION ((uint32_t)0x00000001) k# j& U7 H) g4 @#define RCC_CR_HSIRDY ((uint32_t)0x00000002)/ d: F4 Z. r% Y 4 r [1 e) W e* f) a' a. f$ ] #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) 7 E( C4 u7 R* Z, _#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */ i/ I1 R& W7 P6 h, W#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */ 6 t/ F% ^. g6 ~; L#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */8 b; Z" l5 [' m/ S3 a! K, e- \ #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */ , }- B& g. o+ a. g" z#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */ 2 j7 O9 u0 b, `9 l) v! P5 v% ~ / ?0 C$ ?1 W" W+ Z$ v% \7 p/ k" ^#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) + A2 E& Y) @+ Q/ f a4 ~#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */ * q. i. @' K l#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */& p j! q s7 \: A7 |; f+ } #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */ W9 ^- o3 W' \/ K. U #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */0 R) C: F; _2 O% N; ? #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */ N) ]# v* g2 J( ?: n#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */ / B% A. c( X& x" d7 h2 W2 Q$ g4 u#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */ 3 I" c( s3 W$ H$ B#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */. N' G$ L. `4 ^- @$ q! o, h $ K7 }6 v s( Q' ` #define RCC_CR_HSEON ((uint32_t)0x00010000) 3 Y# z# [* `/ {% k9 c# ^#define RCC_CR_HSERDY ((uint32_t)0x00020000)' R; J# [, d3 Z) B0 V0 b #define RCC_CR_HSEBYP ((uint32_t)0x00040000) 6 f9 z: W3 H: r; M#define RCC_CR_CSSON ((uint32_t)0x00080000) ) K. g5 D$ t+ \6 M3 S8 `#define RCC_CR_PLLON ((uint32_t)0x01000000) * g" a5 S/ d; O* d: i8 F+ {#define RCC_CR_PLLRDY ((uint32_t)0x02000000)4 T. V. b1 P& }9 [% D) U. G# e4 f) u #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)( m; h) c. @; j! E6 }& Z) F; @ #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000) 4 Z0 G! W$ d6 B#define RCC_CR_PLLSAION ((uint32_t)0x10000000) ( [ {- w% q, t5 U) B) U#define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000) ) E0 y0 [) V4 c: ~- U" y7 o2 L+ L' L, P" z4 [/ A /******************** Bit definition for RCC_PLLCFGR register ***************/ 3 W3 T0 i! l; r* M" N* V+ o#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F) - t$ o/ p! C/ l6 k#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)/ c' S' p& G4 v( ~ #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)4 t4 H$ A% E- X) c/ B #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004) ; e+ j: Y' X5 f' t, z& O* R: x#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)7 }) r! \/ v- h3 r& w #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010) ; ~' k5 W: {: N0 m) @# i#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020) 6 n; K; p$ d G* z( F% a 1 S$ T5 Y; C: v) ?; | [#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0) - M: O0 N ^+ M R#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040) 6 A% `3 j: l8 i; O#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080) p) s' ^. N) n" s#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)# q; \4 |7 S# Q! v #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)% {( B( ^ s( U: x. ^" W #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400) " X+ `/ Y2 k; E9 I) @2 j6 n r#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800) - v6 x/ l# m; ~7 m; ]8 w L. @#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000); x2 Q- z& Y. f- D9 \/ [; [* [4 K #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000) + |9 A8 L2 [3 ]* i$ o#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000) ( J, L# o- b0 L, a3 j) j7 S! ~& z/ s #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)! m2 h/ ^9 b8 O v& ~$ V #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)9 e' X9 G" G9 \; I! X V #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)( u {3 ^: d* c9 |7 G& Y! z # O# s9 m2 p# I9 w$ H J#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000) & E, B3 B8 Y# _! Q#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000) 4 W" G) _( w; M" s#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)3 L. d1 s7 ?% d- _, W* V/ o+ E3 P g& v$ O- j3 w# M- n5 Q: v) f#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000) ; a0 E- m; m' L# ]#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)6 L" t9 i: X: ~5 s #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000) ( S0 h5 N! T# e: @#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)9 \3 [, M& [3 y! t q3 E H #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)3 I& i, y- p. v$ h ' n+ R a* [8 B' ]: Y) }3 |4 c u#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) / _" R$ f5 Z# J3 I- r; a4 }0 C; F7 x#define RCC_PLLCFGR_PLLR ((uint32_t)0x70000000) ; n6 l% r W9 C( X; f6 l#define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x10000000) : J! g) R; [; d6 Z+ B#define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x20000000)4 K* c, m7 f5 c- T" M4 d #define RCC_PLLCFGR_PLLR_2 ((uint32_t)0x40000000)/ T0 o( ]% Z6 J8 K8 x: m, [/ e #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ " x6 S) D9 J6 e* U( F3 y, \3 L+ d. G% H/ Y/ H; D /******************** Bit definition for RCC_CFGR register ******************/4 ?! h# G* h1 t! U* @5 m" x /*!< SW configuration */ * c* \4 v$ ?% X2 v3 T. `5 q% ]! G#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */, p- d% Z$ d, G# U1 T4 q #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ : b! _: H; o8 t) G0 L0 E! x#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */# z( X! R' W( t" Z$ D9 @7 ? 7 v: {9 q4 |# b8 n0 J #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */& P) b& B7 u/ r2 R #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */" V4 @* {- F1 Y$ \" e #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL/PLLP selected as system clock */ & [* f+ D: b! c6 ]#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) 9 ~: q6 J- Q, ^# D4 o#define RCC_CFGR_SW_PLLR ((uint32_t)0x00000003) /*!< PLL/PLLR selected as system clock */ 5 U% `. q u- P' s& e q#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ 4 K' F; B7 S2 A! J. n ' E, F% q+ l) H& F8 L/*!< SWS configuration */ # M! }# n; w- g' K- z. @2 k6 X#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */5 l v( b4 i, Q0 c2 R #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ 9 _. z+ q2 k4 i* s+ Z) W, N#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */! X* s( m! f8 r3 v4 D ` 9 S2 c- ^& N2 [ #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ / i- e4 Q& r& c# G#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ * d k# ]6 b! v% x2 C# h#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL/PLLP used as system clock */ , d! x4 ? n& J4 |9 e* H; E, @#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F469_479xx) || defined(STM32F446xx)8 j9 a" q) [) Q #define RCC_CFGR_SWS_PLLR ((uint32_t)0x0000000C) /*!< PLL/PLLR used as system clock */ # v& ^& g! m8 i' z l' I& p#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ # G) Q! E' g% n. K3 S5 u! G* m' G ( [3 K% @, @% k/*!< HPRE configuration */8 x7 K# m- m3 P9 a- T #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */+ z+ P. W4 r1 |, g" g7 u& @0 C* c #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ B8 j6 B8 u9 p#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */3 z- V% o" M. D, K1 ? #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */* }. `0 z7 f" l8 H #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */: G9 D' d7 X: [/ P " f* @4 _- S M! B3 B8 }; t8 m #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ $ w! _& [) }' v% @' b#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */' k* S! k+ o+ _- g #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ ) S1 C/ K t: N# S#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */7 x; j0 w/ h, w2 c) J3 u& s, n #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */$ a+ ^2 U! k& H9 w/ _ #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ $ Q& F/ |5 ?1 k8 O9 U- f: m#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */" e6 i% J5 Y1 S$ r5 o #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */' t# n' K" |. h6 Z2 q1 K! z #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */' G9 K6 d& y+ b6 c: y/ Y* E$ W( ^7 ? - W9 ^! ]+ s, Y" C% p/ j& `#if defined(STM32F410xx) 0 ]; d( A, l1 o* ]8 r/*!< MCO1EN configuration */ 1 x+ B) F5 B# w#define RCC_CFGR_MCO1EN ((uint32_t)0x00000100) /*!< MCO1EN bit */ # s3 v. Z6 {* ^3 h; s" K. p/*!< MCO1EN configuration */, ^% e& b# V" X: R4 q, @ #define RCC_CFGR_MCO2EN ((uint32_t)0x00000200) /*!< MCO2EN bit */ ! `4 I5 h: n3 T5 m$ P#endif /* STM32F410xx */, j9 H$ _5 _7 D7 Y2 `( _5 q4 L7 g /*!< PPRE1 configuration */ # n9 X8 U6 S5 E! R; W! x7 y#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */ - v4 B* @; u" _& K7 j( K' ^8 t#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */ ' }% }. O' J* H$ F! R#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */9 [6 x4 _* c+ r1 G #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */4 y- O N) l8 W; W2 Z1 R; S3 q: f ' S$ W& B" ?6 J2 ]9 V9 q#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */. I: N; ]7 |! x* X/ [# U7 v #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */ + b# S4 Z/ J4 ?, u2 C A) P#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */) }! f3 l0 h, j' S) A4 z #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */% h, ^5 [8 m) V) y; P: p #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */7 |& Z0 W) p3 q$ n/ N 7 `6 r; s1 b! u: W" P. l$ {# \/*!< PPRE2 configuration */ 7 Q9 D' M3 l6 w#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */ $ y/ h# R# |( [/ u, P& m#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */7 M" `0 e, Q( f6 { #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */# L& X; v3 L- k" x$ j4 S) p #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */ 8 H g! W( A! X 2 {3 K3 j, n! V4 y6 Q6 C#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ 1 p% A, J2 j( R& y$ N/ j#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */ 7 t8 B( G2 s; Q' m) a/ x2 T3 b) ]5 Z#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */# t+ b# i0 x# O, @ #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */ ! N* R4 H9 T, @0 N; Y t i#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */, O4 h& \. Z9 P) d0 K7 l. X' [7 A* y + b# T# N; W a! F/ A d/*!< RTCPRE configuration */! ^1 U0 `- e. u- @ c9 W3 a #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000) 1 Z/ G9 k9 g6 U7 s% M#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000) 1 F; _7 j* B$ ^8 K- U7 F0 j+ l#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000) ( X0 }# J& i% G#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)% }! D$ b! [8 p0 |+ J3 T: J #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)1 D( ]% E; k! u7 M% a+ K #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000), P: n, R8 n5 S9 p % J( f4 S" g' f! @1 R/*!< MCO1 configuration */ : E e# C% |1 ~* L! ^3 t#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)- }8 {- v& E! f+ i. q. }' H1 x7 s #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)$ a& ?; A: I. f* a2 k5 \+ [ #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000) y! p% S% Z7 O3 h 2 X0 u7 a q9 J #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) 0 K7 _' s. h ^: ^" e0 X; R1 f/ Q) E r* g2 Z1 k' j #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)& ~1 ~% ]1 Y9 V" z3 V2 Y #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000) 8 G2 r! E$ n) K# _3 O9 h: l: V#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000), w6 {% O" c G$ a. @( E #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000) ' S. {$ z) Q. W; c0 C8 Z7 a+ J, j* m" |- J' v2 d9 b #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000) ( K5 m {7 H4 B#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)$ J0 W& \7 U0 H1 q6 |& t6 e& J0 V #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000) . m! d7 x2 K, ~. u#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)8 }: _* Q7 O% o$ o7 m+ Y* _ ! b. D& `/ f2 d8 B2 m* s) r#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)# G8 t& k% D' \8 P* a #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)0 O1 X8 [9 J( n. q+ D #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000) V/ j) j7 g0 K# S) R 7 b+ d) h, q, k; s& o0 Z /******************** Bit definition for RCC_CIR register *******************/ ( ~3 V- L S7 ^# N#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) 1 A/ L5 I, m' {4 [5 L9 Q3 Z$ P8 w) N#define RCC_CIR_LSERDYF ((uint32_t)0x00000002), W4 g2 k9 N d$ ]* f, f G #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) 8 O; ~- ]' ~# b+ p& F B#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)8 x0 _* l. P. {7 n$ v& l9 q/ W #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) 1 v/ `. A% Z- N. B- v: N3 i1 N#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020) ; l( I j: \. ` { k0 D) k#define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040) Y4 M z2 P9 z R. c) b/ l#define RCC_CIR_CSSF ((uint32_t)0x00000080) % a, g3 [3 m h" r( o2 M- y3 e! x$ M8 v6 e4 I#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) , B( O# D1 Z8 {! @8 I: l. h#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) & i, ?+ F& o% k#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)3 ~% P0 v/ }- t: I+ d7 W #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)% }" ]2 N" A4 v #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)- I8 W3 E7 S' h, ?: b #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000) ! m2 ?0 l7 P' v1 o: C. E1 \#define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000) , \5 I9 R( I. S# ^, _4 O- n#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)$ l! D; ~: q; f P+ r #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) 7 s2 T6 `3 J3 u- Y6 Y) [) @#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) 4 b( l& K3 d/ ~#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) 5 G9 r4 Q0 L, P3 ~9 c" ^#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)5 g3 B* ^9 j5 g) u$ k #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)0 m. [( d" R- L+ @* p% T2 q; \ #define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)2 L; V. ?$ d- y #define RCC_CIR_CSSC ((uint32_t)0x00800000). _2 T" t) K0 v5 \/ Z9 b 3 X( ]' ^0 r3 R) h y' `/******************** Bit definition for RCC_AHB1RSTR register **************/ 1 j: A5 W- R) E6 ^4 O#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001) + P8 \4 ]7 {6 z#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002) . E+ r/ {+ ~% R7 L+ L; m1 ]#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004) ?% |+ m; t. c: o b" p1 l#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008) * h& P: P9 T: N* c#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010) " C3 A9 Y. }8 h6 R* ?#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020), d" N4 H" b9 _% c6 ?! u #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)! @, O* P# D% N& o #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)' S4 l. ]4 J. _ #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100) 1 m, f9 o3 P5 P#define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200) ; G$ z7 b0 t. z; q; E5 q1 v#define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400); f3 D- ~5 e3 m, @+ C# A+ s# e2 n$ X #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)# V0 @+ b3 m7 s. H #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)1 L, n; C; @1 W# a7 ~4 P #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)2 T$ M6 p0 n# u8 K6 H; n #define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000) ; {9 ^' ]; X4 F& k! O( x#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000) # u+ l+ j, V, g( k, a' W& {8 R#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)2 p; T; p) X' b. h; V % O4 j" w* R8 [; V5 K/******************** Bit definition for RCC_AHB2RSTR register **************/0 g9 d+ [/ _: ]+ \) r #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001) 6 a* N/ O4 ~( a& O9 m0 `#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010) . r1 ^% G# q8 g+ a#define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020) 9 C2 g' m! r" j0 }# u, R) p0 K" y /* maintained for legacy purpose */# l7 s9 B+ O2 i" ^5 {7 _( A$ w #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST & n) h$ \$ O; o% m; {9 M- Z#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)' i% A/ o4 d) Q" B5 L* l/ v #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)" T9 q( H, @2 Z. m 6 ~: U& F5 o1 z3 C7 v6 n7 s* x1 D /******************** Bit definition for RCC_AHB3RSTR register **************/3 D5 G& u# W4 F( R6 ^ #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)/ Q) P I1 O) f0 w6 C #define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001); h+ g8 l9 H: `) y( [7 \/ m #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */& Y6 G! u1 s# X' P: M: _! \ " y% L* Y9 q* G8 L #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)" F, y9 y% [2 K0 D5 x- ^' T #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001) * s/ m* S$ v3 |* d#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ w5 J9 ~7 T# t" H4 v s, J#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)4 l; p, F5 n$ K [/ `/ R a! e #define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)) z3 ?$ E" F0 a( s; k7 \# o" | #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */; C6 @. I, O( I" K ( N i4 \, w x( m4 m /******************** Bit definition for RCC_APB1RSTR register **************/( v a8 Q) y9 ^! `' Z #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)" K* `$ G0 j1 Z3 @" S7 L #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) 1 |8 d. O' ?- e* ^! `#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) & n3 {" h9 b2 S* }( ?. ~#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)- Q3 D% ^' F. l: z) |3 I+ W #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)) `' O- D/ ~1 Q$ @' n% G3 k5 c' [0 { #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020); l$ |1 A: r! o0 w' a! h #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) # B5 a/ E; i' m6 i7 k/ [9 Z#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)3 B2 q% m @8 ^8 k6 ~2 e3 `( e( W #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) ! N/ t6 H) j% f: s; _, e#if defined(STM32F410xx) || defined(STM32F413_423xx) ) R% Z7 T, P$ T8 V4 Z$ ^8 ]4 E3 x#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x00000200) 8 }, E/ n, G4 m) ]#endif /* STM32F410xx || STM32F413_423xx */ % Q( ^) s! A2 N& D e: p/ H#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)* N$ L9 o: ~, I5 Q; v3 L: P" p2 W8 @ #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)3 Q2 H% c+ j$ t! m$ h4 F1 K E6 ` #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)3 ]. t$ y D4 t' x. t# J #if defined(STM32F446xx)! J" ^ T& h' Z. y1 S& F/ w# W #define RCC_APB1RSTR_SPDIFRXRST ((uint32_t)0x00010000) & t% {7 ~( g. {+ s4 N; H#endif /* STM32F446xx */% z Z/ C/ X3 x, M5 e #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) 0 H5 w4 N8 U8 y% |0 X#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)7 `8 V8 B8 J; b! d# C #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)# ?+ J7 {( o- q. D. X; L$ |4 c% u #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) ; g- B3 ]( I( d! z4 {#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)! D8 t( j! _- s! ` #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000). u+ {% {+ |2 I2 k" o6 n, k #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)* n3 Q1 Z; L* D4 a6 o #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)' R5 H5 o# X0 D) b# y: I$ X. r #define RCC_APB1RSTR_FMPI2C1RST ((uint32_t)0x01000000) ! b- r+ m/ e( T+ K#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */ ' M* B6 U9 `; t9 L#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)' J- Q1 ]/ M6 y8 b$ O+ Y6 ` #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) , u2 K V2 y. ]% O" X; r+ L* ^1 }#if defined(STM32F446xx) $ w9 U7 A3 R' G: [- D4 w e+ s$ c#define RCC_APB1RSTR_CECRST ((uint32_t)0x08000000)# b. c$ `" |$ Q6 O' U) ^# R3 B #endif /* STM32F446xx */ " |; C/ b: V- {; S: C#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) 1 S2 J2 O% D/ C7 [, Y#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000), R* S& q5 {3 I) R. ]( g9 _ #define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000), X7 l. u) G+ v$ G7 M5 V7 v7 b4 G$ r #define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000), z% i7 H, K0 ~% F6 X 1 s1 y- a2 s5 n; a, x9 O7 h7 |7 w/******************** Bit definition for RCC_APB2RSTR register **************/) X6 X7 T. s+ Q+ i- S O #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001) 8 i0 W) l9 x0 T ^5 `6 K#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)+ a# {* P9 r* r$ c #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010) ; g* ?$ H- D# B1 g3 O. m" z4 ~#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020) I, `/ Y$ t: f/ ]+ k" K/ B3 [2 k #define RCC_APB2RSTR_UART9RST ((uint32_t)0x00000040)# i! a& r# F+ a3 W' A2 @4 A; f #define RCC_APB2RSTR_UART10RST ((uint32_t)0x00000080) S" W) p. P& `" ?! V3 f+ ]! Y% B( p$ B #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)4 m! l2 A9 F' v% l# P3 U #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) 8 O+ }- S) p2 ^( e: G$ s# c#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) s6 m6 e/ u% s) J2 } w# C #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000); r- e2 ?# |( H" F3 Q #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000) / A$ d$ y5 }# g/ f, d+ r#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)0 A% p& X& l+ O- z' O #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)$ }, [2 @# X9 s: f #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000) / a" }9 D) V( p0 D7 N* z1 Q6 R#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000) - j3 q9 ^9 Q/ g, _$ _* }#define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000) , n% g, v' t: z f#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000) S, F$ D3 G y$ B7 e#if defined(STM32F446xx) 6 F" `* Y9 C$ |) z#define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00800000)5 d: k/ W/ W/ g H* K8 V #endif /* STM32F446xx *// \) n; V; e8 L9 }! { #define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000) 4 U% k8 B- u: l3 y#if defined(STM32F469_479xx)( @# V! ]. r' d5 L T #define RCC_APB2RSTR_DSIRST ((uint32_t)0x08000000)- Q6 K4 s% W. @) i; { #endif /* STM32F469_479xx */4 K1 f. T/ X! Z9 L #if defined(STM32F412xG) || defined(STM32F413_423xx) 5 c2 N9 y E1 R+ z3 r! D, D7 F$ [9 \#define RCC_APB2RSTR_DFSDM1RST ((uint32_t)0x01000000)' Z$ D3 H: t7 T #endif /* STM32F412xG || STM32F413_423xx */ 5 O6 X1 f: G! _5 t( y' o8 S% {; D S/ x #if defined(STM32F413_423xx) 5 D: W1 P* @6 X: L#define RCC_APB2RSTR_DFSDM2RST ((uint32_t)0x02000000) 6 Q6 F, e& X- Z9 Q6 x1 |#endif /* STM32F413_423xx */% N! }, X' S# u /* Old definitions, maintained for legacy purpose */; v& h+ ]- C+ ^) V ^. D6 N4 F* Q/ u #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST R) R6 |8 ?- i- G& |: h$ F #define RCC_APB2RSTR_DFSDMRST RCC_APB2RSTR_DFSDM1RST 7 H( w# a8 D) S8 g* z4 P3 g+ b( B6 }% k, w1 B1 ] /******************** Bit definition for RCC_AHB1ENR register ***************/ $ h5 r J# N% a0 A, `! d#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001) ' [. X4 o% g' {: S2 {1 _( G#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)3 C4 V7 f, q) Q1 n% R( l7 B+ O #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004) 8 q1 X( J! r! m& N#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008): ~7 B9 S$ t. \+ @ #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010) 0 x8 R$ Q. K( k, l7 h e% ?#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020) 2 d! n: A1 Z( M$ P, j#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)9 w% z4 g+ U$ V( {. k; h; d" h5 R #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080) 7 E6 |- O8 {4 k6 f, E#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100) * C/ ~5 l5 x7 |8 u+ i: _#define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)2 B, q8 r4 |9 T1 \3 M #define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400) . e; ~& N0 { f8 C" V#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)2 D a4 t: @4 n #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000) " a& X, _# C) @6 O" I P#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000) ( a o! x4 C6 a) D& A#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000) ; E4 f2 M7 G4 {: S: W+ R% h#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000) , s! [+ ]4 I2 r) H% E8 B2 Q! f#define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000) W+ A+ [$ K1 j$ T1 P #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000) T; t! P6 x3 Y! g) M5 \8 P- b6 [ #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000). A' I/ [. L" H #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)& J$ n9 L7 m( O5 O7 P% K$ C k #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000) , w8 Y0 z- e( V' }1 o- G' D4 p#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000) u8 ~" o6 [& m7 F7 j8 @, q3 p #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000) " E, Z( i8 O8 M 1 x- H# h! Z: T2 V# J/******************** Bit definition for RCC_AHB2ENR register ***************/ 1 g: D: M3 l6 b+ ?1 S# x. E#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001) 5 f2 J2 x2 m0 P3 j8 i#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010) 9 y& x1 y/ \; R& z& Y+ D! p9 v5 y% Z#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020) $ V9 j. F( l Z5 o! \#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040) 0 T- n G3 Y }, u6 g! M4 [#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)5 j9 H2 Z F ?4 C z% h' b ( `2 C7 ] }* S- H5 x/******************** Bit definition for RCC_AHB3ENR register ***************/ P8 ?+ `- w! {$ N1 A" C" Z, R ! @ H/ _0 `4 l8 N0 i( Q; t3 s #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) & J% G- Y9 x6 K#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)) f8 _: c; L& z- M0 z #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ + n7 W$ ]. R2 o( K) M- e- v4 {3 D #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) , T* O8 M6 \3 l( _# B8 `: ]" F6 ?#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001) $ N3 o3 L/ c9 i3 O: S# m8 Z1 t#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */' a% i2 a: |! z. W " B0 j3 w3 ^2 e, P' K- k #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) - K9 b2 q0 I2 u4 T4 ? P4 I$ [ p#define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)( L; f0 e; F y& G #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ 3 I( C0 e4 |, s( C+ h# p+ Y' T- u3 a; o1 i /******************** Bit definition for RCC_APB1ENR register ***************/( u1 u V! y0 x: J+ F' P #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)& A9 d" J: }4 A: O #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)9 Y7 `( A' l, T7 l; K4 } #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)2 A- A+ Q ?5 ^* p4 l9 f: K( V, t #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) ) O c% ^1 a. W, E#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)+ Q9 d7 W+ l8 D/ g( I #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) 3 n' @9 P! n# z#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)- r4 S# c$ u9 S #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) * V* ~% ?% B. |- a2 V+ F#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)& ^ c# q9 V; ]) I' ^% c6 z( s2 h. o #if defined(STM32F410xx) || defined(STM32F413_423xx)2 i3 w2 E6 X* Y; R: F #define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x00000200) 9 U S5 e3 m# Z& T+ Z$ [' r#endif /* STM32F410xx || STM32F413_423xx */ ( J) E1 | U7 l% o0 ]( s5 A% h#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) 0 ]1 V3 @. w5 ^; a C; V+ |#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)$ h$ T% g. s `% b6 G! v$ g #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000): Q/ v3 r% v5 G6 E- T1 ^ #if defined(STM32F446xx)8 w7 ~$ ^" E6 i, \ #define RCC_APB1ENR_SPDIFRXEN ((uint32_t)0x00010000)5 V# Y# f* ]; P t7 n #endif /* STM32F446xx */ 0 e g1 @! y" l. w1 ~) t#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) 9 P, |$ r" E% R4 H* W; q9 `! V#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)4 d8 a w0 m4 D #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) ( N' q1 b2 b1 y f#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) : y7 z) a4 A% I. B; s' V4 z) ~. m#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) $ u* t" Y8 h; i" x% l#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) 8 H" R) G, P7 s% N+ e* n9 A; R#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)) O( B! v0 V2 ^ G( _( { #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)6 g- y3 i1 ~! z& c/ q; P! s #define RCC_APB1ENR_FMPI2C1EN ((uint32_t)0x01000000) 1 F6 o4 U" G& T9 ~% i* W#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */ 1 |; I) C- B r* @#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) 7 A, |+ Q( `! ^7 ?#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000); E$ p% d# e/ c% j #if defined(STM32F446xx) * a- n3 k! k: Q6 X* v! C#define RCC_APB1ENR_CECEN ((uint32_t)0x08000000)8 b/ S+ Y: @2 J: @1 ^ #endif /* STM32F446xx */ 7 q& U5 ?& m6 d) _$ @$ Y8 e) b#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) ' O1 y/ x5 U. x0 z0 w#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)4 K w4 ^' @; a #define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)8 Y" `! H4 b+ r3 u9 s #define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)' T/ }& y) W& D Z: h * I8 t/ Y! j6 R" l /******************** Bit definition for RCC_APB2ENR register ***************/ : `! c( E) q0 m4 C& s#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001): Q8 w1 F. B% Y, D) j: ]. N Y! i #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002) % K( |* ?9 U1 W( @; v9 z l#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010) 4 t0 I3 v, j- C" g#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020) ) @$ n" Q/ }4 @9 S2 x0 y#define RCC_APB2ENR_UART9EN ((uint32_t)0x00000040) 7 z" M1 l' D: k+ g/ A' r: I#define RCC_APB2ENR_UART10EN ((uint32_t)0x00000080) ; X/ K8 j, u4 s6 r- _. Z#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100) ; w, x( G5 c, u5 h! z# N#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)0 b, J! ~1 v. v6 C0 N4 `) S #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)$ H! Q" r) r# C3 k! [# w #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) ; ^ R' R2 P/ u1 q#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)" k4 |% v# c' |! }: P' m #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)8 h) K" }1 G) l8 a1 U& I# _+ R #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000) , J! \$ C C1 G4 s# T#define RCC_APB2ENR_EXTIEN ((uint32_t)0x00008000) 0 [9 S% A8 o5 t4 X; W ?" X#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000) " j( L8 a7 w- b& d5 t' C6 X+ N6 n1 I#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000) n* n7 Z, b' t i' _1 f, R #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000) % D, n+ v( c" {% m) E#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000) " t2 b- D+ j9 W- R- O5 K: M2 p#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000) 0 l2 Q G6 C8 F- I+ R1 M k#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000) ; v2 v5 K4 z, Y. S' @+ x#if defined(STM32F446xx) 4 n0 e4 {: S" X#define RCC_APB2ENR_SAI2EN ((uint32_t)0x00800000); ~! F& |: e0 h* V; ^# c7 }! c #endif /* STM32F446xx */: n( Z/ k$ P- H$ }! h& v4 [1 C. w# v #define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)$ A- p: Y+ E, j: v1 m' _3 N1 V #if defined(STM32F469_479xx) ; y0 x3 M/ |3 s#define RCC_APB2ENR_DSIEN ((uint32_t)0x08000000) ; A; M; b1 z7 p) \0 F2 A#endif /* STM32F469_479xx */ & f) J9 x$ J/ @#if defined(STM32F412xG) || defined(STM32F413_423xx) ) _4 ^2 V' w0 D0 R( c! T#define RCC_APB2ENR_DFSDM1EN ((uint32_t)0x01000000)' P5 w0 F& ^7 c #endif /* STM32F412xG || STM32F413_423xx */2 c$ J, I2 F* r3 A2 z% g& C @ #if defined(STM32F413_423xx) ; ^6 I4 F" V2 ]# T3 P- x#define RCC_APB2ENR_DFSDM2EN ((uint32_t)0x02000000) 0 P, M o. M. d) V5 F#endif /* STM32F413_423xx */ 7 s6 }9 y; h. B/******************** Bit definition for RCC_AHB1LPENR register *************/ ) p# [3 ?5 u8 N. A' O2 o#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)* b4 F% F5 ~$ X) J+ Z #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)" ]% G0 A/ X- W- h. C0 _ #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004) & @9 M1 n0 I( J% d#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)/ z) v7 z5 K1 H ^: O #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010) , P; o" k* n2 r V) H# M" p4 m#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)0 w. @( B/ c# x1 v) h1 O #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040) $ D1 a# V% k$ D9 K7 g#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)4 ]# O$ }+ `7 T l+ p6 x #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)4 A7 K) ?- G8 \) X, P; X, w) _ #define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)" L1 v% e% F" Z/ M6 j/ b' Z #define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)7 d1 g: |7 y6 K0 b4 D #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)' S. e. r% X$ k1 s0 a #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)6 q- D2 I8 B9 p2 K7 y8 x0 u #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)) l& N7 h5 u. t @/ U. M2 q. m1 p! m #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)' F" A% l* f8 Z6 o6 M; A6 D #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000) ' Q8 y, k- a" @( _#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)$ Z q- p/ i4 B. \& I% `9 {% v* T #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)# p" U! ?# W* G- R3 O. D #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)1 N2 y0 ^# c/ X #define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000) 0 P5 X) G: z% k3 C4 R) Q' y#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)9 r6 o- ~( [0 Z' b, y9 v #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000) 6 L" C V8 ]8 u6 G#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000) ) a" q: v1 l. w X9 v$ V O#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000) + z5 {$ t' f! c# \#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)8 l5 ?% q, @- E' A% T9 N0 @ #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)* ^( l" m3 ^: L, \7 m " g6 }3 a0 E* b# ~- t; { y /******************** Bit definition for RCC_AHB2LPENR register *************/ $ i, I0 x* ?; `: E( B$ i/ |$ y#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001) $ ?: O# P9 J& @5 c$ u- C#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010), F. V, t$ l" d) ^) x6 v #define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)1 }7 V4 J4 C/ Y- U8 l% a9 x& C0 D #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040) ' C% I4 a" x1 H6 @5 _% ?- y#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)$ v6 H0 O4 P$ |. r5 D5 p 9 E5 m2 @$ [* Q0 {' K% i* T$ P3 r' c9 j/******************** Bit definition for RCC_AHB3LPENR register *************/: {; {7 o) H+ `4 t" @) s$ B) R #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)* W/ G8 s) z+ c( r- b8 Q" C5 x. D+ s #define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)% ~1 S& x% V: q$ ` #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ 1 [0 M: D( y2 ]. M- _3 w + x. W+ i3 b9 [& `2 w/ w4 M#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)7 `; G. Q) c6 `5 I& l( J #define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001) # u: D, p* W, D0 H3 c3 v#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ ) P t7 J4 Z$ Z+ q#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)$ N9 M6 c/ V; I% }* c# Z #define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002) , w$ g$ } f$ o#endif /* STM32F412xG || STM32F413_423xx || STM32F469_479xx || STM32F446xx */% `: G+ o+ o& Q" s$ \& W6 b$ `5 V 6 v! T' [ z' p, A# A /******************** Bit definition for RCC_APB1LPENR register *************/ ' I, ?* P) D# k( Q/ w, S2 F: E#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) 4 |, I6 c2 i* e6 r9 w f W#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)1 z" W$ }" u9 `4 d6 z. h #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) 9 @7 P5 p! l& j; \#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)3 \3 C) e0 b* v6 |% v8 W5 z #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)8 D& t( `# {% S D #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) : ~; Y, p5 L9 {$ {#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040) b; i1 r+ Z, p D9 G7 \" L C #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080) , ^) |& Y' M/ f/ r0 q6 U7 L- W; |1 q+ m#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100) , n% d% M9 ^" |0 M* Y0 o `7 G#if defined(STM32F410xx) || defined(STM32F413_423xx). t0 P/ S2 k: L3 M$ K3 W; Y+ S #define RCC_APB1LPENR_LPTIM1LPEN ((uint32_t)0x00000200)2 ~+ h/ |% x+ o5 ^" E( j' B& x% E; c #endif /* STM32F410xx || STM32F413_423xx */ # N6 t% W5 J5 }- e2 i( Z8 ?' v; Y#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800): k% I0 R' J# C' ~3 k0 D& ` #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) 6 ~8 |/ D: h2 p! W#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000): l, Z* S, Q) n. s: }* L& ^. Q0 N8 E #if defined(STM32F446xx)! N7 Z" ~7 D9 f) n! [ #define RCC_APB1LPENR_SPDIFRXLPEN ((uint32_t)0x00010000) 3 Q7 X$ i2 j( ~, I e#endif /* STM32F446xx */( @1 X3 @1 k' Y8 ]9 } #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)- Z, O! E( x' \ #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)+ t3 k& Z5 F) o #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)6 c/ Z; Q7 R* l: I } #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)8 n1 ?. l' `' h! a! X9 E #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) 6 M# I% d a9 R: }( y2 O#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) 1 g# p+ D0 k2 E" w#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000) # b" E( W$ d; D#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)8 l- v+ {' H4 r5 D3 h5 d" U' p #define RCC_APB1LPENR_FMPI2C1LPEN ((uint32_t)0x01000000)* @: A* {' c8 f; `' J6 @ #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */% v( m1 b* k$ O) b$ \ #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)1 v" c# E. X# y7 ^. _3 `8 [0 j #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000) ^: ?- p( h) C2 j, r& c9 r#if defined(STM32F446xx) K& f% D6 v- x' F/ j* r/ n #define RCC_APB1LPENR_CECLPEN ((uint32_t)0x08000000) 6 `# x; B1 Z! c#endif /* STM32F446xx */% \; L" L" e6 C5 a6 t #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)5 C3 L# |5 F! G #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) ( ~4 L2 X1 v6 {# g& R#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000). m1 T+ R) ]" [5 E: \6 o #define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000) 3 w) `/ b! S/ s- U5 A 2 W$ U [/ Z. g- a6 Z/******************** Bit definition for RCC_APB2LPENR register *************/# T/ S3 Y2 P- E! u3 C H #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001) : B3 L! w# @$ I" y$ i#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002) - }/ ^1 Q6 V' P' d9 p& A* D#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)4 N3 N6 C9 U" Z2 p( ~ #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)3 n" S; ^: ^; \5 W& T #define RCC_APB2LPENR_UART9LPEN ((uint32_t)0x00000040) " y/ ~1 a4 y2 m' i1 F#define RCC_APB2LPENR_UART10LPEN ((uint32_t)0x00000080)! G$ t d0 c4 f( s" ?. U1 _( C# G7 g #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100) - d) y0 Y0 p0 ~2 ?' i# E" o#define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)( j1 F% U" I! N #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)* X# r; }+ a, E% b7 |1 d2 f #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) : @3 w1 t* Z* Q- b5 F1 ~) s#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)! o2 C, b' }4 p5 b' r$ x# a; t' i #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000) ; g. C% t6 i5 N ?8 @# R#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000) # M& k u# r* v1 V9 ]#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)1 h8 K+ r( ?% V3 t N; y' W$ Z #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000) / U6 u. P1 {# ^3 l# g G#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)( d( [3 o/ N; k- R& h( L# d #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)6 ]9 X/ ~/ y% B! b' K1 s* P, v #define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)7 {' z) w' ^8 s/ m9 K2 O# C #define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000) - B8 L8 e% Y4 h- G9 x#if defined(STM32F446xx) 5 t% C/ H3 Y6 B#define RCC_APB2LPENR_SAI2LPEN ((uint32_t)0x00800000) ) @9 N& @$ P- Y0 m) v7 }: J#endif /* STM32F446xx */* l, |# f; [: u) @1 q0 S #define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)& ]6 W5 D4 I5 F; J #if defined(STM32F469_479xx)" M; V+ ^/ q! d5 u. J$ K #define RCC_APB2LPENR_DSILPEN ((uint32_t)0x08000000)# k/ O3 A* Z5 W6 t #endif /* STM32F469_479xx */# C* W5 i8 N; S #if defined(STM32F412xG) || defined(STM32F413_423xx) u% O4 u: T8 k5 ?8 a! [ #define RCC_APB2LPENR_DFSDM1LPEN ((uint32_t)0x01000000) . @. R R& d2 a) Y: f#endif /* STM32F412xG || STM32F413_423xx */" o: B1 S; t3 u2 _0 s U* ? #if defined(STM32F413_423xx) 9 i: _/ j- I& l q$ E#define RCC_APB2LPENR_DFSDM2LPEN ((uint32_t)0x02000000)" C3 r5 e' p6 j- w% J+ U* }- P #endif /* STM32F413_423xx */1 t. b5 X$ D8 V( ] # ^: r6 _( E6 Z4 ^ p+ E /******************** Bit definition for RCC_BDCR register ******************// I1 Y4 G9 N- w6 D #define RCC_BDCR_LSEON ((uint32_t)0x00000001) 3 P6 Y" [0 p5 p& A#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) ! x( Z+ c. g, e0 J#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004). p: X8 }# R$ h7 R _' P8 R9 H5 g1 _ #define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)$ f: k- U! B+ F! V/ E$ Q 3 G( m2 D' q$ G #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)9 P1 Q9 X. B* |6 U" x% @" t5 e #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) " C& [" p% u( \#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)$ d1 [& M% g" G) [) F* {/ c# _ 4 _# e8 A" P3 O#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) ' x; Z c( b* e( y) E#define RCC_BDCR_BDRST ((uint32_t)0x00010000) ! y/ p: B0 K0 l4 q q9 X6 N/ Q4 r/******************** Bit definition for RCC_CSR register *******************/& x3 E. w. x" `& z# f% D #define RCC_CSR_LSION ((uint32_t)0x00000001) . p& h: w. `: h/ k1 T#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)# L4 p& [7 P( Q" y #define RCC_CSR_RMVF ((uint32_t)0x01000000)( h' R2 L, Z) K! b #define RCC_CSR_BORRSTF ((uint32_t)0x02000000) 4 ^9 Z, M! B4 W, A#define RCC_CSR_PADRSTF ((uint32_t)0x04000000) : G- T/ X& C* L1 L% F- B1 N#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)) P. {# R" t2 c% S* V! g #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) 7 t+ T7 d4 o! V#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000) % G5 r' `; {1 k; P6 `#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)+ H4 A0 y. R$ d7 c1 P #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000). A9 V0 m. Q8 B 6 d2 i1 [/ J- p1 M/******************** Bit definition for RCC_SSCGR register *****************/; `! @! G/ p7 v6 ~. e, z- d #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF) 0 c M- k5 n, P. |5 T+ s2 S2 M#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)7 g2 @. R7 y6 P5 r" e #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)' N$ i/ o+ `( }/ I #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000) 9 y6 a2 X# x1 J/ D$ N7 B/ X7 i' S# L& l2 E! I# v /******************** Bit definition for RCC_PLLI2SCFGR register ************/ - H: q, Z4 \9 r* p: J#define RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F); @2 | @3 K& G #define RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001)' f! T- o6 \$ S/ |2 \- o/ I #define RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002)3 O7 C& I+ \1 J& S #define RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004)% D+ E; L% k9 o. s7 Y3 r #define RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008) ( B0 ^5 ~- c8 [* \% v0 R#define RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010) : ^0 q) g* W! V" t& y#define RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020); c+ s' L, ?) X, G- ^ : e. Z7 C9 }; S7 T7 {, ~ #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0) 0 s2 G2 F) T; j6 n% l#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040) t# i' x2 O0 S: J) N #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080). c @8 u z3 j- h: u" w9 f; } #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100), R% Z4 J% V) E, B+ c* e- J #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200) 6 q$ m5 Q% d" g/ {#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)) {) Q2 Y, H1 r2 e) L- p" O #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800) . J0 @( O! n; n/ E1 r- Z#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000). i4 C0 |) ~% b) t #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)$ F; B6 S2 d7 L #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)& I% |4 P2 f# f8 | 5 o9 `* ?4 v: [9 `1 ?, j #if defined(STM32F412xG) || defined(STM32F413_423xx) @/ Q! ]+ b% E- i5 ? #define RCC_PLLI2SCFGR_PLLI2SSRC ((uint32_t)0x00400000) # o$ B0 @* v, I7 h- h( ~% F#endif /* STM32F412xG || STM32F413_423xx */ 8 e* A6 i' m& G/ t4 H( W" k+ B. V( b& Y; { #if defined(STM32F446xx) Y8 ~% z; e0 f/ s# Q7 q8 D#define RCC_PLLI2SCFGR_PLLI2SP ((uint32_t)0x00030000)( }/ [4 L. g9 s$ ? #define RCC_PLLI2SCFGR_PLLI2SP_0 ((uint32_t)0x00010000)' S; ^3 V6 A( c #define RCC_PLLI2SCFGR_PLLI2SP_1 ((uint32_t)0x00020000) : u7 P$ D" K- C, ?: q#endif /* STM32F446xx */" P5 M( a) V, w4 l4 C- x$ d2 a , @+ g; v' {5 x. j$ C" ~$ B" J#define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000) " w7 X1 A) n. A5 E$ Y, ^#define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000) . l& E1 j3 o. X8 G+ B+ D#define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000) : D) m; V% u# K& l( Z. c! e+ [#define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000) 6 D! C, [& `+ _6 o#define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000) " {# F# N6 A" } ' ~! m) E, a0 K0 Q6 u+ t# c#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000) 2 `3 Q& z7 h1 m k. |#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000) / H% @0 T; ~6 q& |# c#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000) 2 r R8 _* \7 C+ Y( u#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000) 8 Y: N e4 _9 q$ o" I' }; F O3 o8 b6 ? /******************** Bit definition for RCC_PLLSAICFGR register ************/- Y: M) @! H. Y, V+ c' A$ H6 X #if defined(STM32F446xx)7 V) q. _2 g. q/ \ #define RCC_PLLSAICFGR_PLLSAIM ((uint32_t)0x0000003F)' p) R' F3 W: q7 g" W) Q #define RCC_PLLSAICFGR_PLLSAIM_0 ((uint32_t)0x00000001); B" D' z- Z* ~3 s0 S4 x" G #define RCC_PLLSAICFGR_PLLSAIM_1 ((uint32_t)0x00000002) / b. Z& i' \1 q0 `6 r#define RCC_PLLSAICFGR_PLLSAIM_2 ((uint32_t)0x00000004) 3 ` ]2 b0 g! u, M. E#define RCC_PLLSAICFGR_PLLSAIM_3 ((uint32_t)0x00000008)4 p5 j6 G$ t' q5 @7 U #define RCC_PLLSAICFGR_PLLSAIM_4 ((uint32_t)0x00000010) 7 C& k0 e2 R1 H1 k#define RCC_PLLSAICFGR_PLLSAIM_5 ((uint32_t)0x00000020)0 \9 S5 w# Z) r #endif /* STM32F446xx */, f; M/ @* v" [. u* X 2 o! d8 b; e c7 Z; X0 h #define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0) + u6 t- A- x8 k) S& `( X# ]5 q#define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040) 1 W8 Y; \" Z9 p# ^- d( o1 U5 s9 W* Y#define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)2 |7 z) \$ Y" s1 {8 M6 f #define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)9 r$ T) U# Q0 ]0 u9 o) B #define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200) 1 m V9 v9 j: ?) y [- R2 F% a#define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400) ' `: U/ x! t$ B, n0 I0 G3 H#define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800) ' X4 c7 O8 `5 {#define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)/ j. A8 X5 i5 i; H6 [. u #define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)7 P+ g, Q( k# F4 t1 S #define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000) & C% k" p* P9 B8 J( m# S2 x- E+ U3 E& E+ o! v7 C( F# x- q* P! t #if defined(STM32F446xx) || defined(STM32F469_479xx) / f& Y: _, g. x6 l( }$ I#define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000) / r" X) B v6 z6 y2 {5 ]#define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000) 9 a- q" g3 g9 _) D7 U! L% [, e6 A( @#define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)0 D' N' G+ H9 T #endif /* STM32F446xx || STM32F469_479xx */ ' x. o8 ]' C6 }+ e5 _" q * U1 D! @1 Z4 _#define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)# p: k# h- m1 W) i5 H #define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000) * T* q( t! J6 T* J+ b* ]0 [/ @. l* H' [# _#define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)" R) @$ Z: T' j! F% P #define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000) : z5 H! v, m$ i3 V1 v3 g#define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000) ( D0 O, B1 h3 ?( f6 ?3 y9 S/ u; N9 p- @7 } #define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000) 3 O. E: q7 j }7 f5 m/ Z#define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000) 8 q4 T5 k$ |/ g" w' B @( N#define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)* o3 q* z* Y: }* b6 @, W$ W #define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000) 3 G1 w# \7 Z1 i7 C/ Z, m: h" G I7 U- @, r3 H /******************** Bit definition for RCC_DCKCFGR register ***************/ ( H! [0 {* O9 j1 L! T: l! K4 {#define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F) / V* A- I' C) F* g6 v' M; n#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)# w+ @- U. ]" Q! R9 o #define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000) ; S' l+ A \3 A2 c9 a 1 w4 {4 l; x: q3 w9 b#if defined(STM32F412xG) || defined(STM32F413_423xx). ]& E9 X$ Y( R2 v) \) d! k3 c& K #define RCC_DCKCFGR_CKDFSDM1SEL ((uint32_t)0x80000000) A3 K1 B. d0 B1 ^ c. [1 i #define RCC_DCKCFGR_CKDFSDM1ASEL ((uint32_t)0x00008000) ' M/ b3 U x" W2 n; Q#endif /* STM32F412xG || STM32F413_423xx */6 _3 {$ y4 O. w + v" ^7 i% W/ q#if defined(STM32F413_423xx) : W: d% Q( N3 H' o" g3 _' S7 i5 f#define RCC_DCKCFGR_PLLI2SDIVR ((uint32_t)0x0000001F) 7 Q# f+ p6 S9 @) K#define RCC_DCKCFGR_PLLI2SDIVR_0 ((uint32_t)0x00000001)7 o9 h" ?. t" o; V #define RCC_DCKCFGR_PLLI2SDIVR_1 ((uint32_t)0x00000002): H' e2 R: H7 U7 \ #define RCC_DCKCFGR_PLLI2SDIVR_2 ((uint32_t)0x00000004)% |9 D" s' i# Q #define RCC_DCKCFGR_PLLI2SDIVR_3 ((uint32_t)0x00000008) / f( }2 m: d6 n- n3 H6 S#define RCC_DCKCFGR_PLLI2SDIVR_4 ((uint32_t)0x00000010) 1 z! u0 ~, a1 ~1 b6 g& n/ Y1 `6 ^! Z t #define RCC_DCKCFGR_PLLDIVR ((uint32_t)0x00001F00)- }3 i8 ~4 j2 { #define RCC_DCKCFGR_PLLDIVR_0 ((uint32_t)0x00000100); z; w* r6 c" y$ O: T #define RCC_DCKCFGR_PLLDIVR_1 ((uint32_t)0x00000200) ; x e+ e+ p( [6 \, ~' |& T( m#define RCC_DCKCFGR_PLLDIVR_2 ((uint32_t)0x00000400)5 q3 q. W3 T, m #define RCC_DCKCFGR_PLLDIVR_3 ((uint32_t)0x00000800) $ t; U& t7 w3 v#define RCC_DCKCFGR_PLLDIVR_4 ((uint32_t)0x00001000) , B9 A, q% i& b! K6 ?% L#define RCC_DCKCFGR_CKDFSDM2ASEL ((uint32_t)0x00004000)0 v- y( P. h6 n #endif /* STM32F413_423xx */. |, f- H, ^2 q5 z0 x7 B) E 9 y s( R5 r8 y6 f- M0 T4 ]: T #define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)1 x U. V0 Z- ^# s: n #define RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000)- c- }* c: d$ U #define RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000) : h2 Y4 T( e0 A' X: X& o# q0 Y#if defined(STM32F446xx)' P9 s5 V" i0 y1 e4 | #define RCC_DCKCFGR_SAI1SRC ((uint32_t)0x00300000), [8 B/ Z! f& z8 \/ w# q) p #define RCC_DCKCFGR_SAI1SRC_0 ((uint32_t)0x00100000)3 z9 y2 z1 |; X1 U- t l" L& X; k #define RCC_DCKCFGR_SAI1SRC_1 ((uint32_t)0x00200000) 3 Z. d- E' t: }" Y#endif /* STM32F446xx */" q5 C+ w2 L" K% K& z / G8 s; c* F4 D3 o4 | #define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000) * f9 A, { U$ I#define RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000)( ~' G7 k/ ]" a) F$ n4 w #define RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000) $ s9 V( ]0 e0 c6 |# c#if defined(STM32F446xx)) s, Q4 D8 A9 D #define RCC_DCKCFGR_SAI2SRC ((uint32_t)0x00C00000)- C6 d0 Y$ O. N: ?! X #define RCC_DCKCFGR_SAI2SRC_0 ((uint32_t)0x00400000)# }- V; `; m& b: m #define RCC_DCKCFGR_SAI2SRC_1 ((uint32_t)0x00800000) ^+ [1 w/ U; F# l #endif /* STM32F446xx */# L9 J. T- H& g 9 h2 Q6 |" \2 i8 w" D #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)( N/ h! a" Q" x8 \0 p #if defined(STM32F469_479xx) / T8 e/ Z& [# Q7 Q4 l$ `#define RCC_DCKCFGR_CK48MSEL ((uint32_t)0x08000000)* [1 U @( s$ p( \+ s7 o7 @, P& y5 G #define RCC_DCKCFGR_SDIOSEL ((uint32_t)0x10000000) / D; A! K6 f5 O5 M#define RCC_DCKCFGR_DSISEL ((uint32_t)0x20000000) 3 g; Z- Q! m+ w2 d5 s#endif /* STM32F469_479xx */( J, L& I5 z) s' {- ?5 @% N1 s 5 o$ `5 j& V. Z8 n #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) / l& N' ^& ^8 S7 Y U; d#define RCC_DCKCFGR_I2S1SRC ((uint32_t)0x06000000)3 j' u. ~1 u7 b #define RCC_DCKCFGR_I2S1SRC_0 ((uint32_t)0x02000000)5 E1 t1 B: P' w0 `' U6 J. a #define RCC_DCKCFGR_I2S1SRC_1 ((uint32_t)0x04000000)! L a# I4 U7 b1 m% u #define RCC_DCKCFGR_I2S2SRC ((uint32_t)0x18000000)% R6 t! K$ r: T* r #define RCC_DCKCFGR_I2S2SRC_0 ((uint32_t)0x08000000) J: G% B$ }+ P* C* h- [2 c0 P9 a#define RCC_DCKCFGR_I2S2SRC_1 ((uint32_t)0x10000000) 4 i, r8 z4 Q# q/ h6 G0 I9 F# q6 |( R2 c; L: l0 j9 t /******************** Bit definition for RCC_CKGATENR register ***************/ , c6 _) s9 ^1 A# n9 P#define RCC_CKGATENR_AHB2APB1_CKEN ((uint32_t)0x00000001)7 Y f, Q; U; U9 [1 ] #define RCC_CKGATENR_AHB2APB2_CKEN ((uint32_t)0x00000002); r$ e+ U: a B$ U! ? #define RCC_CKGATENR_CM4DBG_CKEN ((uint32_t)0x00000004) 1 @. @+ U& a/ r8 O* _#define RCC_CKGATENR_SPARE_CKEN ((uint32_t)0x00000008)$ b" p6 B7 x' _- T4 k #define RCC_CKGATENR_SRAM_CKEN ((uint32_t)0x00000010) * M2 F& r9 s: B) i0 g" i$ ?#define RCC_CKGATENR_FLITF_CKEN ((uint32_t)0x00000020)4 u: I5 D1 o# Z& Y8 T( i- H1 A ` #define RCC_CKGATENR_RCC_CKEN ((uint32_t)0x00000040)2 y2 g/ a3 f2 u! W5 V: ?* J) { #if defined(STM32F412xG) || defined(STM32F413_423xx) 0 I% [5 \$ M. H m/ c+ @0 l; K; Q#define RCC_CKGATENR_RCC_EVTCTL ((uint32_t)0x00000080) % W' ~5 g, L7 P; c2 ~ s: L#endif /* STM32F412xG || STM32F413_423xx */) c% q# T: I+ i: | 5 Q' a3 b2 z! t8 |: }/******************** Bit definition for RCC_DCKCFGR2 register ***************/; x! |. C$ f2 K #define RCC_DCKCFGR2_FMPI2C1SEL ((uint32_t)0x00C00000) 4 ~$ n6 g; W3 h4 W% V#define RCC_DCKCFGR2_FMPI2C1SEL_0 ((uint32_t)0x00400000) # Z8 B+ U0 Q# _' r4 d: o#define RCC_DCKCFGR2_FMPI2C1SEL_1 ((uint32_t)0x00800000) # k# G7 I: I6 O#define RCC_DCKCFGR2_CECSEL ((uint32_t)0x04000000) . s3 C! h4 P9 x; s8 k/ ^* J#define RCC_DCKCFGR2_CK48MSEL ((uint32_t)0x08000000) 1 b( I" c$ y+ H4 v ?, ]$ C8 d#define RCC_DCKCFGR2_SDIOSEL ((uint32_t)0x10000000) * @5 ?" a, C" o#if defined(STM32F446xx) 3 n0 m+ B- E4 `1 m#define RCC_DCKCFGR2_SPDIFRXSEL ((uint32_t)0x20000000)/ _; ]& R5 N& @1 }' K. g #endif /* STM32F446xx */ 7 K- C+ s% Z6 V8 D0 X3 ?4 a6 Q#if defined(STM32F413_423xx)5 w; C5 L" \" Q7 p; J #define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0xC0000000) 9 ]( ~8 z2 Z3 r+ T# V8 \1 ^#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x40000000)5 `& x$ B, f% D" {( `" c #define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x80000000) g$ t$ A7 o& D9 j2 Y #endif /* STM32F413_423xx */ * R; A0 x. F: H% a$ \- Y#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */" f* L% z- Y. `3 Y7 X 6 N7 u8 P% }' X& g/ X #if defined(STM32F410xx) . }+ _* z. l" I7 w) ?#define RCC_DCKCFGR_I2SSRC ((uint32_t)0x06000000)+ B5 |4 I/ ^7 ^" ^ #define RCC_DCKCFGR_I2SSRC_0 ((uint32_t)0x02000000) / X' V7 Y V- G/ i/ V+ {#define RCC_DCKCFGR_I2SSRC_1 ((uint32_t)0x04000000) " S+ C6 y: F* N#endif /* STM32F410xx */( a3 [7 E0 J1 _* ?: O! [* ` @ ' [3 O' j& @" o0 ]8 j/ h# [9 |2 c #if defined(STM32F410xx), c7 y) e+ L, l /******************** Bit definition for RCC_DCKCFGR2 register **************/+ e( I6 g) _1 \ #define RCC_DCKCFGR2_FMPI2C1SEL ((uint32_t)0x00C00000)2 U0 c2 C9 W3 {8 |1 Y$ ~3 E8 p #define RCC_DCKCFGR2_FMPI2C1SEL_0 ((uint32_t)0x00400000) - k( d( Z% a4 t: j7 p/ Q#define RCC_DCKCFGR2_FMPI2C1SEL_1 ((uint32_t)0x00800000) 7 S6 x9 L+ p N; w/ f$ O% Y( T#define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0xC0000000) 3 ?7 y* w! u% V#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x40000000)# i4 }4 f. T3 a+ e$ a #define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x80000000) / f3 ?0 Z6 N6 c6 P#endif /* STM32F410xx */ 3 x) [7 [6 V9 d3 a# N& `复制代码 3 q" t3 A+ f) T/ b f S) D ; K8 g' v3 P" V

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STMCU小助手发布时间：2022-6-10 20:14

技术帖
文章封面:
文章简介:	STM32 时钟相关函数和类型

01. 概述
在 STM32F4 标准固件库里，时钟源的选择以及时钟使能等函数都是在 RCC 相关固件库文件 stm32f4xx_rcc.h 和 stm32f4xx_rcc.c 中声明和定义的。大家打开 stm32f4xx_rcc.h 文件可以看到文件开头有很多宏定义标识符，然后是一系列时钟配置和时钟使能函数申明。这些函数大致可以归结为三类，一类是外设时钟使能函数，一类是时钟源和分频因子配置函数，还有一类是外设复位函数。当然还有几个获取时钟源配置的函数。

02. 相关类型
RCC_ClocksTypeDef

/* Exported types ------------------------------------------------------------*/$ x9 T# {1 n2 c4 O7 H( y8 ?# G
typedef struct
: S/ q' C! y- y* b3 S& |" ]
{
' E+ s5 |! c5 ~% S8 e, e
uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
( e& c0 u. w! I% X/ M
uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */; t% p+ ~+ X+ t; T: b
uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
! t7 Q( y" F2 w7 l& Z
uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */6 Y5 M. w/ ?! Y7 {- _
}RCC_ClocksTypeDef;

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RCC_HSE_configuration

/** @defgroup RCC_HSE_configuration
: l! k/ q$ H& }2 B Z, a" M
* @{
; m* d% N# z# ^, l; i! V
*/1 [% x2 F2 e' J3 O# ~
#define RCC_HSE_OFF ((uint8_t)0x00); ~7 u; }1 d: b G3 v" ^7 q. c
#define RCC_HSE_ON ((uint8_t)0x01)
! I! o! N4 [+ d
#define RCC_HSE_Bypass ((uint8_t)0x05)
2 o5 L! R* \0 H
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \+ j5 H2 ^1 _, q6 a; V% W. Z
((HSE) == RCC_HSE_Bypass))5 f# M6 [4 w) d" ~) U! J( O

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RCC_LSE_Dual_Mode_Selection

/** @defgroup RCC_LSE_Dual_Mode_Selection
2 P2 q0 _& U7 w9 F
* @{7 J6 {5 g% E- `: z1 R2 s( x
*/
t: Y$ i! K% b& |
#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
( d c/ V* [. z! V
#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
( Q" M5 @& a, p3 f1 @3 w, S/ \
#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \8 ?8 k' n: v. K- S+ p9 ?
((MODE) == RCC_LSE_HIGHDRIVE_MODE))

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RCC_PLLSAIDivR_Factor

/** @defgroup RCC_PLLSAIDivR_Factor, b7 g: r4 u) b3 I# X& k
* @{
% G: j6 y K+ [& z6 j) q, y+ f
*/1 n2 ]2 ? @! r( p! u5 j9 R& b
#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)
9 a* r0 q9 s! [9 c8 U
#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000) X" |; T- ~& `: c
#define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)
) E9 ?6 [ \8 X R# z! u8 E# P
#define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)) s, e/ Y/ a+ f$ v. Y+ g
#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\) S& R4 F4 y% g5 |: ^
((VALUE) == RCC_PLLSAIDivR_Div4) ||\
( `# x- O9 _6 H# h$ C
((VALUE) == RCC_PLLSAIDivR_Div8) ||\
2 W# e% \. t H7 k0 K8 f
((VALUE) == RCC_PLLSAIDivR_Div16))
: U3 k% t6 g6 [. Q. F

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5 Q& @( e: F3 ]* V; S$ uRCC_PLL_Clock_Source

/** @defgroup RCC_PLL_Clock_Source h: U% h) A* c3 I9 u, [' \: v' @1 k& Q
* @{' O( n" s) z5 Q8 j( j/ j
*/6 {2 v. ]+ _5 w
#define RCC_PLLSource_HSI ((uint32_t)0x00000000)/ x$ ]3 p( T" I, t. M( B. p
#define RCC_PLLSource_HSE ((uint32_t)0x00400000)/ a1 X8 u+ d6 j7 x8 g8 y
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \4 t$ ]5 G" H* J& Q- a
((SOURCE) == RCC_PLLSource_HSE))
+ z* R" a; F; I/ R
#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
7 Z' x+ f) n8 W* m' t
#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)), ~8 t0 P4 N+ @9 _
#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || + v' h8 c" a8 P/ [% a
((VALUE) == 6) || ((VALUE) == 8))- ]( q; s' |1 Z2 N7 H
#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)). C$ S) [3 Q+ d; a+ K# ^. f& D3 w. Q8 c
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) 7 k2 i* c' Z* ?
|| defined(STM32F446xx) || defined(STM32F469_479xx)
2 |' x1 h% k2 Z# W* V1 l' b
#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
7 {/ E2 r- Y- _ V$ {8 }9 g0 B
#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx
- @8 b9 T5 A! q% ]; m* i
|| STM32F469_479xx */6 i) t) o1 A$ M% J) z) C: {
# e5 t2 e1 Q* C
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
% t% D( D9 ?: d+ E4 A
#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
, H8 d) w% Y, D! J+ j6 D) D- z
#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))/ `$ b- t1 i6 l7 s: w+ ?$ j- a( a; v/ w
#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))% X$ U0 r H W+ b1 g, f+ P
#if defined(STM32F446xx) ) a9 V4 ^0 Q9 r. ?& G
#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4)
8 `# X0 M% ?' D) X4 q
|| ((VALUE) == 6) || ((VALUE) == 8)); [- f9 u: {. _1 x8 ]1 Z
#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
( K5 D# I$ H) C/ b" w/ \
#elif defined(STM32F412xG) || defined(STM32F413_423xx)
. H1 j/ Z3 i4 W2 F
#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4)
) b" H; d: o$ n& M
|| ((VALUE) == 6) || ((VALUE) == 8))2 D% O& \' \/ w% v
#else
4 D! Y. i l$ T: }* N
#endif /* STM32F446xx */- ?/ g {6 d8 y, m
#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
$ Z' L9 Z( N9 x( H8 R; ~& U
#if defined(STM32F446xx) || defined(STM32F469_479xx)
- j3 W' [# W9 k# j! K* U
#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) % p3 X3 }" `1 x% T
|| ((VALUE) == 6) || ((VALUE) == 8))7 U2 a4 l( }! ^
#endif /* STM32F446xx || STM32F469_479xx */$ w* ?) e4 o" w8 _
#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
' l( C6 k- ]7 b* @
#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) # q! V$ H1 U) q, d) q) ^
; A* |- Y( N) s. K5 o" q
#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))4 S# G3 |- I8 m; ~8 H* O
#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
" v, T4 m& H; p& }1 s" n6 Z
6 C" Q) [) G5 R9 e
#if defined(STM32F413_423xx)0 I/ V" Z0 ~ `6 k0 H: [9 o/ z9 \
#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
1 {1 O2 `+ R6 q- c; ?* T5 f
#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
& f* o4 F* D/ p ]
#endif /* STM32F413_423xx */# ?7 O' C1 g# |& ~1 C

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RCC_System_Clock_Source

/** @defgroup RCC_System_Clock_Source n6 E7 d! m" r, M9 D
* @{
. f0 F+ I( F8 A) b. M! s( h
*/
# B% x% P) a9 {! L' d8 `% M w0 I
/ }3 p! O, h' G& v! N: h
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)/ @4 m+ r; e3 N: q0 i
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)- J% I, J4 f% q5 I* L. `1 k% R4 N
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)6 s$ ~. |; E/ \8 q9 R. l/ U0 ~/ a
#define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002)
3 }( r) V2 Y$ t' A( [
#define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003)
# ]' S Y8 U9 K0 o* A9 l
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
) r6 d' ]! _: x9 k* h
((SOURCE) == RCC_SYSCLKSource_HSE) || \- ]9 p! P3 x% u1 U4 Z# M4 v. c8 C
((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \
* J& P6 J) l) w9 X0 F
((SOURCE) == RCC_SYSCLKSource_PLLRCLK)) }5 @/ r; T3 \( a
/* Add legacy definition */! K/ {/ b& z+ O0 ?
#define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK : a- M# \7 z; y k- _, T
#endif /* STM32F446xx */. p) n1 C L! @
8 u9 P# @: @% [
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) a$ |. v3 p) b, c
|| defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) 0 X; A5 t7 X& t* k0 F5 k! H6 a
|| defined(STM32F469_479xx)
: U1 ]/ P0 P' h1 q6 g
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)- P _8 I/ q7 C+ p2 J+ L
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)9 O4 x. k7 a7 g6 B6 a; z8 I
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
) X# F: L; b+ L2 E/ r, e8 }: Q
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \9 c! i: K# W6 w
((SOURCE) == RCC_SYSCLKSource_HSE) || \' Q4 x/ D/ F) T% k" g
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
' f0 `& u3 w9 ]& H. M
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx
. @5 u0 d, [7 R# }' W- p
|| STM32F410xx || STM32F411xE || STM32F469_479xx */ 7 {) R, V, [) C! W/ X/ G& L' n

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RCC_AHB_Clock_Source

/** @defgroup RCC_AHB_Clock_Source
* @{( {7 a: x X ^
*/1 z0 D; |) k6 ~7 P6 F- ] j z
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000): P5 q2 k& a6 T, |& T/ _
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
- m( t! R1 Z8 x
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
; J7 Y: W* ^' v2 N4 t4 q, z
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)" q; v$ R* u! B8 y. k! L# j
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
8 q/ e3 A s& f2 H- g
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
3 q# i' k* U) d6 _! S, u# U
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
7 M. C) [8 ?! G; k5 N! E0 e
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)4 U) V- d" w2 A( F3 O/ S$ j
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)8 o7 }1 I, p! G5 F- W
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
! o) O [& \5 r+ G
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \' ^! O/ e3 P8 B' D/ C4 }2 `, |
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ |. a; r0 @$ {. Q8 Z2 f$ J4 w8 Y
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \( x3 [6 @' d7 ~, p/ |3 I. X$ M
((HCLK) == RCC_SYSCLK_Div512))

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RCC_APB1_APB2_Clock_Source

/** @defgroup RCC_APB1_APB2_Clock_Source
[. ~- ? i% K& w3 j
* @{
& t$ R! E4 X9 g3 ]" z$ t, B$ ~
*/. S3 I2 ~/ V+ d) Y& I4 w' Y: Q2 D
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
. V7 E3 w$ Y3 F2 f5 I5 Z
#define RCC_HCLK_Div2 ((uint32_t)0x00001000)1 Z: t* R/ v7 l
#define RCC_HCLK_Div4 ((uint32_t)0x00001400)
" w$ H* Z% o. x1 s2 ~4 V0 c
#define RCC_HCLK_Div8 ((uint32_t)0x00001800)
- j: Q( k9 n% P
#define RCC_HCLK_Div16 ((uint32_t)0x00001C00)1 w0 V% N6 N% b
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \5 Y& C$ O% B5 u" O
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \2 A# @& w8 u4 u" C) k
((PCLK) == RCC_HCLK_Div16))
! W- a' \" J. s; n6 p* c

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- [+ f8 U! [& O0 Y6 G6 r* q: p
RCC_Interrupt_Source

/** @defgroup RCC_Interrupt_Source " e* f6 g) r* Y
* @{
& x. i+ c+ w" c
*/
+ ^9 c- I7 Q. F. b6 B
#define RCC_IT_LSIRDY ((uint8_t)0x01)
/ K# y/ n' M5 X- S0 ~, p A" f; ~$ O
#define RCC_IT_LSERDY ((uint8_t)0x02) v# g ?* X4 m+ q) e6 e! U% Q- A
#define RCC_IT_HSIRDY ((uint8_t)0x04). F# F& E+ A8 O) K
#define RCC_IT_HSERDY ((uint8_t)0x08)
3 ?( S, U" o1 @$ t$ t
#define RCC_IT_PLLRDY ((uint8_t)0x10)
" |; K( K; g4 X9 c5 j$ W
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) ! _& K3 `+ [& `. G1 m
#define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
3 I9 f; k' u$ F8 D, o7 O) J
#define RCC_IT_CSS ((uint8_t)0x80)' l1 g0 m1 Y) R0 y, H3 x5 R
4 J8 G# Z% X* j3 A2 G: H/ ]
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
; r" R& H: {# ~0 q- P/ V
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \4 h0 `0 W( s$ d; P1 X9 l# d. m8 U
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
. U! E* e0 L5 w# b! {* V% ?
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \! t- }, h( n5 e K: R
((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
) g+ D! B! P# m6 d( L! g# P
#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)6 ?' ?% c+ l( I- {

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RCC_LSE_Configuration

/** @defgroup RCC_LSE_Configuration . Q6 W% ^9 z. C) @! p- a' \- r
* @{
' b- [, b0 k2 U9 Y- l
*/
/ y1 L+ b3 e" v1 y6 m: K! T
#define RCC_LSE_OFF ((uint8_t)0x00)
, M R3 `! n0 o( d# Z% b9 n
#define RCC_LSE_ON ((uint8_t)0x01)
7 @. M* _& s, \: w/ F
#define RCC_LSE_Bypass ((uint8_t)0x04)
! E5 ?# P# m' F7 i3 P" y
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
/ d) _; a" \: u) n5 r# H( R( l
((LSE) == RCC_LSE_Bypass))

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* U, {" y+ N( R3 f: q$ F% ?- @
RCC_RTC_Clock_Source

/** @defgroup RCC_RTC_Clock_Source
- ~$ Q& Y0 V& ]" f0 B8 U4 c
* @{
; {7 l, \! R8 [+ {3 B: ^! p
*/
2 d3 T1 P+ a6 O$ x
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)$ i8 r. U7 a0 \ ^8 P
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)$ Z" v+ ?& g8 c
#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)
- d! Y* J5 @. ^: U, V# e: @+ ^
#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)* }, ?- h: p3 S8 m
#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
9 \; l" o# d$ }, J" G) m
#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)3 J# C, }9 z; H
#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)' Q% J. J. M* _$ ^2 J4 f6 ?4 u
#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)3 E6 A" L$ ^( a/ n6 z8 e
#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)
! @' U0 Z3 J. c; Y, U$ [
#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300), K9 T8 {3 a' F9 n3 N
#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)
, y8 u1 n# b. J* c2 l4 C* p; Y
#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
* Z( y( \- {; J, @ c9 }+ P. L
#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
/ @. j; R# H: @# y8 ^9 z4 y
#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300), z; n4 l* f# m2 r
#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)" u j& Y" N; h0 j2 q
#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)& t$ Z2 A) d! D' k0 g
#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
* d- T& B ^' A: q: g% P6 m8 R6 c/ _
#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)+ }; a0 y- r1 J5 F$ K
#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
9 {+ w# y' ~5 e" T4 c( ]# ]
#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)" T* l7 ~: z" b5 H' h
#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
/ s( o4 p% O/ Z* ^: [3 M8 _
#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)4 z1 C, L' M/ Q3 y9 o% V
#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)
6 k8 Y0 O9 [2 U3 s1 ?- u
#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)$ l, m0 j2 [% }9 H9 H& n. x
#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
2 x9 e1 h" n) y: L1 X" a# H
#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
$ U$ \; k& {* D6 c4 ?% v
#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
2 W# m* e- k9 S. Z. c! @
#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
! a, s( b! ?1 [2 O* S
#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)- m- S* u1 R3 L& c8 ^
#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)6 l* g2 l; O4 X- ]9 Q% H
#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
; x2 `) j+ w& q* d' B( E# [
#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)* f8 A) A$ _ Q
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
9 e w) `: _- `
((SOURCE) == RCC_RTCCLKSource_LSI) || \, E1 l7 z3 t# u' R0 i/ `
((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \- ~9 d1 ~# A$ a' _) M
((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
) T3 ?* l' M, {) e) Y3 \
((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
- I& I+ H% |5 D- k% j% s, R h
((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \8 V& t* N# e- g/ j4 q
((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
4 m- ?5 c0 O- t& X/ W
((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
0 ?: q7 `/ j) m8 p) @$ b- [
((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
e5 m3 q4 j5 s0 C
((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \/ }- R! g( r6 K
((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
# ~# H0 @0 f5 C4 v# w1 g8 o: j6 B
((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \- H% B! v# ]4 C: V
((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \; O. s( r' K6 U
((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
$ S: x& R, {( y+ q
((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \( q5 O. ^) g5 }9 E3 g
((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
- M1 d5 d9 [2 {
((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
$ e. `6 N0 \4 z- o: ~6 a9 E9 ]. A7 F
((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \2 X( O3 P" F) \3 ?
((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \. `' a7 Y$ K, ]& k: v" B8 m
((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \1 t4 q. u- L6 Z, w% g
((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
$ x7 B1 n" p' U) r! D
((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
, m. X6 `1 ?) _* A! U
((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \& x# v F3 K( p) B
((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \2 M' N4 ~5 P' K- O0 g* D- i; s
((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
- C/ K1 @6 E2 F+ B& C
((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
( b# h, f' \; g, q
((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \& I, c3 }" V% J, ~& V. I0 r
((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \4 v7 j- u, X" d
((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \" L+ C- W: b0 ~$ S W1 ^+ ?4 F
((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \7 |2 a- v( p/ V
((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
! E. M4 L) ~$ z3 M, F4 V

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RCC_SAI_BlockA_Clock_Source. u# \* U* {$ {! o3 F; U5 D

R' D4 P+ [# e* S; ~- m* P7 C
/** @defgroup RCC_SAI_BlockA_Clock_Source
* d2 }& A) j- t+ t7 n
* @{
*/
( ~' q2 j. a2 m- z6 r
#define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000)
7 k3 V: m1 w* X& g2 t1 a7 y
#define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000)
" U/ A5 M: l( v4 N) A/ |: e& i
#define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000)0 g6 O0 i0 v& b6 N: g7 c
z8 t a! A/ d! ?! A
#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\6 A- E5 z3 g1 E+ ^3 ?0 ?% H
((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\9 _( N% D5 Y O: m1 O/ o. v
((SOURCE) == RCC_SAIACLKSource_Ext))
, Z9 f6 f. A2 [7 q* `) v

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RCC_SAI_BlockB_Clock_Source

/** @defgroup RCC_SAI_BlockB_Clock_Source2 @& {, S& m) F; k6 t
* @{
9 x% l8 C% L" c/ u% q
*/3 M6 E7 ?0 r) M* S& A! ? M
#define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000)* u. z. ~, P( K2 _- H0 W
#define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000)
1 a+ } q: m* z
#define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000)
: E0 |- @& e% u$ W7 Q
/ A O5 r3 q. c; n' f
#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\
$ g2 Z/ t5 b: N9 f
((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\
5 s- Z6 e6 Z% M9 p
((SOURCE) == RCC_SAIBCLKSource_Ext))

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RCC_TIM_PRescaler_Selection

/** @defgroup RCC_TIM_PRescaler_Selection
0 Z9 R x2 e7 _1 Z- X
* @{7 l0 o; K. M- q: \% T+ E
*/& a5 }0 |0 j4 A" F
#define RCC_TIMPrescDesactivated ((uint8_t)0x00)' D5 |: r5 L' F1 Y- c0 q. b3 O
#define RCC_TIMPrescActivated ((uint8_t)0x01)
! D E+ s4 t. x% M; O# ~
5 V# U. @$ c; V V
#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) : O Y/ }1 A5 l' U' q
|| ((VALUE) == RCC_TIMPrescActivated))6 _0 y8 F* S x# y4 s7 C5 B

复制代码

5 s2 M/ w% F% i$ }. `1 N( V2 R
RCC_AHB1_Peripherals

/** @defgroup RCC_AHB1_Peripherals
6 Q3 ^/ ]& G& z" h
* @{" u3 I) O, h! k W; p: D* V
*/ " h- `7 |$ m, N* K
#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)
- S) c9 H. u; ~& O$ L5 `" ^
#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)# [& U& I# l' x: t+ ^( R; S( _
#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)0 W7 I" z0 W" N m
#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)% m j! r. E2 S, @$ @
#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)4 P4 E3 u2 e* ^
#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)3 x1 S2 L: t, g/ n
#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
; o7 j: u/ c5 x
#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080), Q% @8 x( T+ r' i. I$ W
#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
1 U1 Z- X, i: u3 \6 D' q" |) F: ~
#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200)
4 z$ k1 `" o7 O: g4 ~
#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400)
. }9 _# e' k6 d+ R
#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
0 e& R j u3 j
#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
# ^: Q) i2 E# i( p Q
#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
; r3 l& b5 O- m* d
#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)* ^; `4 r& Q- n% }
#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
' f5 v" M$ H" h/ H4 N) ^' a( v
#define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000)( {4 O! G$ Y, Z
#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)! s _8 f$ c% {- D2 _- V. `# l
#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) L7 f( Q: l. f J# p
#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)9 Q+ O4 d. ]& B" W i+ O6 E
#define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000)
* y. n/ d% u7 _% F6 K
#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
% P2 Y9 { W. p+ N' y6 \6 o, ~+ |3 Q
#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)! D! O! J7 U/ L8 q; \& L9 s
#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
, D! l2 f u' z$ }( e7 @* }
#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
! Z7 q8 R5 p) t4 O
#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000): j+ V/ _5 B, @
#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
* G) r' b, [+ u8 D8 q
* D( y3 k D" }9 U2 _% ~8 B9 ^
#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH)
+ h0 ~- I+ `5 V; n
((((PERIPH) & 0x010BE800) == 0x00) && ((PERIPH) != 0x00))
& p0 k& X" P( L2 ]5 S! }" X
#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) * m$ [' ]" [" N8 Q1 @2 p
((((PERIPH) & 0x51FE800) == 0x00) && ((PERIPH) != 0x00))0 [ |! \/ M& A( ?' i7 U
#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) $ j: Y1 p- {0 h( e; e2 R, u
((((PERIPH) & 0x01106800) == 0x00) && ((PERIPH) != 0x00))
$ v+ U, C( h3 Q. P* ?: Q

复制代码

RCC_AHB2_Peripherals

/** @defgroup RCC_AHB2_Peripherals % k- h, I+ h/ x- B( w& x& D. P, m
* @{
0 a, P* u* @2 x
*/ ' T5 X. I* v& i5 M4 f( V. q
#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
: A6 ?5 L. g, c$ n' y
#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
+ m. Z* X( ]" K2 ^! ]: O! Y; [1 Z& i
#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
; P) d$ i2 r. r& i# @& A
#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)4 |! |3 A, m, [* L0 ~0 @
#define IS_RCC_AHB2_PERIPH(PERIPH)
' V7 L6 X* h% \5 z
((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))

复制代码

H, C. F$ X5 l8 P- w" }
RCC_APB1_Peripherals

/** @defgroup RCC_APB1_Peripherals
/ H, l9 v% J. \* D
* @{
; |( u8 e4 X# {! Y% e) s9 M
*/
! j6 c0 r" J6 v$ h, t1 @( t
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
& O% T2 E2 n4 M: n& m0 U: `" E
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)$ K* o a4 @% k
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)) J+ \! R% n/ N% @% d4 J3 a( E5 G5 ~
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)$ c5 @; _/ I G$ y( Q& n
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010): O- V/ b, u) }8 z [; `+ |
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
3 I! N; p2 P% S/ ]7 p4 y
#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)( D8 w8 d( `3 v, i
#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
! K+ ^; {! @# W5 i6 |( l# j0 e
#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
; ?- I' Y- i F) A- U4 N6 v/ z
#if defined(STM32F410xx) || defined(STM32F413_423xx)
' B5 z8 N( f( k) q3 W1 n; a& [4 Y
#define RCC_APB1Periph_LPTIM1 ((uint32_t)0x00000200); z" ^, n; Z0 p7 r. c
#endif /* STM32F410xx || STM32F413_423xx */
" |/ k' I5 E6 }, z u; n
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
3 `6 Z, F* a# o& K0 i" X2 V
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
0 B7 s7 p, g- F1 d) J6 p
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
7 |; Z P% K2 i$ e0 q) W
#if defined(STM32F446xx)+ |/ D* G2 g2 ?6 m$ @
#define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000). C$ o/ F+ `, [/ R# i
#endif /* STM32F446xx */ * ]* d \* f% @2 D" r f& k
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000). p2 `! U' K2 b4 F
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)1 m) U- w z& b, P7 I
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)2 {7 }7 V e4 V3 P( G
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
9 s! M6 T+ D2 l3 Z! I! g
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
, z1 t, T; n# T' |
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
2 E$ y" K* {: Z
#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)3 d# P, A) N1 X. f3 z. Z0 O. Y3 p
#if defined(STM32F410xx) || defined(STM32F412xG) & Z" ]' }8 \' c5 q) d7 G
|| defined(STM32F413_423xx) || defined(STM32F446xx)1 |6 e& i8 u) S/ U, S
#define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000)
0 v" C1 p9 s2 U% E' k1 Z7 F" y" x
#endif /* STM32F410xx || STM32F446xx || STM32F413_423xx*/ + V3 V; i* o+ p+ T$ I4 T. E4 ]* ]
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
3 J9 x6 R: s( I4 t: B! y4 |4 J0 e, H
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
+ z$ s: [; C8 c' V, E" B
#if defined(STM32F413_423xx)8 v' W8 D0 l. u& ]; e6 G$ j/ e' A
#define RCC_APB1Periph_CAN3 ((uint32_t)0x08000000)+ E2 X7 m( {5 O% Q# s& t& j6 q& W
#endif /* STM32F413_423xx */
3 G8 ?: [$ `6 G( L# [! K( f
#if defined(STM32F446xx)
/ H8 ?. _2 S, t S) Z1 B
#define RCC_APB1Periph_CEC ((uint32_t)0x08000000)) F8 _" u0 {0 j( @6 p& }3 P. O
#endif /* STM32F446xx */
5 _8 ^4 N" K0 H+ T
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000): Y0 ? V: y( E1 X D
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)9 E+ I8 Z0 R- H- f
#define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)3 f5 q2 L8 ]6 r& ?' y* k
#define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)2 L# c! w7 `/ w
#define IS_RCC_APB1_PERIPH(PERIPH)
8 R1 @; A# k. V/ \2 |
((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00))4 k1 z" x4 u6 c0 a0 t% _

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RCC_APB2_Peripherals

/** @defgroup RCC_APB2_Peripherals - Q' H, I- ]: p" I A6 x, p* m
* @{) B) h: b7 J/ ]; P8 r" s7 q
*/ 4 N4 h8 G+ i0 Z4 o% l: X3 N$ q
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)- x7 t' `2 v9 L4 o% O2 d: h. ~# X! M
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)# e! p: l" h5 p( W3 s* s0 Y
#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
# E. D D& \4 E3 V; B* x
#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)
" \ o3 s; K A* [# A
#define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
7 Q7 H) f6 x; \* R
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)* w/ R6 q# e' q/ n/ [
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)( x# l4 j" p9 V- T
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
0 h# G4 u2 s$ d1 n. s
#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)9 M+ k9 K5 k' ^! \- Z- e
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
0 j( x; v) k, E- H7 ~/ E% g( m
#define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000)
5 ^/ \& `4 o3 b0 ^6 ]
#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)% R6 x2 `. l' E# c% ]; @6 W
#define RCC_APB2Periph_EXTIT ((uint32_t)0x00008000)
6 V6 Z. a& u7 L! ~8 E
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000); l9 \* Y( p: u- F+ N0 C5 A( X
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
# C9 n& v% N! |% r+ }
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
$ \5 E7 \6 J. a: a: U6 W
#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)1 V8 a1 b. M7 \ ]( m& N
#define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000)
+ x8 {* U- F. d8 n$ S
#define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000)3 ]: i$ _: q2 Q. z4 m
#if defined(STM32F446xx) || defined(STM32F469_479xx)1 } b* Q: L0 t3 f
#define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000)( }" E1 }1 Z! f Z( e
#endif /* STM32F446xx || STM32F469_479xx */
& r7 Z7 @/ B3 g. t# L+ G
#define RCC_APB2Periph_LTDC ((uint32_t)0x04000000)
* p; ~. f h4 U* K0 {: w
#if defined(STM32F469_479xx)
2 X, i+ ^; j8 g; r0 D7 G3 f
#define RCC_APB2Periph_DSI ((uint32_t)0x08000000)) G2 G: v+ A/ S
#endif /* STM32F469_479xx */. ~8 x: p: K/ ]6 Z
#if defined(STM32F412xG) || defined(STM32F413_423xx)
" V/ O1 A# J9 J% M0 p6 w- k2 e* {
#define RCC_APB2Periph_DFSDM1 ((uint32_t)0x01000000)
* ^4 [/ X) K- f. ^
#endif /* STM32F412xG || STM32F413_423xx */# b8 V# E9 _+ u# S& W. p
#if defined(STM32F413_423xx)) `% S5 k1 G: X7 ]
#define RCC_APB2Periph_DFSDM2 ((uint32_t)0x02000000)
9 |, m& M) X) }* J {
#define RCC_APB2Periph_UART9 ((uint32_t)0x02000040)) t) F' r* ?6 J! c& T
#define RCC_APB2Periph_UART10 ((uint32_t)0x00000080)
7 R" J- x# P; L# V. F" [0 u
#endif /* STM32F413_423xx */
6 t! m7 m( |5 a9 j) T
/ ]1 ^" r9 a: Q
/* Legacy Defines */+ e7 T" c- S; o+ D$ [# K: ^3 t
#define RCC_APB2Periph_DFSDM RCC_APB2Periph_DFSDM1
) e$ x1 J$ f( `7 b& k5 m: Y% c1 D
5 p* ]& n. k9 F J* q( t' ?" @
#define IS_RCC_APB2_PERIPH(PERIPH)
5 p: l% u/ g+ e8 [7 ?" H6 I
((((PERIPH) & 0xF008000C) == 0x00) && ((PERIPH) != 0x00))
" W6 c7 z& S9 x' b7 T$ B+ d5 V. W% n
#define IS_RCC_APB2_RESET_PERIPH(PERIPH) - V( k! T% c- U$ z9 ~
((((PERIPH) & 0xF208860C) == 0x00) && ((PERIPH) != 0x00))

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RCC_MCO1_Clock_Source_Prescaler

/** @defgroup RCC_MCO1_Clock_Source_Prescaler8 j1 f" b" _4 Z3 l8 z
* @{
0 m! C8 C5 }5 l, j4 j
*/
, q9 x0 @) d$ x% V( Z7 D$ a
#define RCC_MCO1Source_HSI ((uint32_t)0x00000000)
! g1 `7 q# x4 B) o
#define RCC_MCO1Source_LSE ((uint32_t)0x00200000)
6 s% w6 z6 u$ k6 r6 }
#define RCC_MCO1Source_HSE ((uint32_t)0x00400000)
3 r$ {) H* X: X. V, b
#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
$ K' u9 Q _. b# ? c( ^
#define RCC_MCO1Div_1 ((uint32_t)0x00000000), T( ~4 I, p# {1 i! h. ^8 x7 Z+ I
#define RCC_MCO1Div_2 ((uint32_t)0x04000000)
) s) n, A1 |" N6 [
#define RCC_MCO1Div_3 ((uint32_t)0x05000000)% J* x0 B: f9 |7 E; o
#define RCC_MCO1Div_4 ((uint32_t)0x06000000)9 c8 x% d1 P6 C: G
#define RCC_MCO1Div_5 ((uint32_t)0x07000000). P4 f8 S. k# {, x+ p
#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI)
7 m/ D+ d4 D1 K3 G
|| ((SOURCE) == RCC_MCO1Source_LSE) || \& Y' R1 Y6 H. Z4 h; ~& t$ y. k
((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
8 J. S- w6 T4 @
+ P+ Z5 S) F+ U! x- D; w. H0 W
#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \- d. e9 b5 u7 ?& r& _
((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
& H/ K" ` _& h/ x7 {
((DIV) == RCC_MCO1Div_5))

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RCC_MCO2_Clock_Source_Prescaler

/** @defgroup RCC_MCO2_Clock_Source_Prescaler
& S2 m' h" p0 f" b7 M1 U
* @{
4 H( i- o2 O1 N( t
*/
) f+ _( N0 a) u& x M% k0 k9 D9 s
#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
$ Q. ?% z8 S2 o3 ^" w. V4 n
#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)9 X! I- c+ v% B( O5 ^
#define RCC_MCO2Source_HSE ((uint32_t)0x80000000)
( |& Q, ~7 [/ t+ k* p, x+ i& ^& m: d
#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)2 U8 H, O. o$ u; Q
#define RCC_MCO2Div_1 ((uint32_t)0x00000000)
! _1 ?& ]6 m6 ` V, T( T8 q" R
#define RCC_MCO2Div_2 ((uint32_t)0x20000000)
% x9 @* X! Q6 ?
#define RCC_MCO2Div_3 ((uint32_t)0x28000000), H( k" T" q5 ]6 a
#define RCC_MCO2Div_4 ((uint32_t)0x30000000)4 |6 R: N( P0 b2 A0 u1 B; G& z
#define RCC_MCO2Div_5 ((uint32_t)0x38000000)7 y, f$ B9 J3 o3 B
#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK)
1 U h" C- ?! F# h) K7 ^
|| ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
9 w4 S9 c$ L- e8 `; H' b
((SOURCE) == RCC_MCO2Source_HSE) , f0 o8 ^6 V2 e# S* g
|| ((SOURCE) == RCC_MCO2Source_PLLCLK))5 \7 z$ U' r; L3 @* u, w
$ N3 p C9 e; i$ T- Q$ b
#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
& v: `5 ?3 \% l/ v0 T4 B8 y; K
((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
7 @5 Z2 L" i, u% e
((DIV) == RCC_MCO2Div_5)) 9 H% [. H. r9 z5 a

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RCC_Flag

/** @defgroup RCC_Flag 6 w6 M) M0 `9 b5 n' ^, c+ q
* @{* c5 S; \8 _9 q1 s, `/ A5 ^0 q& l* x
*/) u& G# i s/ G' j- b4 c
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)' k' \: I9 s2 u, D. P- b Y: a% v
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
! R# e" n; `2 P ^3 X! i& s- t2 P
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
- r, B9 {" d: G/ h
#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)2 s: w) G$ t4 m2 P
#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D)0 l! \" }, P' f0 U( \9 X: r: }4 ^9 \
#define RCC_FLAG_LSERDY ((uint8_t)0x41)% P& N; U8 a% c1 k
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
+ `$ {! w$ [% \! t4 ^
#define RCC_FLAG_BORRST ((uint8_t)0x79)
' S0 C, U3 [- \* C7 t
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
4 N' u: m: g. a6 {
#define RCC_FLAG_PORRST ((uint8_t)0x7B)9 K7 O/ p" m( _# p) @
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
2 N) {& }( H! V. Y8 ?% p
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
, W+ m! h ^1 V* R
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E); e5 w8 J2 V$ k
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)7 r: g2 J5 q, f7 p
% R% N, g/ U3 P0 N
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \& F J& i6 w# K- c9 [, q( z- p8 @
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
$ v3 u) R9 Y& I4 u
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
1 M' e2 J6 A$ l" c' a" E% e
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
2 f6 q8 X( c* J1 X$ f: o5 K' M6 T( n
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \% I' W) i$ _1 ?. n5 P
((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \
8 ~ U' f# S2 P& ~: R! _( S
((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
: C/ U. h$ ~% h6 Q5 d
* l# i( u7 ?: N, W1 ~
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)

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: P$ ~1 F8 V8 _* t% r1 I
03. 相关函数

/* Function used to set the RCC clock configuration to the default reset state */7 v+ a- D" n8 i5 ~* d6 `$ f
void RCC_DeInit(void);7 C6 D! G% W& F6 T3 Q& o
# v ^& h3 n2 U% I3 i, H
/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
9 W- }3 {8 y) h
void RCC_HSEConfig(uint8_t RCC_HSE);# I0 E2 e- L- u% D
ErrorStatus RCC_WaitForHSEStartUp(void);0 w1 Z+ @* ?( f: u
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);0 D5 s1 [1 q- h7 Y
void RCC_HSICmd(FunctionalState NewState);- G1 H6 [& l: I7 @: P
void RCC_LSEConfig(uint8_t RCC_LSE);
u) U# q. d) S" c
void RCC_LSICmd(FunctionalState NewState);4 \& m; s; _1 M+ s
|3 x" P1 L: d% T; D" I. y* I
void RCC_PLLCmd(FunctionalState NewState);0 k/ L: C1 B/ T+ N" B8 o
$ _6 ^0 b6 {( Q1 ^% D3 A
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN,
) t2 y) D7 a4 w
uint32_t PLLP, uint32_t PLLQ);" _3 \" c. `- u; o3 H
. l) x6 h! s0 e% X" g
void RCC_PLLI2SCmd(FunctionalState NewState);8 X" }2 n" ~( L+ c! N( `
* X& z5 @! h2 d% j
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); m- E0 `. [" N. L2 ]
* N$ P; ^) R+ b( l% J5 F
+ H& Y* r6 f2 j! ^4 r% D
void RCC_PLLSAICmd(FunctionalState NewState);7 P1 _7 j+ W9 i: a6 u# R5 f
$ K& @) A/ l6 `' Y
void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);5 |5 Z- }2 F+ |" _, Z
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
' B- ^& T7 Q0 Z6 U
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);, h; o6 \+ l8 ^1 {$ c9 ?
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
/ N" N2 o5 @/ t# @
, Y7 j; R1 {' j3 ?8 t9 c& t- b. K( s
' A: x6 V8 P9 t
/* System, AHB and APB busses clocks configuration functions ******************/
$ x! n" K: M* i: K
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);. b% \7 J/ ^1 B8 a/ T
uint8_t RCC_GetSYSCLKSource(void);
6 h5 ^: C# ]# |5 z/ o! }* [
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);7 t4 a6 B9 ?! E9 u8 q" h3 {
void RCC_PCLK1Config(uint32_t RCC_HCLK);& ]: l& j/ o6 I, i( Z# b
void RCC_PCLK2Config(uint32_t RCC_HCLK);
7 b' O, F* v$ R
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);) }5 H8 L/ V4 M# A( R% g7 e
8 a9 p% b. H- a4 X8 K
/* Peripheral clocks configuration functions **********************************/
A$ i" Z, ]; G+ F( Y# C5 h" d
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);8 V5 k% c7 I8 K6 @
void RCC_RTCCLKCmd(FunctionalState NewState);
+ l+ I. Q! e+ t+ \3 E0 S- v* b
void RCC_BackupResetCmd(FunctionalState NewState);
5 n: E- e* F) X
8 Q2 g7 X+ ?4 S# @6 j" y& o
7 S$ i4 C0 m) Z: `. R
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
: Y3 x9 q5 T4 }
7 K. \; g2 o* ^/ G
% L( s& l4 X- K0 T1 |) X- D
void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);; q0 O* C8 ~0 L( `. H% u3 \
void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);2 D! `: m% \- C! b2 i2 k
9 t, ~1 g! Y$ a) c Z
! G @' K& k' G' Q+ P
void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);- ?2 B2 J2 S% A; Q- W; n" x
void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);, R' `) h ^ i/ T: d8 r
/ p' G( H. C8 L5 u+ L
- O* \( d1 z; U
void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);. i2 o/ K5 F" i' e+ u5 V
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);6 U! }. S4 _, h3 Y9 r4 s& y0 ]
; J" t% s/ J; |9 {/ r; U
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
; A$ l0 R8 p! ~0 P* Y
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);- S4 U* X0 o& L" g/ m- U
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
+ K) n. H% s9 T b
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);6 G9 U) ]6 M2 K( I# ]; e7 r
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
8 e3 Y& Q& O. t* L) X" q
8 T3 w4 b7 j, P7 ]' E8 a+ z
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
2 J$ H& f5 ?' s7 G, q) ^7 u3 F: f1 G
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
* y1 X+ y+ q( S! Y& X
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
, w. g- i* l" [; {3 h- v
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
5 S4 Y# C8 C7 Y" P) ~
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
: \6 j0 D8 Y) ?9 G
' z1 _. {' x4 J) [' s# v' n' O1 x
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
9 \$ {, {3 c5 ?6 D3 k( d
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
& I/ ~% y$ Z2 [6 ]- b
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);" F" z9 J; \$ d z5 Y' {
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
* S" L# p* k& y) E0 o7 }
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);) z# }9 {" J. T9 u5 E
/ |0 L& d1 w- T n0 q' `
3 P6 Z" o, I" \7 m: G" B1 ^3 `
/* Interrupts and flags management functions **********************************/
2 x' r# M- b8 T3 H% I2 B
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
: u2 D x+ S, j0 a6 n
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
, m- N$ z! b* u4 d: A* u
void RCC_ClearFlag(void);7 {) M" }, @! r( W {( H
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
* m$ j0 S1 L. I9 {* Z
void RCC_ClearITPendingBit(uint8_t RCC_IT);
2 O, |3 m/ Z2 k/ `9 s

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04. 结构体封装

/**
$ c4 i- _5 L+ \4 h
* @brief Reset and Clock Control
* S6 J5 i1 o Q
*/
+ }8 T' e+ A1 _# B
3 k! e ?; {9 A: a
typedef struct
$ \0 e: F! @8 I, g8 y
{
z# F# ~ u3 @9 Q* z8 S
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
1 W. X: s0 r+ g+ K* ^
__IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */' K6 j/ m4 W* L9 b% F- f
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
6 p; y; C: ~/ {$ c$ m" A
__IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */$ R; y" _( m/ P G7 w2 v9 f
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
, L: P ^" T* ]0 x
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */8 \0 }2 |" @0 E- X; {4 `. P! h) D% X
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */9 l4 E8 \! E; S b- ?. a
uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ M/ x: g( G1 O2 c' ]+ D
__IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */5 v8 B" A% t: Q+ ]# z+ o! y: X2 P
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
, {1 D9 l; f4 O/ L+ ]0 D
uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */. ]+ t4 q1 L4 w
__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */" g) B5 [( R! J0 A
__IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */2 R: e3 X2 Z( n8 M+ u0 C: F% @ B! w- A
__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
3 p% ?/ O9 {# n5 J
uint32_t RESERVED2; /*!< Reserved, 0x3C */
* \& z3 g. \4 o9 b. N+ q
__IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
7 i; M( x) d: ~' s$ _# `2 z- g% N' b
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */8 z' i6 b7 Q. X' ^# ^
uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */: T" r- k: \4 S) N! n+ s5 C/ r) G1 n
__IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */% m/ t2 p) a/ |1 u' ]
__IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
$ j/ m" h* B3 ^# A+ m% G5 `
__IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */' U1 F/ c4 g% h+ z- F! h( `
uint32_t RESERVED4; /*!< Reserved, 0x5C */7 _3 S; g4 H7 f; l# ^/ @' d
__IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */: w9 A1 { p; M9 U
__IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
* R5 g' ^( ]3 [6 D: T+ z
uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */8 h. a1 k( ^8 J- k* [3 W
__IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
1 ]5 P; f0 |8 B7 t* E2 t
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
" \5 x8 _; d) @5 l
uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */% A$ Z, B9 W' e1 d( G
__IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */2 c9 V5 A. k4 d- X4 b" M6 Q6 S7 y
__IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
! R/ s) V' u @- L" G: g$ v7 D! K
__IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
$ n9 P6 h" C/ _* L, D9 {" @' F
__IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */8 B2 r+ S* ?& M( x9 a8 F& R
__IO uint32_t CKGATENR; /*!< RCC Clocks Gated Enable Register, Address offset: 0x90 */ /* Only for STM32F412xG, STM32413_423xx and STM32F446xx devices */
) S5 Y( z9 t# U! I9 ^+ V
__IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */ /* Only for STM32F410xx, STM32F412xG, STM32413_423xx and STM32F446xx devices */: f* [: [' a% k) P
* x% e3 H( b5 y, B" z+ S: T
} RCC_TypeDef;
1 O, [0 P" M `& c/ A9 B

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05. 其它

/******************************************************************************/
! D/ i/ o# A/ \! X( A& I
/* */
' K; D; ^, L3 c- q3 l! d
/* Reset and Clock Control */
+ i8 `7 I* N. N) `8 O) {
/* */% {9 T) ~6 T( D* N" }2 `& Y" A; b
/******************************************************************************/+ `9 o. G+ @# ~3 p' y7 N2 ^
/******************** Bit definition for RCC_CR register ********************/
2 D6 ?( ~4 l# j
#define RCC_CR_HSION ((uint32_t)0x00000001)
k# j& U7 H) g4 @
#define RCC_CR_HSIRDY ((uint32_t)0x00000002)/ d: F4 Z. r% Y
4 r [1 e) W e* f) a' a. f$ ]
#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
7 E( C4 u7 R* Z, _
#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
i/ I1 R& W7 P6 h, W
#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
6 t/ F% ^. g6 ~; L
#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */8 b; Z" l5 [' m/ S3 a! K, e- \
#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
, }- B& g. o+ a. g" z
#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
2 j7 O9 u0 b, `9 l) v! P5 v% ~
/ ?0 C$ ?1 W" W+ Z$ v% \7 p/ k" ^
#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
+ A2 E& Y) @+ Q/ f a4 ~
#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
* q. i. @' K l
#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */& p j! q s7 \: A7 |; f+ }
#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */ W9 ^- o3 W' \/ K. U
#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */0 R) C: F; _2 O% N; ?
#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
N) ]# v* g2 J( ?: n
#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
/ B% A. c( X& x" d7 h2 W2 Q$ g4 u
#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
3 I" c( s3 W$ H$ B
#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */. N' G$ L. `4 ^- @$ q! o, h
$ K7 }6 v s( Q' `
#define RCC_CR_HSEON ((uint32_t)0x00010000)
3 Y# z# [* `/ {% k9 c# ^
#define RCC_CR_HSERDY ((uint32_t)0x00020000)' R; J# [, d3 Z) B0 V0 b
#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
6 f9 z: W3 H: r; M
#define RCC_CR_CSSON ((uint32_t)0x00080000)
) K. g5 D$ t+ \6 M3 S8 `
#define RCC_CR_PLLON ((uint32_t)0x01000000)
* g" a5 S/ d; O* d: i8 F+ {
#define RCC_CR_PLLRDY ((uint32_t)0x02000000)4 T. V. b1 P& }9 [% D) U. G# e4 f) u
#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)( m; h) c. @; j! E6 }& Z) F; @
#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
4 Z0 G! W$ d6 B
#define RCC_CR_PLLSAION ((uint32_t)0x10000000)
( [ {- w% q, t5 U) B) U
#define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
) E0 y0 [) V4 c: ~- U" y7 o
2 L+ L' L, P" z4 [/ A
/******************** Bit definition for RCC_PLLCFGR register ***************/
3 W3 T0 i! l; r* M" N* V+ o
#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
- t$ o/ p! C/ l6 k
#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)/ c' S' p& G4 v( ~
#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)4 t4 H$ A% E- X) c/ B
#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
; e+ j: Y' X5 f' t, z& O* R: x
#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)7 }) r! \/ v- h3 r& w
#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
; ~' k5 W: {: N0 m) @# i
#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
6 n; K; p$ d G* z( F% a
1 S$ T5 Y; C: v) ?; | [
#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
- M: O0 N ^+ M R
#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
6 A% `3 j: l8 i; O
#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
p) s' ^. N) n" s
#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)# q; \4 |7 S# Q! v
#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)% {( B( ^ s( U: x. ^" W
#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
" X+ `/ Y2 k; E9 I) @2 j6 n r
#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
- v6 x/ l# m; ~7 m; ]8 w L. @
#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000); x2 Q- z& Y. f- D9 \/ [; [* [4 K
#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
+ |9 A8 L2 [3 ]* i$ o
#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
( J, L# o- b0 L, a
3 j) j7 S! ~& z/ s
#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)! m2 h/ ^9 b8 O v& ~$ V
#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)9 e' X9 G" G9 \; I! X V
#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)( u {3 ^: d* c9 |7 G& Y! z
# O# s9 m2 p# I9 w$ H J
#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
& E, B3 B8 Y# _! Q
#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
4 W" G) _( w; M" s
#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)3 L. d1 s7 ?% d- _, W* V/ o+ E3 P
g& v$ O- j3 w# M- n5 Q: v) f
#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
; a0 E- m; m' L# ]
#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)6 L" t9 i: X: ~5 s
#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
( S0 h5 N! T# e: @
#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)9 \3 [, M& [3 y! t q3 E H
#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)3 I& i, y- p. v$ h
' n+ R a* [8 B' ]: Y) }3 |4 c u
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
/ _" R$ f5 Z# J3 I- r; a4 }0 C; F7 x
#define RCC_PLLCFGR_PLLR ((uint32_t)0x70000000)
; n6 l% r W9 C( X; f6 l
#define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x10000000)
: J! g) R; [; d6 Z+ B
#define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x20000000)4 K* c, m7 f5 c- T" M4 d
#define RCC_PLLCFGR_PLLR_2 ((uint32_t)0x40000000)/ T0 o( ]% Z6 J8 K8 x: m, [/ e
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
" x6 S) D9 J6 e* U( F3 y
, \3 L+ d. G% H/ Y/ H; D
/******************** Bit definition for RCC_CFGR register ******************/4 ?! h# G* h1 t! U* @5 m" x
/*!< SW configuration */
* c* \4 v$ ?% X2 v3 T. `5 q% ]! G
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */, p- d% Z$ d, G# U1 T4 q
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
: b! _: H; o8 t) G0 L0 E! x
#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */# z( X! R' W( t" Z$ D9 @7 ?
7 v: {9 q4 |# b8 n0 J
#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */& P) b& B7 u/ r2 R
#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */" V4 @* {- F1 Y$ \" e
#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL/PLLP selected as system clock */
& [* f+ D: b! c6 ]
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
9 ~: q6 J- Q, ^# D4 o
#define RCC_CFGR_SW_PLLR ((uint32_t)0x00000003) /*!< PLL/PLLR selected as system clock */
5 U% `. q u- P' s& e q
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
4 K' F; B7 S2 A! J. n
' E, F% q+ l) H& F8 L
/*!< SWS configuration */
# M! }# n; w- g' K- z. @2 k6 X
#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */5 l v( b4 i, Q0 c2 R
#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
9 _. z+ q2 k4 i* s+ Z) W, N
#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */! X* s( m! f8 r3 v4 D `
9 S2 c- ^& N2 [
#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
/ i- e4 Q& r& c# G
#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
* d k# ]6 b! v% x2 C# h
#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL/PLLP used as system clock */
, d! x4 ? n& J4 |9 e* H; E, @
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F469_479xx) || defined(STM32F446xx)8 j9 a" q) [) Q
#define RCC_CFGR_SWS_PLLR ((uint32_t)0x0000000C) /*!< PLL/PLLR used as system clock */
# v& ^& g! m8 i' z l' I& p
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
# G) Q! E' g% n. K3 S5 u! G* m' G
( [3 K% @, @% k
/*!< HPRE configuration */8 x7 K# m- m3 P9 a- T
#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */+ z+ P. W4 r1 |, g" g7 u& @0 C* c
#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
B8 j6 B8 u9 p
#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */3 z- V% o" M. D, K1 ?
#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */* }. `0 z7 f" l8 H
#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */: G9 D' d7 X: [/ P
" f* @4 _- S M! B3 B8 }; t8 m
#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
$ w! _& [) }' v% @' b
#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */' k* S! k+ o+ _- g
#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
) S1 C/ K t: N# S
#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */7 x; j0 w/ h, w2 c) J3 u& s, n
#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */$ a+ ^2 U! k& H9 w/ _
#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
$ Q& F/ |5 ?1 k8 O9 U- f: m
#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */" e6 i% J5 Y1 S$ r5 o
#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */' t# n' K" |. h6 Z2 q1 K! z
#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */' G9 K6 d& y+ b6 c: y/ Y* E$ W( ^7 ?
- W9 ^! ]+ s, Y" C% p/ j& `
#if defined(STM32F410xx)
0 ]; d( A, l1 o* ]8 r
/*!< MCO1EN configuration */
1 x+ B) F5 B# w
#define RCC_CFGR_MCO1EN ((uint32_t)0x00000100) /*!< MCO1EN bit */
# s3 v. Z6 {* ^3 h; s" K. p
/*!< MCO1EN configuration */, ^% e& b# V" X: R4 q, @
#define RCC_CFGR_MCO2EN ((uint32_t)0x00000200) /*!< MCO2EN bit */
! `4 I5 h: n3 T5 m$ P
#endif /* STM32F410xx */, j9 H$ _5 _7 D7 Y2 `( _5 q4 L7 g
/*!< PPRE1 configuration */
# n9 X8 U6 S5 E! R; W! x7 y
#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
- v4 B* @; u" _& K7 j( K' ^8 t
#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
' }% }. O' J* H$ F! R
#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */9 [6 x4 _* c+ r1 G
#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */4 y- O N) l8 W; W2 Z1 R; S3 q: f
' S$ W& B" ?6 J2 ]9 V9 q
#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */. I: N; ]7 |! x* X/ [# U7 v
#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
+ b# S4 Z/ J4 ?, u2 C A) P
#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */) }! f3 l0 h, j' S) A4 z
#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */% h, ^5 [8 m) V) y; P: p
#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */7 |& Z0 W) p3 q$ n/ N
7 `6 r; s1 b! u: W" P. l$ {# \
/*!< PPRE2 configuration */
7 Q9 D' M3 l6 w
#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
$ y/ h# R# |( [/ u, P& m
#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */7 M" `0 e, Q( f6 {
#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */# L& X; v3 L- k" x$ j4 S) p
#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
8 H g! W( A! X
2 {3 K3 j, n! V4 y6 Q6 C
#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
1 p% A, J2 j( R& y$ N/ j
#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
7 t8 B( G2 s; Q' m) a/ x2 T3 b) ]5 Z
#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */# t+ b# i0 x# O, @
#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
! N* R4 H9 T, @0 N; Y t i
#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */, O4 h& \. Z9 P) d0 K7 l. X' [7 A* y
+ b# T# N; W a! F/ A d
/*!< RTCPRE configuration */! ^1 U0 `- e. u- @ c9 W3 a
#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
1 Z/ G9 k9 g6 U7 s% M
#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
1 F; _7 j* B$ ^8 K- U7 F0 j+ l
#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
( X0 }# J& i% G
#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)% }! D$ b! [8 p0 |+ J3 T: J
#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)1 D( ]% E; k! u7 M% a+ K
#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000), P: n, R8 n5 S9 p
% J( f4 S" g' f! @1 R
/*!< MCO1 configuration */
: E e# C% |1 ~* L! ^3 t
#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)- }8 {- v& E! f+ i. q. }' H1 x7 s
#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)$ a& ?; A: I. f* a2 k5 \+ [
#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000) y! p% S% Z7 O3 h
2 X0 u7 a q9 J
#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
0 K7 _' s. h ^: ^" e0 X; R1 f
/ Q) E r* g2 Z1 k' j
#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)& ~1 ~% ]1 Y9 V" z3 V2 Y
#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
8 G2 r! E$ n) K# _3 O9 h: l: V
#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000), w6 {% O" c G$ a. @( E
#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
' S. {$ z) Q. W; c
0 C8 Z7 a+ J, j* m" |- J' v2 d9 b
#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
( K5 m {7 H4 B
#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)$ J0 W& \7 U0 H1 q6 |& t6 e& J0 V
#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
. m! d7 x2 K, ~. u
#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)8 }: _* Q7 O% o$ o7 m+ Y* _
! b. D& `/ f2 d8 B2 m* s) r
#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)# G8 t& k% D' \8 P* a
#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)0 O1 X8 [9 J( n. q+ D
#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000) V/ j) j7 g0 K# S) R
7 b+ d) h, q, k; s& o0 Z
/******************** Bit definition for RCC_CIR register *******************/
( ~3 V- L S7 ^# N
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
1 A/ L5 I, m' {4 [5 L9 Q3 Z$ P8 w) N
#define RCC_CIR_LSERDYF ((uint32_t)0x00000002), W4 g2 k9 N d$ ]* f, f G
#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
8 O; ~- ]' ~# b+ p& F B
#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)8 x0 _* l. P. {7 n$ v& l9 q/ W
#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
1 v/ `. A% Z- N. B- v: N3 i1 N
#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
; l( I j: \. ` { k0 D) k
#define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
Y4 M z2 P9 z R. c) b/ l
#define RCC_CIR_CSSF ((uint32_t)0x00000080)
#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
, B( O# D1 Z8 {! @8 I: l. h
#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
& i, ?+ F& o% k
#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)3 ~% P0 v/ }- t: I+ d7 W
#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)% }" ]2 N" A4 v
#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)- I8 W3 E7 S' h, ?: b
#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
! m2 ?0 l7 P' v1 o: C. E1 \
#define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
, \5 I9 R( I. S# ^, _4 O- n
#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)$ l! D; ~: q; f P+ r
#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
7 s2 T6 `3 J3 u- Y6 Y) [) @
#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
4 b( l& K3 d/ ~
#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
5 G9 r4 Q0 L, P3 ~9 c" ^
#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)5 g3 B* ^9 j5 g) u$ k
#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)0 m. [( d" R- L+ @* p% T2 q; \
#define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)2 L; V. ?$ d- y
#define RCC_CIR_CSSC ((uint32_t)0x00800000). _2 T" t) K0 v5 \/ Z9 b
3 X( ]' ^0 r3 R) h y' `
/******************** Bit definition for RCC_AHB1RSTR register **************/
1 j: A5 W- R) E6 ^4 O
#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
+ P8 \4 ]7 {6 z
#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
. E+ r/ {+ ~% R7 L+ L; m1 ]
#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
?% |+ m; t. c: o b" p1 l
#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
* h& P: P9 T: N* c
#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
" C3 A9 Y. }8 h6 R* ?
#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020), d" N4 H" b9 _% c6 ?! u
#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)! @, O* P# D% N& o
#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)' S4 l. ]4 J. _
#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
1 m, f9 o3 P5 P
#define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
; G$ z7 b0 t. z; q; E5 q1 v
#define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400); f3 D- ~5 e3 m, @+ C# A+ s# e2 n$ X
#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)# V0 @+ b3 m7 s. H
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)1 L, n; C; @1 W# a7 ~4 P
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)2 T$ M6 p0 n# u8 K6 H; n
#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
; {9 ^' ]; X4 F& k! O( x
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
# u+ l+ j, V, g( k, a' W& {8 R
#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)2 p; T; p) X' b. h; V
% O4 j" w* R8 [; V5 K
/******************** Bit definition for RCC_AHB2RSTR register **************/0 g9 d+ [/ _: ]+ \) r
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
6 a* N/ O4 ~( a& O9 m0 `
#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
. r1 ^% G# q8 g+ a
#define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)
9 C2 g' m! r" j0 }# u, R) p0 K" y
/* maintained for legacy purpose */# l7 s9 B+ O2 i" ^5 {7 _( A$ w
#define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
& n) h$ \$ O; o% m; {9 M- Z
#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)' i% A/ o4 d) Q" B5 L* l/ v
#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)" T9 q( H, @2 Z. m
6 ~: U& F5 o1 z3 C7 v6 n7 s* x1 D
/******************** Bit definition for RCC_AHB3RSTR register **************/3 D5 G& u# W4 F( R6 ^
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)/ Q) P I1 O) f0 w6 C
#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001); h+ g8 l9 H: `) y( [7 \/ m
#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */& Y6 G! u1 s# X' P: M: _! \
" y% L* Y9 q* G8 L
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)" F, y9 y% [2 K0 D5 x- ^' T
#define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
* s/ m* S$ v3 |* d
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
w5 J9 ~7 T# t" H4 v s, J
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)4 l; p, F5 n$ K [/ `/ R a! e
#define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)) z3 ?$ E" F0 a( s; k7 \# o" |
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */; C6 @. I, O( I" K
( N i4 \, w x( m4 m
/******************** Bit definition for RCC_APB1RSTR register **************/( v a8 Q) y9 ^! `' Z
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)" K* `$ G0 j1 Z3 @" S7 L
#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
1 |8 d. O' ?- e* ^! `
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
& n3 {" h9 b2 S* }( ?. ~
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)- Q3 D% ^' F. l: z) |3 I+ W
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)) `' O- D/ ~1 Q$ @' n% G3 k5 c' [0 {
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020); l$ |1 A: r! o0 w' a! h
#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
# B5 a/ E; i' m6 i7 k/ [9 Z
#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)3 B2 q% m @8 ^8 k6 ~2 e3 `( e( W
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
! N/ t6 H) j% f: s; _, e
#if defined(STM32F410xx) || defined(STM32F413_423xx)
) R% Z7 T, P$ T8 V4 Z$ ^8 ]4 E3 x
#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x00000200)
8 }, E/ n, G4 m) ]
#endif /* STM32F410xx || STM32F413_423xx */
% Q( ^) s! A2 N& D e: p/ H
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)* N$ L9 o: ~, I5 Q; v3 L: P" p2 W8 @
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)3 Q2 H% c+ j$ t! m$ h4 F1 K E6 `
#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)3 ]. t$ y D4 t' x. t# J
#if defined(STM32F446xx)! J" ^ T& h' Z. y1 S& F/ w# W
#define RCC_APB1RSTR_SPDIFRXRST ((uint32_t)0x00010000)
& t% {7 ~( g. {+ s4 N; H
#endif /* STM32F446xx */% z Z/ C/ X3 x, M5 e
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
0 H5 w4 N8 U8 y% |0 X
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)7 `8 V8 B8 J; b! d# C
#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)# ?+ J7 {( o- q. D. X; L$ |4 c% u
#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
; g- B3 ]( I( d! z4 {
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)! D8 t( j! _- s! `
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000). u+ {% {+ |2 I2 k" o6 n, k
#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)* n3 Q1 Z; L* D4 a6 o
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)' R5 H5 o# X0 D) b# y: I$ X. r
#define RCC_APB1RSTR_FMPI2C1RST ((uint32_t)0x01000000)
! b- r+ m/ e( T+ K
#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
' M* B6 U9 `; t9 L
#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)' J- Q1 ]/ M6 y8 b$ O+ Y6 `
#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
, u2 K V2 y. ]% O" X; r+ L* ^1 }
#if defined(STM32F446xx)
$ w9 U7 A3 R' G: [- D4 w e+ s$ c
#define RCC_APB1RSTR_CECRST ((uint32_t)0x08000000)# b. c$ `" |$ Q6 O' U) ^# R3 B
#endif /* STM32F446xx */
" |; C/ b: V- {; S: C
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
1 S2 J2 O% D/ C7 [, Y
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000), R* S& q5 {3 I) R. ]( g9 _
#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000), X7 l. u) G+ v$ G7 M5 V7 v7 b4 G$ r
#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000), z% i7 H, K0 ~% F6 X
1 s1 y- a2 s5 n; a, x9 O7 h7 |7 w
/******************** Bit definition for RCC_APB2RSTR register **************/) X6 X7 T. s+ Q+ i- S O
#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
8 i0 W) l9 x0 T ^5 `6 K
#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)+ a# {* P9 r* r$ c
#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
; g* ?$ H- D# B1 g3 O. m" z4 ~
#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020) I, `/ Y$ t: f/ ]+ k" K/ B3 [2 k
#define RCC_APB2RSTR_UART9RST ((uint32_t)0x00000040)# i! a& r# F+ a3 W' A2 @4 A; f
#define RCC_APB2RSTR_UART10RST ((uint32_t)0x00000080) S" W) p. P& `" ?! V3 f+ ]! Y% B( p$ B
#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)4 m! l2 A9 F' v% l# P3 U
#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
8 O+ }- S) p2 ^( e: G$ s# c
#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) s6 m6 e/ u% s) J2 } w# C
#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000); r- e2 ?# |( H" F3 Q
#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
/ A$ d$ y5 }# g/ f, d+ r
#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)0 A% p& X& l+ O- z' O
#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)$ }, [2 @# X9 s: f
#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
/ a" }9 D) V( p0 D7 N* z1 Q6 R
#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
- j3 q9 ^9 Q/ g, _$ _* }
#define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
, n% g, v' t: z f
#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
S, F$ D3 G y$ B7 e
#if defined(STM32F446xx)
6 F" `* Y9 C$ |) z
#define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00800000)5 d: k/ W/ W/ g H* K8 V
#endif /* STM32F446xx *// \) n; V; e8 L9 }! {
#define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
4 U% k8 B- u: l3 y
#if defined(STM32F469_479xx)( @# V! ]. r' d5 L T
#define RCC_APB2RSTR_DSIRST ((uint32_t)0x08000000)- Q6 K4 s% W. @) i; {
#endif /* STM32F469_479xx */4 K1 f. T/ X! Z9 L
#if defined(STM32F412xG) || defined(STM32F413_423xx)
5 c2 N9 y E1 R+ z3 r! D, D7 F$ [9 \
#define RCC_APB2RSTR_DFSDM1RST ((uint32_t)0x01000000)' Z$ D3 H: t7 T
#endif /* STM32F412xG || STM32F413_423xx */
5 O6 X1 f: G! _5 t( y
' o8 S% {; D S/ x
#if defined(STM32F413_423xx)
5 D: W1 P* @6 X: L
#define RCC_APB2RSTR_DFSDM2RST ((uint32_t)0x02000000)
6 Q6 F, e& X- Z9 Q6 x1 |
#endif /* STM32F413_423xx */% N! }, X' S# u
/* Old definitions, maintained for legacy purpose */; v& h+ ]- C+ ^) V ^. D6 N4 F* Q/ u
#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST R) R6 |8 ?- i- G& |: h$ F
#define RCC_APB2RSTR_DFSDMRST RCC_APB2RSTR_DFSDM1RST
7 H( w# a8 D) S8 g* z4 P
3 g+ b( B6 }% k, w1 B1 ]
/******************** Bit definition for RCC_AHB1ENR register ***************/
$ h5 r J# N% a0 A, `! d
#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
' [. X4 o% g' {: S2 {1 _( G
#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)3 C4 V7 f, q) Q1 n% R( l7 B+ O
#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
8 q1 X( J! r! m& N
#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008): ~7 B9 S$ t. \+ @
#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
0 x8 R$ Q. K( k, l7 h e% ?
#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
2 d! n: A1 Z( M$ P, j
#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)9 w% z4 g+ U$ V( {. k; h; d" h5 R
#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
7 E6 |- O8 {4 k6 f, E
#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
* C/ ~5 l5 x7 |8 u+ i: _
#define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)2 B, q8 r4 |9 T1 \3 M
#define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
. e; ~& N0 { f8 C" V
#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)2 D a4 t: @4 n
#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
" a& X, _# C) @6 O" I P
#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
( a o! x4 C6 a) D& A
#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
; E4 f2 M7 G4 {: S: W+ R% h
#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
, s! [+ ]4 I2 r) H% E8 B2 Q! f
#define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000) W+ A+ [$ K1 j$ T1 P
#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000) T; t! P6 x3 Y! g) M5 \8 P- b6 [
#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000). A' I/ [. L" H
#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)& J$ n9 L7 m( O5 O7 P% K$ C k
#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
, w8 Y0 z- e( V' }1 o- G' D4 p
#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000) u8 ~" o6 [& m7 F7 j8 @, q3 p
#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
" E, Z( i8 O8 M
1 x- H# h! Z: T2 V# J
/******************** Bit definition for RCC_AHB2ENR register ***************/
1 g: D: M3 l6 b+ ?1 S# x. E
#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
5 f2 J2 x2 m0 P3 j8 i
#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
9 y& x1 y/ \; R& z& Y+ D! p9 v5 y% Z
#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
$ V9 j. F( l Z5 o! \
#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
0 T- n G3 Y }, u6 g! M4 [
#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)5 j9 H2 Z F ?4 C z% h' b
( `2 C7 ] }* S- H5 x
/******************** Bit definition for RCC_AHB3ENR register ***************/ P8 ?+ `- w! {$ N1 A" C" Z, R
! @ H/ _0 `4 l8 N0 i( Q; t3 s
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
& J% G- Y9 x6 K
#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)) f8 _: c; L& z- M0 z
#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
+ n7 W$ ]. R2 o( K
) M- e- v4 {3 D
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
, T* O8 M6 \3 l( _# B8 `: ]" F6 ?
#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
$ N3 o3 L/ c9 i3 O: S# m8 Z1 t
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */' a% i2 a: |! z. W
" B0 j3 w3 ^2 e, P' K- k
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
- K9 b2 q0 I2 u4 T4 ? P4 I$ [ p
#define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)( L; f0 e; F y& G
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
3 I( C0 e4 |, s( C
+ h# p+ Y' T- u3 a; o1 i
/******************** Bit definition for RCC_APB1ENR register ***************/( u1 u V! y0 x: J+ F' P
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)& A9 d" J: }4 A: O
#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)9 Y7 `( A' l, T7 l; K4 }
#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)2 A- A+ Q ?5 ^* p4 l9 f: K( V, t
#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
) O c% ^1 a. W, E
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)+ Q9 d7 W+ l8 D/ g( I
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
3 n' @9 P! n# z
#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)- r4 S# c$ u9 S
#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
* V* ~% ?% B. |- a2 V+ F
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)& ^ c# q9 V; ]) I' ^% c6 z( s2 h. o
#if defined(STM32F410xx) || defined(STM32F413_423xx)2 i3 w2 E6 X* Y; R: F
#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x00000200)
9 U S5 e3 m# Z& T+ Z$ [' r
#endif /* STM32F410xx || STM32F413_423xx */
( J) E1 | U7 l% o0 ]( s5 A% h
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
0 ]1 V3 @. w5 ^; a C; V+ |
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)$ h$ T% g. s `% b6 G! v$ g
#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000): Q/ v3 r% v5 G6 E- T1 ^
#if defined(STM32F446xx)8 w7 ~$ ^" E6 i, \
#define RCC_APB1ENR_SPDIFRXEN ((uint32_t)0x00010000)5 V# Y# f* ]; P t7 n
#endif /* STM32F446xx */
0 e g1 @! y" l. w1 ~) t
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
9 P, |$ r" E% R4 H* W; q9 `! V
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)4 d8 a w0 m4 D
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
( N' q1 b2 b1 y f
#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
: y7 z) a4 A% I. B; s' V4 z) ~. m
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
$ u* t" Y8 h; i" x% l
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
8 H" R) G, P7 s% N+ e* n9 A; R
#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)) O( B! v0 V2 ^ G( _( {
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)6 g- y3 i1 ~! z& c/ q; P! s
#define RCC_APB1ENR_FMPI2C1EN ((uint32_t)0x01000000)
1 F6 o4 U" G& T9 ~% i* W
#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
1 |; I) C- B r* @
#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
7 A, |+ Q( `! ^7 ?
#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000); E$ p% d# e/ c% j
#if defined(STM32F446xx)
* a- n3 k! k: Q6 X* v! C
#define RCC_APB1ENR_CECEN ((uint32_t)0x08000000)8 b/ S+ Y: @2 J: @1 ^
#endif /* STM32F446xx */
7 q& U5 ?& m6 d) _$ @$ Y8 e) b
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
' O1 y/ x5 U. x0 z0 w
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)4 K w4 ^' @; a
#define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)8 Y" `! H4 b+ r3 u9 s
#define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)' T/ }& y) W& D Z: h
* I8 t/ Y! j6 R" l
/******************** Bit definition for RCC_APB2ENR register ***************/
: `! c( E) q0 m4 C& s
#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001): Q8 w1 F. B% Y, D) j: ]. N Y! i
#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
% K( |* ?9 U1 W( @; v9 z l
#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
4 t0 I3 v, j- C" g
#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
) @$ n" Q/ }4 @9 S2 x0 y
#define RCC_APB2ENR_UART9EN ((uint32_t)0x00000040)
7 z" M1 l' D: k+ g/ A' r: I
#define RCC_APB2ENR_UART10EN ((uint32_t)0x00000080)
; X/ K8 j, u4 s6 r- _. Z
#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
; w, x( G5 c, u5 h! z# N
#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)0 b, J! ~1 v. v6 C0 N4 `) S
#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)$ H! Q" r) r# C3 k! [# w
#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
; ^ R' R2 P/ u1 q
#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)" k4 |% v# c' |! }: P' m
#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)8 h) K" }1 G) l8 a1 U& I# _+ R
#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
, J! \$ C C1 G4 s# T
#define RCC_APB2ENR_EXTIEN ((uint32_t)0x00008000)
0 [9 S% A8 o5 t4 X; W ?" X
#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
" j( L8 a7 w- b& d5 t' C6 X+ N6 n1 I
#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000) n* n7 Z, b' t i' _1 f, R
#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
% D, n+ v( c" {% m) E
#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
" t2 b- D+ j9 W- R- O5 K: M2 p
#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
0 l2 Q G6 C8 F- I+ R1 M k
#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
; v2 v5 K4 z, Y. S' @+ x
#if defined(STM32F446xx)
4 n0 e4 {: S" X
#define RCC_APB2ENR_SAI2EN ((uint32_t)0x00800000); ~! F& |: e0 h* V; ^# c7 }! c
#endif /* STM32F446xx */: n( Z/ k$ P- H$ }! h& v4 [1 C. w# v
#define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)$ A- p: Y+ E, j: v1 m' _3 N1 V
#if defined(STM32F469_479xx)
; y0 x3 M/ |3 s
#define RCC_APB2ENR_DSIEN ((uint32_t)0x08000000)
; A; M; b1 z7 p) \0 F2 A
#endif /* STM32F469_479xx */
& f) J9 x$ J/ @
#if defined(STM32F412xG) || defined(STM32F413_423xx)
) _4 ^2 V' w0 D0 R( c! T
#define RCC_APB2ENR_DFSDM1EN ((uint32_t)0x01000000)' P5 w0 F& ^7 c
#endif /* STM32F412xG || STM32F413_423xx */2 c$ J, I2 F* r3 A2 z% g& C @
#if defined(STM32F413_423xx)
; ^6 I4 F" V2 ]# T3 P- x
#define RCC_APB2ENR_DFSDM2EN ((uint32_t)0x02000000)
0 P, M o. M. d) V5 F
#endif /* STM32F413_423xx */
7 s6 }9 y; h. B
/******************** Bit definition for RCC_AHB1LPENR register *************/
) p# [3 ?5 u8 N. A' O2 o
#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)* b4 F% F5 ~$ X) J+ Z
#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)" ]% G0 A/ X- W- h. C0 _
#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
& @9 M1 n0 I( J% d
#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)/ z) v7 z5 K1 H ^: O
#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
, P; o" k* n2 r V) H# M" p4 m
#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)0 w. @( B/ c# x1 v) h1 O
#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
$ D1 a# V% k$ D9 K7 g
#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)4 ]# O$ }+ `7 T l+ p6 x
#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)4 A7 K) ?- G8 \) X, P; X, w) _
#define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)" L1 v% e% F" Z/ M6 j/ b' Z
#define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)7 d1 g: |7 y6 K0 b4 D
#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)' S. e. r% X$ k1 s0 a
#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)6 q- D2 I8 B9 p2 K7 y8 x0 u
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)) l& N7 h5 u. t @/ U. M2 q. m1 p! m
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)' F" A% l* f8 Z6 o6 M; A6 D
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
' Q8 y, k- a" @( _
#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)$ Z q- p/ i4 B. \& I% `9 {% v* T
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)# p" U! ?# W* G- R3 O. D
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)1 N2 y0 ^# c/ X
#define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
0 P5 X) G: z% k3 C4 R) Q' y
#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)9 r6 o- ~( [0 Z' b, y9 v
#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
6 L" C V8 ]8 u6 G
#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
) a" q: v1 l. w X9 v$ V O
#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
+ z5 {$ t' f! c# \
#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)8 l5 ?% q, @- E' A% T9 N0 @
#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)* ^( l" m3 ^: L, \7 m
" g6 }3 a0 E* b# ~- t; { y
/******************** Bit definition for RCC_AHB2LPENR register *************/
$ i, I0 x* ?; `: E( B$ i/ |$ y
#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
$ ?: O# P9 J& @5 c$ u- C
#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010), F. V, t$ l" d) ^) x6 v
#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)1 }7 V4 J4 C/ Y- U8 l% a9 x& C0 D
#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
' C% I4 a" x1 H6 @5 _% ?- y
#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)$ v6 H0 O4 P$ |. r5 D5 p
9 E5 m2 @$ [* Q0 {' K% i* T$ P3 r' c9 j
/******************** Bit definition for RCC_AHB3LPENR register *************/: {; {7 o) H+ `4 t" @) s$ B) R
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)* W/ G8 s) z+ c( r- b8 Q" C5 x. D+ s
#define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)% ~1 S& x% V: q$ `
#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
1 [0 M: D( y2 ]. M- _3 w
+ x. W+ i3 b9 [& `2 w/ w4 M
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)7 `; G. Q) c6 `5 I& l( J
#define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
# u: D, p* W, D0 H3 c3 v
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
) P t7 J4 Z$ Z+ q
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)$ N9 M6 c/ V; I% }* c# Z
#define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002)
, w$ g$ } f$ o
#endif /* STM32F412xG || STM32F413_423xx || STM32F469_479xx || STM32F446xx */% `: G+ o+ o& Q" s$ \& W6 b$ `5 V
6 v! T' [ z' p, A# A
/******************** Bit definition for RCC_APB1LPENR register *************/
' I, ?* P) D# k( Q/ w, S2 F: E
#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
4 |, I6 c2 i* e6 r9 w f W
#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)1 z" W$ }" u9 `4 d6 z. h
#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
9 @7 P5 p! l& j; \
#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)3 \3 C) e0 b* v6 |% v8 W5 z
#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)8 D& t( `# {% S D
#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
: ~; Y, p5 L9 {$ {
#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040) b; i1 r+ Z, p D9 G7 \" L C
#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
, ^) |& Y' M/ f/ r0 q6 U7 L- W; |1 q+ m
#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
, n% d% M9 ^" |0 M* Y0 o `7 G
#if defined(STM32F410xx) || defined(STM32F413_423xx). t0 P/ S2 k: L3 M$ K3 W; Y+ S
#define RCC_APB1LPENR_LPTIM1LPEN ((uint32_t)0x00000200)2 ~+ h/ |% x+ o5 ^" E( j' B& x% E; c
#endif /* STM32F410xx || STM32F413_423xx */
# N6 t% W5 J5 }- e2 i( Z8 ?' v; Y
#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800): k% I0 R' J# C' ~3 k0 D& `
#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
6 ~8 |/ D: h2 p! W
#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000): l, Z* S, Q) n. s: }* L& ^. Q0 N8 E
#if defined(STM32F446xx)! N7 Z" ~7 D9 f) n! [
#define RCC_APB1LPENR_SPDIFRXLPEN ((uint32_t)0x00010000)
3 Q7 X$ i2 j( ~, I e
#endif /* STM32F446xx */( @1 X3 @1 k' Y8 ]9 }
#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)- Z, O! E( x' \
#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)+ t3 k& Z5 F) o
#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)6 c/ Z; Q7 R* l: I }
#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)8 n1 ?. l' `' h! a! X9 E
#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
6 M# I% d a9 R: }( y2 O
#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
1 g# p+ D0 k2 E" w
#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
# b" E( W$ d; D
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)8 l- v+ {' H4 r5 D3 h5 d" U' p
#define RCC_APB1LPENR_FMPI2C1LPEN ((uint32_t)0x01000000)* @: A* {' c8 f; `' J6 @
#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */% v( m1 b* k$ O) b$ \
#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)1 v" c# E. X# y7 ^. _3 `8 [0 j
#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
^: ?- p( h) C2 j, r& c9 r
#if defined(STM32F446xx) K& f% D6 v- x' F/ j* r/ n
#define RCC_APB1LPENR_CECLPEN ((uint32_t)0x08000000)
6 `# x; B1 Z! c
#endif /* STM32F446xx */% \; L" L" e6 C5 a6 t
#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)5 C3 L# |5 F! G
#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
( ~4 L2 X1 v6 {# g& R
#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000). m1 T+ R) ]" [5 E: \6 o
#define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
3 w) `/ b! S/ s- U5 A
2 W$ U [/ Z. g- a6 Z
/******************** Bit definition for RCC_APB2LPENR register *************/# T/ S3 Y2 P- E! u3 C H
#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
: B3 L! w# @$ I" y$ i
#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
- }/ ^1 Q6 V' P' d9 p& A* D
#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)4 N3 N6 C9 U" Z2 p( ~
#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)3 n" S; ^: ^; \5 W& T
#define RCC_APB2LPENR_UART9LPEN ((uint32_t)0x00000040)
" y/ ~1 a4 y2 m' i1 F
#define RCC_APB2LPENR_UART10LPEN ((uint32_t)0x00000080)! G$ t d0 c4 f( s" ?. U1 _( C# G7 g
#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
- d) y0 Y0 p0 ~2 ?' i# E" o
#define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)( j1 F% U" I! N
#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)* X# r; }+ a, E% b7 |1 d2 f
#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
: @3 w1 t* Z* Q- b5 F1 ~) s
#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)! o2 C, b' }4 p5 b' r$ x# a; t' i
#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
; g. C% t6 i5 N ?8 @# R
#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
# M& k u# r* v1 V9 ]
#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)1 h8 K+ r( ?% V3 t N; y' W$ Z
#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
/ U6 u. P1 {# ^3 l# g G
#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)( d( [3 o/ N; k- R& h( L# d
#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)6 ]9 X/ ~/ y% B! b' K1 s* P, v
#define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)7 {' z) w' ^8 s/ m9 K2 O# C
#define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
- B8 L8 e% Y4 h- G9 x
#if defined(STM32F446xx)
5 t% C/ H3 Y6 B
#define RCC_APB2LPENR_SAI2LPEN ((uint32_t)0x00800000)
) @9 N& @$ P- Y0 m) v7 }: J
#endif /* STM32F446xx */* l, |# f; [: u) @1 q0 S
#define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)& ]6 W5 D4 I5 F; J
#if defined(STM32F469_479xx)" M; V+ ^/ q! d5 u. J$ K
#define RCC_APB2LPENR_DSILPEN ((uint32_t)0x08000000)# k/ O3 A* Z5 W6 t
#endif /* STM32F469_479xx */# C* W5 i8 N; S
#if defined(STM32F412xG) || defined(STM32F413_423xx) u% O4 u: T8 k5 ?8 a! [
#define RCC_APB2LPENR_DFSDM1LPEN ((uint32_t)0x01000000)
. @. R R& d2 a) Y: f
#endif /* STM32F412xG || STM32F413_423xx */" o: B1 S; t3 u2 _0 s U* ?
#if defined(STM32F413_423xx)
9 i: _/ j- I& l q$ E
#define RCC_APB2LPENR_DFSDM2LPEN ((uint32_t)0x02000000)" C3 r5 e' p6 j- w% J+ U* }- P
#endif /* STM32F413_423xx */1 t. b5 X$ D8 V( ]
# ^: r6 _( E6 Z4 ^ p+ E
/******************** Bit definition for RCC_BDCR register ******************// I1 Y4 G9 N- w6 D
#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
3 P6 Y" [0 p5 p& A
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
! x( Z+ c. g, e0 J
#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004). p: X8 }# R$ h7 R _' P8 R9 H5 g1 _
#define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)$ f: k- U! B+ F! V/ E$ Q
3 G( m2 D' q$ G
#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)9 P1 Q9 X. B* |6 U" x% @" t5 e
#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
" C& [" p% u( \
#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)$ d1 [& M% g" G) [) F* {/ c# _
4 _# e8 A" P3 O
#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
' x; Z c( b* e( y) E
#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
! y/ p: B0 K0 l4 q
q9 X6 N/ Q4 r
/******************** Bit definition for RCC_CSR register *******************/& x3 E. w. x" `& z# f% D
#define RCC_CSR_LSION ((uint32_t)0x00000001)
. p& h: w. `: h/ k1 T
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)# L4 p& [7 P( Q" y
#define RCC_CSR_RMVF ((uint32_t)0x01000000)( h' R2 L, Z) K! b
#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
4 ^9 Z, M! B4 W, A
#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
: G- T/ X& C* L1 L% F- B1 N
#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)) P. {# R" t2 c% S* V! g
#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
7 t+ T7 d4 o! V
#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
% G5 r' `; {1 k; P6 `
#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)+ H4 A0 y. R$ d7 c1 P
#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000). A9 V0 m. Q8 B
6 d2 i1 [/ J- p1 M
/******************** Bit definition for RCC_SSCGR register *****************/; `! @! G/ p7 v6 ~. e, z- d
#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
0 c M- k5 n, P. |5 T+ s2 S2 M
#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)7 g2 @. R7 y6 P5 r" e
#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)' N$ i/ o+ `( }/ I
#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
9 y6 a2 X# x1 J/ D$ N7 B/ X
7 i' S# L& l2 E! I# v
/******************** Bit definition for RCC_PLLI2SCFGR register ************/
- H: q, Z4 \9 r* p: J
#define RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F); @2 | @3 K& G
#define RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001)' f! T- o6 \$ S/ |2 \- o/ I
#define RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002)3 O7 C& I+ \1 J& S
#define RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004)% D+ E; L% k9 o. s7 Y3 r
#define RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008)
( B0 ^5 ~- c8 [* \% v0 R
#define RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010)
: ^0 q) g* W! V" t& y
#define RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020); c+ s' L, ?) X, G- ^
: e. Z7 C9 }; S7 T7 {, ~
#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
0 s2 G2 F) T; j6 n% l
#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040) t# i' x2 O0 S: J) N
#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080). c @8 u z3 j- h: u" w9 f; }
#define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100), R% Z4 J% V) E, B+ c* e- J
#define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
6 q$ m5 Q% d" g/ {
#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)) {) Q2 Y, H1 r2 e) L- p" O
#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
. J0 @( O! n; n/ E1 r- Z
#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000). i4 C0 |) ~% b) t
#define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)$ F; B6 S2 d7 L
#define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)& I% |4 P2 f# f8 |
5 o9 `* ?4 v: [9 `1 ?, j
#if defined(STM32F412xG) || defined(STM32F413_423xx) @/ Q! ]+ b% E- i5 ?
#define RCC_PLLI2SCFGR_PLLI2SSRC ((uint32_t)0x00400000)
# o$ B0 @* v, I7 h- h( ~% F
#endif /* STM32F412xG || STM32F413_423xx */
8 e* A6 i' m& G/ t4 H( W
" k+ B. V( b& Y; {
#if defined(STM32F446xx)
Y8 ~% z; e0 f/ s# Q7 q8 D
#define RCC_PLLI2SCFGR_PLLI2SP ((uint32_t)0x00030000)( }/ [4 L. g9 s$ ?
#define RCC_PLLI2SCFGR_PLLI2SP_0 ((uint32_t)0x00010000)' S; ^3 V6 A( c
#define RCC_PLLI2SCFGR_PLLI2SP_1 ((uint32_t)0x00020000)
: u7 P$ D" K- C, ?: q
#endif /* STM32F446xx */" P5 M( a) V, w4 l4 C- x$ d2 a
, @+ g; v' {5 x. j$ C" ~$ B" J
#define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
" w7 X1 A) n. A5 E$ Y, ^
#define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
. l& E1 j3 o. X8 G+ B+ D
#define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
: D) m; V% u# K& l( Z. c! e+ [
#define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
6 D! C, [& `+ _6 o
#define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
" {# F# N6 A" }
' ~! m) E, a0 K0 Q6 u+ t# c
#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
2 `3 Q& z7 h1 m k. |
#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
/ H% @0 T; ~6 q& |# c
#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
2 r R8 _* \7 C+ Y( u
#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
8 Y: N e4 _9 q$ o
" I' }; F O3 o8 b6 ?
/******************** Bit definition for RCC_PLLSAICFGR register ************/- Y: M) @! H. Y, V+ c' A$ H6 X
#if defined(STM32F446xx)7 V) q. _2 g. q/ \
#define RCC_PLLSAICFGR_PLLSAIM ((uint32_t)0x0000003F)' p) R' F3 W: q7 g" W) Q
#define RCC_PLLSAICFGR_PLLSAIM_0 ((uint32_t)0x00000001); B" D' z- Z* ~3 s0 S4 x" G
#define RCC_PLLSAICFGR_PLLSAIM_1 ((uint32_t)0x00000002)
/ b. Z& i' \1 q0 `6 r
#define RCC_PLLSAICFGR_PLLSAIM_2 ((uint32_t)0x00000004)
3 ` ]2 b0 g! u, M. E
#define RCC_PLLSAICFGR_PLLSAIM_3 ((uint32_t)0x00000008)4 p5 j6 G$ t' q5 @7 U
#define RCC_PLLSAICFGR_PLLSAIM_4 ((uint32_t)0x00000010)
7 C& k0 e2 R1 H1 k
#define RCC_PLLSAICFGR_PLLSAIM_5 ((uint32_t)0x00000020)0 \9 S5 w# Z) r
#endif /* STM32F446xx */, f; M/ @* v" [. u* X
2 o! d8 b; e c7 Z; X0 h
#define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
+ u6 t- A- x8 k) S& `( X# ]5 q
#define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
1 W8 Y; \" Z9 p# ^- d( o1 U5 s9 W* Y
#define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)2 |7 z) \$ Y" s1 {8 M6 f
#define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)9 r$ T) U# Q0 ]0 u9 o) B
#define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
1 m V9 v9 j: ?) y [- R2 F% a
#define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
' `: U/ x! t$ B, n0 I0 G3 H
#define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
' X4 c7 O8 `5 {
#define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)/ j. A8 X5 i5 i; H6 [. u
#define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)7 P+ g, Q( k# F4 t1 S
#define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
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#if defined(STM32F446xx) || defined(STM32F469_479xx)
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#define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)
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#define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)
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#define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)0 D' N' G+ H9 T
#endif /* STM32F446xx || STM32F469_479xx */
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#define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)# p: k# h- m1 W) i5 H
#define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
#define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)" R) @$ Z: T' j! F% P
#define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
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#define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
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#define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)
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#define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)
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#define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)* o3 q* z* Y: }* b6 @, W$ W
#define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)
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/******************** Bit definition for RCC_DCKCFGR register ***************/
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#define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)
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#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)# w+ @- U. ]" Q! R9 o
#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
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#if defined(STM32F412xG) || defined(STM32F413_423xx). ]& E9 X$ Y( R2 v) \) d! k3 c& K
#define RCC_DCKCFGR_CKDFSDM1SEL ((uint32_t)0x80000000) A3 K1 B. d0 B1 ^ c. [1 i
#define RCC_DCKCFGR_CKDFSDM1ASEL ((uint32_t)0x00008000)
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#endif /* STM32F412xG || STM32F413_423xx */6 _3 {$ y4 O. w
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#if defined(STM32F413_423xx)
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#define RCC_DCKCFGR_PLLI2SDIVR ((uint32_t)0x0000001F)
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#define RCC_DCKCFGR_PLLI2SDIVR_0 ((uint32_t)0x00000001)7 o9 h" ?. t" o; V
#define RCC_DCKCFGR_PLLI2SDIVR_1 ((uint32_t)0x00000002): H' e2 R: H7 U7 \
#define RCC_DCKCFGR_PLLI2SDIVR_2 ((uint32_t)0x00000004)% |9 D" s' i# Q
#define RCC_DCKCFGR_PLLI2SDIVR_3 ((uint32_t)0x00000008)
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#define RCC_DCKCFGR_PLLI2SDIVR_4 ((uint32_t)0x00000010)
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#define RCC_DCKCFGR_PLLDIVR ((uint32_t)0x00001F00)- }3 i8 ~4 j2 {
#define RCC_DCKCFGR_PLLDIVR_0 ((uint32_t)0x00000100); z; w* r6 c" y$ O: T
#define RCC_DCKCFGR_PLLDIVR_1 ((uint32_t)0x00000200)
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#define RCC_DCKCFGR_PLLDIVR_2 ((uint32_t)0x00000400)5 q3 q. W3 T, m
#define RCC_DCKCFGR_PLLDIVR_3 ((uint32_t)0x00000800)
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#define RCC_DCKCFGR_PLLDIVR_4 ((uint32_t)0x00001000)
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#define RCC_DCKCFGR_CKDFSDM2ASEL ((uint32_t)0x00004000)0 v- y( P. h6 n
#endif /* STM32F413_423xx */. |, f- H, ^2 q5 z0 x7 B) E
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#define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)1 x U. V0 Z- ^# s: n
#define RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000)- c- }* c: d$ U
#define RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000)
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#if defined(STM32F446xx)' P9 s5 V" i0 y1 e4 |
#define RCC_DCKCFGR_SAI1SRC ((uint32_t)0x00300000), [8 B/ Z! f& z8 \/ w# q) p
#define RCC_DCKCFGR_SAI1SRC_0 ((uint32_t)0x00100000)3 z9 y2 z1 |; X1 U- t l" L& X; k
#define RCC_DCKCFGR_SAI1SRC_1 ((uint32_t)0x00200000)
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#endif /* STM32F446xx */" q5 C+ w2 L" K% K& z
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#define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
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#define RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000)( ~' G7 k/ ]" a) F$ n4 w
#define RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000)
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#if defined(STM32F446xx)) s, Q4 D8 A9 D
#define RCC_DCKCFGR_SAI2SRC ((uint32_t)0x00C00000)- C6 d0 Y$ O. N: ?! X
#define RCC_DCKCFGR_SAI2SRC_0 ((uint32_t)0x00400000)# }- V; `; m& b: m
#define RCC_DCKCFGR_SAI2SRC_1 ((uint32_t)0x00800000) ^+ [1 w/ U; F# l
#endif /* STM32F446xx */# L9 J. T- H& g
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#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)( N/ h! a" Q" x8 \0 p
#if defined(STM32F469_479xx)
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#define RCC_DCKCFGR_CK48MSEL ((uint32_t)0x08000000)* [1 U @( s$ p( \+ s7 o7 @, P& y5 G
#define RCC_DCKCFGR_SDIOSEL ((uint32_t)0x10000000)
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#define RCC_DCKCFGR_DSISEL ((uint32_t)0x20000000)
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#endif /* STM32F469_479xx */( J, L& I5 z) s' {- ?5 @% N1 s
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#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
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#define RCC_DCKCFGR_I2S1SRC ((uint32_t)0x06000000)3 j' u. ~1 u7 b
#define RCC_DCKCFGR_I2S1SRC_0 ((uint32_t)0x02000000)5 E1 t1 B: P' w0 `' U6 J. a
#define RCC_DCKCFGR_I2S1SRC_1 ((uint32_t)0x04000000)! L a# I4 U7 b1 m% u
#define RCC_DCKCFGR_I2S2SRC ((uint32_t)0x18000000)% R6 t! K$ r: T* r
#define RCC_DCKCFGR_I2S2SRC_0 ((uint32_t)0x08000000)
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#define RCC_DCKCFGR_I2S2SRC_1 ((uint32_t)0x10000000)
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/******************** Bit definition for RCC_CKGATENR register ***************/
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#define RCC_CKGATENR_AHB2APB1_CKEN ((uint32_t)0x00000001)7 Y f, Q; U; U9 [1 ]
#define RCC_CKGATENR_AHB2APB2_CKEN ((uint32_t)0x00000002); r$ e+ U: a B$ U! ?
#define RCC_CKGATENR_CM4DBG_CKEN ((uint32_t)0x00000004)
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#define RCC_CKGATENR_SPARE_CKEN ((uint32_t)0x00000008)$ b" p6 B7 x' _- T4 k
#define RCC_CKGATENR_SRAM_CKEN ((uint32_t)0x00000010)
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#define RCC_CKGATENR_FLITF_CKEN ((uint32_t)0x00000020)4 u: I5 D1 o# Z& Y8 T( i- H1 A `
#define RCC_CKGATENR_RCC_CKEN ((uint32_t)0x00000040)2 y2 g/ a3 f2 u! W5 V: ?* J) {
#if defined(STM32F412xG) || defined(STM32F413_423xx)
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#define RCC_CKGATENR_RCC_EVTCTL ((uint32_t)0x00000080)
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#endif /* STM32F412xG || STM32F413_423xx */) c% q# T: I+ i: |
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/******************** Bit definition for RCC_DCKCFGR2 register ***************/; x! |. C$ f2 K
#define RCC_DCKCFGR2_FMPI2C1SEL ((uint32_t)0x00C00000)
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#define RCC_DCKCFGR2_FMPI2C1SEL_0 ((uint32_t)0x00400000)
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#define RCC_DCKCFGR2_FMPI2C1SEL_1 ((uint32_t)0x00800000)
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#define RCC_DCKCFGR2_CECSEL ((uint32_t)0x04000000)
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#define RCC_DCKCFGR2_CK48MSEL ((uint32_t)0x08000000)
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#define RCC_DCKCFGR2_SDIOSEL ((uint32_t)0x10000000)
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#if defined(STM32F446xx)
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#define RCC_DCKCFGR2_SPDIFRXSEL ((uint32_t)0x20000000)/ _; ]& R5 N& @1 }' K. g
#endif /* STM32F446xx */
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#if defined(STM32F413_423xx)5 w; C5 L" \" Q7 p; J
#define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0xC0000000)
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#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x40000000)5 `& x$ B, f% D" {( `" c
#define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x80000000) g$ t$ A7 o& D9 j2 Y
#endif /* STM32F413_423xx */
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#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */" f* L% z- Y. `3 Y7 X
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#if defined(STM32F410xx)
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#define RCC_DCKCFGR_I2SSRC ((uint32_t)0x06000000)+ B5 |4 I/ ^7 ^" ^
#define RCC_DCKCFGR_I2SSRC_0 ((uint32_t)0x02000000)
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#define RCC_DCKCFGR_I2SSRC_1 ((uint32_t)0x04000000)
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#endif /* STM32F410xx */( a3 [7 E0 J1 _* ?: O! [* ` @
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#if defined(STM32F410xx), c7 y) e+ L, l
/******************** Bit definition for RCC_DCKCFGR2 register **************/+ e( I6 g) _1 \
#define RCC_DCKCFGR2_FMPI2C1SEL ((uint32_t)0x00C00000)2 U0 c2 C9 W3 {8 |1 Y$ ~3 E8 p
#define RCC_DCKCFGR2_FMPI2C1SEL_0 ((uint32_t)0x00400000)
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#define RCC_DCKCFGR2_FMPI2C1SEL_1 ((uint32_t)0x00800000)
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#define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0xC0000000)
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#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x40000000)# i4 }4 f. T3 a+ e$ a
#define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x80000000)
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#endif /* STM32F410xx */
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