【经验分享】STM32 时钟相关函数和类型

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STMCU小助手发布时间：2022-6-10 20:14

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文章封面:
文章简介:	STM32 时钟相关函数和类型

01. 概述
在 STM32F4 标准固件库里，时钟源的选择以及时钟使能等函数都是在 RCC 相关固件库文件 stm32f4xx_rcc.h 和 stm32f4xx_rcc.c 中声明和定义的。大家打开 stm32f4xx_rcc.h 文件可以看到文件开头有很多宏定义标识符，然后是一系列时钟配置和时钟使能函数申明。这些函数大致可以归结为三类，一类是外设时钟使能函数，一类是时钟源和分频因子配置函数，还有一类是外设复位函数。当然还有几个获取时钟源配置的函数。

02. 相关类型
RCC_ClocksTypeDef

/* Exported types ------------------------------------------------------------*/
typedef struct
{
uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
}RCC_ClocksTypeDef;

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RCC_HSE_configuration

/** @defgroup RCC_HSE_configuration
* @{
*/
#define RCC_HSE_OFF ((uint8_t)0x00)
#define RCC_HSE_ON ((uint8_t)0x01)
#define RCC_HSE_Bypass ((uint8_t)0x05)
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
((HSE) == RCC_HSE_Bypass))

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RCC_LSE_Dual_Mode_Selection

/** @defgroup RCC_LSE_Dual_Mode_Selection
* @{
*/
#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \
((MODE) == RCC_LSE_HIGHDRIVE_MODE))

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RCC_PLLSAIDivR_Factor

/** @defgroup RCC_PLLSAIDivR_Factor
* @{
*/
#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)
#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)
#define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)
#define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)
#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\
((VALUE) == RCC_PLLSAIDivR_Div4) ||\
((VALUE) == RCC_PLLSAIDivR_Div8) ||\
((VALUE) == RCC_PLLSAIDivR_Div16))

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RCC_PLL_Clock_Source

/** @defgroup RCC_PLL_Clock_Source
* @{
*/
#define RCC_PLLSource_HSI ((uint32_t)0x00000000)
#define RCC_PLLSource_HSE ((uint32_t)0x00400000)
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
((SOURCE) == RCC_PLLSource_HSE))
#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) ||
((VALUE) == 6) || ((VALUE) == 8))
#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
|| defined(STM32F446xx) || defined(STM32F469_479xx)
#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx
|| STM32F469_479xx */
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#if defined(STM32F446xx)
#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4)
|| ((VALUE) == 6) || ((VALUE) == 8))
#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
#elif defined(STM32F412xG) || defined(STM32F413_423xx)
#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4)
|| ((VALUE) == 6) || ((VALUE) == 8))
#else
#endif /* STM32F446xx */
#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
#if defined(STM32F446xx) || defined(STM32F469_479xx)
#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4)
|| ((VALUE) == 6) || ((VALUE) == 8))
#endif /* STM32F446xx || STM32F469_479xx */
#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
#if defined(STM32F413_423xx)
#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
#endif /* STM32F413_423xx */

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RCC_System_Clock_Source

/** @defgroup RCC_System_Clock_Source
* @{
*/
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
#define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002)
#define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003)
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
((SOURCE) == RCC_SYSCLKSource_HSE) || \
((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \
((SOURCE) == RCC_SYSCLKSource_PLLRCLK))
/* Add legacy definition */
#define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK
#endif /* STM32F446xx */
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx)
|| defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE)
|| defined(STM32F469_479xx)
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
((SOURCE) == RCC_SYSCLKSource_HSE) || \
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx
|| STM32F410xx || STM32F411xE || STM32F469_479xx */

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RCC_AHB_Clock_Source

/** @defgroup RCC_AHB_Clock_Source
* @{
*/
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
((HCLK) == RCC_SYSCLK_Div512))

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RCC_APB1_APB2_Clock_Source

/** @defgroup RCC_APB1_APB2_Clock_Source
* @{
*/
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
#define RCC_HCLK_Div2 ((uint32_t)0x00001000)
#define RCC_HCLK_Div4 ((uint32_t)0x00001400)
#define RCC_HCLK_Div8 ((uint32_t)0x00001800)
#define RCC_HCLK_Div16 ((uint32_t)0x00001C00)
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
((PCLK) == RCC_HCLK_Div16))

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RCC_Interrupt_Source

/** @defgroup RCC_Interrupt_Source
* @{
*/
#define RCC_IT_LSIRDY ((uint8_t)0x01)
#define RCC_IT_LSERDY ((uint8_t)0x02)
#define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
#define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
#define RCC_IT_CSS ((uint8_t)0x80)
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)

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RCC_LSE_Configuration

/** @defgroup RCC_LSE_Configuration
* @{
*/
#define RCC_LSE_OFF ((uint8_t)0x00)
#define RCC_LSE_ON ((uint8_t)0x01)
#define RCC_LSE_Bypass ((uint8_t)0x04)
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
((LSE) == RCC_LSE_Bypass))

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RCC_RTC_Clock_Source

/** @defgroup RCC_RTC_Clock_Source
* @{
*/
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)
#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)
#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)
#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)
#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)
#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)
#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)
#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)
#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)
#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)
#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)
#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)
#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)
#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)
#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)
#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
((SOURCE) == RCC_RTCCLKSource_LSI) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div31))

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RCC_SAI_BlockA_Clock_Source

/** @defgroup RCC_SAI_BlockA_Clock_Source
* @{
*/
#define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000)
#define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000)
#define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000)
#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\
((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\
((SOURCE) == RCC_SAIACLKSource_Ext))

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RCC_SAI_BlockB_Clock_Source

/** @defgroup RCC_SAI_BlockB_Clock_Source
* @{
*/
#define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000)
#define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000)
#define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000)
#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\
((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\
((SOURCE) == RCC_SAIBCLKSource_Ext))

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RCC_TIM_PRescaler_Selection

/** @defgroup RCC_TIM_PRescaler_Selection
* @{
*/
#define RCC_TIMPrescDesactivated ((uint8_t)0x00)
#define RCC_TIMPrescActivated ((uint8_t)0x01)
#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated)
|| ((VALUE) == RCC_TIMPrescActivated))

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RCC_AHB1_Peripherals

/** @defgroup RCC_AHB1_Peripherals
* @{
*/
#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)
#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)
#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)
#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)
#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)
#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200)
#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400)
#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
#define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000)
#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
#define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000)
#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH)
((((PERIPH) & 0x010BE800) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_RESET_PERIPH(PERIPH)
((((PERIPH) & 0x51FE800) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH)
((((PERIPH) & 0x01106800) == 0x00) && ((PERIPH) != 0x00))

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RCC_AHB2_Peripherals

/** @defgroup RCC_AHB2_Peripherals
* @{
*/
#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
#define IS_RCC_AHB2_PERIPH(PERIPH)
((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))

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RCC_APB1_Peripherals

/** @defgroup RCC_APB1_Peripherals
* @{
*/
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
#if defined(STM32F410xx) || defined(STM32F413_423xx)
#define RCC_APB1Periph_LPTIM1 ((uint32_t)0x00000200)
#endif /* STM32F410xx || STM32F413_423xx */
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
#if defined(STM32F446xx)
#define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000)
#endif /* STM32F446xx */
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
#if defined(STM32F410xx) || defined(STM32F412xG)
|| defined(STM32F413_423xx) || defined(STM32F446xx)
#define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000)
#endif /* STM32F410xx || STM32F446xx || STM32F413_423xx*/
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
#if defined(STM32F413_423xx)
#define RCC_APB1Periph_CAN3 ((uint32_t)0x08000000)
#endif /* STM32F413_423xx */
#if defined(STM32F446xx)
#define RCC_APB1Periph_CEC ((uint32_t)0x08000000)
#endif /* STM32F446xx */
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
#define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)
#define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)
#define IS_RCC_APB1_PERIPH(PERIPH)
((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00))

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RCC_APB2_Peripherals

/** @defgroup RCC_APB2_Peripherals
* @{
*/
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)
#define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
#define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000)
#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
#define RCC_APB2Periph_EXTIT ((uint32_t)0x00008000)
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)
#define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000)
#define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000)
#if defined(STM32F446xx) || defined(STM32F469_479xx)
#define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000)
#endif /* STM32F446xx || STM32F469_479xx */
#define RCC_APB2Periph_LTDC ((uint32_t)0x04000000)
#if defined(STM32F469_479xx)
#define RCC_APB2Periph_DSI ((uint32_t)0x08000000)
#endif /* STM32F469_479xx */
#if defined(STM32F412xG) || defined(STM32F413_423xx)
#define RCC_APB2Periph_DFSDM1 ((uint32_t)0x01000000)
#endif /* STM32F412xG || STM32F413_423xx */
#if defined(STM32F413_423xx)
#define RCC_APB2Periph_DFSDM2 ((uint32_t)0x02000000)
#define RCC_APB2Periph_UART9 ((uint32_t)0x02000040)
#define RCC_APB2Periph_UART10 ((uint32_t)0x00000080)
#endif /* STM32F413_423xx */
/* Legacy Defines */
#define RCC_APB2Periph_DFSDM RCC_APB2Periph_DFSDM1
#define IS_RCC_APB2_PERIPH(PERIPH)
((((PERIPH) & 0xF008000C) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_APB2_RESET_PERIPH(PERIPH)
((((PERIPH) & 0xF208860C) == 0x00) && ((PERIPH) != 0x00))

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RCC_MCO1_Clock_Source_Prescaler

/** @defgroup RCC_MCO1_Clock_Source_Prescaler
* @{
*/
#define RCC_MCO1Source_HSI ((uint32_t)0x00000000)
#define RCC_MCO1Source_LSE ((uint32_t)0x00200000)
#define RCC_MCO1Source_HSE ((uint32_t)0x00400000)
#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
#define RCC_MCO1Div_1 ((uint32_t)0x00000000)
#define RCC_MCO1Div_2 ((uint32_t)0x04000000)
#define RCC_MCO1Div_3 ((uint32_t)0x05000000)
#define RCC_MCO1Div_4 ((uint32_t)0x06000000)
#define RCC_MCO1Div_5 ((uint32_t)0x07000000)
#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI)
|| ((SOURCE) == RCC_MCO1Source_LSE) || \
((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
((DIV) == RCC_MCO1Div_5))

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RCC_MCO2_Clock_Source_Prescaler

/** @defgroup RCC_MCO2_Clock_Source_Prescaler
* @{
*/
#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)
#define RCC_MCO2Source_HSE ((uint32_t)0x80000000)
#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)
#define RCC_MCO2Div_1 ((uint32_t)0x00000000)
#define RCC_MCO2Div_2 ((uint32_t)0x20000000)
#define RCC_MCO2Div_3 ((uint32_t)0x28000000)
#define RCC_MCO2Div_4 ((uint32_t)0x30000000)
#define RCC_MCO2Div_5 ((uint32_t)0x38000000)
#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK)
|| ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
((SOURCE) == RCC_MCO2Source_HSE)
|| ((SOURCE) == RCC_MCO2Source_PLLCLK))
#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
((DIV) == RCC_MCO2Div_5))

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RCC_Flag

/** @defgroup RCC_Flag
* @{
*/
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D)
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define RCC_FLAG_BORRST ((uint8_t)0x79)
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \
((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)

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03. 相关函数

/* Function used to set the RCC clock configuration to the default reset state */
void RCC_DeInit(void);
/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
void RCC_HSEConfig(uint8_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_LSEConfig(uint8_t RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN,
uint32_t PLLP, uint32_t PLLQ);
void RCC_PLLI2SCmd(FunctionalState NewState);
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
void RCC_PLLSAICmd(FunctionalState NewState);
void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
/* System, AHB and APB busses clocks configuration functions ******************/
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLK1Config(uint32_t RCC_HCLK);
void RCC_PCLK2Config(uint32_t RCC_HCLK);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
/* Peripheral clocks configuration functions **********************************/
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);
void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);
void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT);

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04. 结构体封装

/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
__IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
__IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
uint32_t RESERVED0; /*!< Reserved, 0x1C */
__IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
__IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
uint32_t RESERVED2; /*!< Reserved, 0x3C */
__IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
__IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
__IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
__IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
uint32_t RESERVED4; /*!< Reserved, 0x5C */
__IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
__IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
__IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
__IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
__IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
__IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
__IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
__IO uint32_t CKGATENR; /*!< RCC Clocks Gated Enable Register, Address offset: 0x90 */ /* Only for STM32F412xG, STM32413_423xx and STM32F446xx devices */
__IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */ /* Only for STM32F410xx, STM32F412xG, STM32413_423xx and STM32F446xx devices */
} RCC_TypeDef;

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05. 其它

/******************************************************************************/
/* */
/* Reset and Clock Control */
/* */
/******************************************************************************/
/******************** Bit definition for RCC_CR register ********************/
#define RCC_CR_HSION ((uint32_t)0x00000001)
#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
#define RCC_CR_HSEON ((uint32_t)0x00010000)
#define RCC_CR_HSERDY ((uint32_t)0x00020000)
#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
#define RCC_CR_CSSON ((uint32_t)0x00080000)
#define RCC_CR_PLLON ((uint32_t)0x01000000)
#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
#define RCC_CR_PLLSAION ((uint32_t)0x10000000)
#define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
/******************** Bit definition for RCC_PLLCFGR register ***************/
#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
#define RCC_PLLCFGR_PLLR ((uint32_t)0x70000000)
#define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x10000000)
#define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x20000000)
#define RCC_PLLCFGR_PLLR_2 ((uint32_t)0x40000000)
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
/******************** Bit definition for RCC_CFGR register ******************/
/*!< SW configuration */
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL/PLLP selected as system clock */
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
#define RCC_CFGR_SW_PLLR ((uint32_t)0x00000003) /*!< PLL/PLLR selected as system clock */
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
/*!< SWS configuration */
#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL/PLLP used as system clock */
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F469_479xx) || defined(STM32F446xx)
#define RCC_CFGR_SWS_PLLR ((uint32_t)0x0000000C) /*!< PLL/PLLR used as system clock */
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
#if defined(STM32F410xx)
/*!< MCO1EN configuration */
#define RCC_CFGR_MCO1EN ((uint32_t)0x00000100) /*!< MCO1EN bit */
/*!< MCO1EN configuration */
#define RCC_CFGR_MCO2EN ((uint32_t)0x00000200) /*!< MCO2EN bit */
#endif /* STM32F410xx */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
/*!< RTCPRE configuration */
#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
/*!< MCO1 configuration */
#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
/******************** Bit definition for RCC_CIR register *******************/
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
#define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
#define RCC_CIR_CSSF ((uint32_t)0x00000080)
#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
#define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
#define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
#define RCC_CIR_CSSC ((uint32_t)0x00800000)
/******************** Bit definition for RCC_AHB1RSTR register **************/
#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
#define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
#define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
#define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)
/* maintained for legacy purpose */
#define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
/******************** Bit definition for RCC_AHB3RSTR register **************/
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
#define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
#define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
/******************** Bit definition for RCC_APB1RSTR register **************/
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
#if defined(STM32F410xx) || defined(STM32F413_423xx)
#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x00000200)
#endif /* STM32F410xx || STM32F413_423xx */
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
#if defined(STM32F446xx)
#define RCC_APB1RSTR_SPDIFRXRST ((uint32_t)0x00010000)
#endif /* STM32F446xx */
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
#define RCC_APB1RSTR_FMPI2C1RST ((uint32_t)0x01000000)
#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
#if defined(STM32F446xx)
#define RCC_APB1RSTR_CECRST ((uint32_t)0x08000000)
#endif /* STM32F446xx */
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
/******************** Bit definition for RCC_APB2RSTR register **************/
#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
#define RCC_APB2RSTR_UART9RST ((uint32_t)0x00000040)
#define RCC_APB2RSTR_UART10RST ((uint32_t)0x00000080)
#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
#define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
#if defined(STM32F446xx)
#define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00800000)
#endif /* STM32F446xx */
#define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
#if defined(STM32F469_479xx)
#define RCC_APB2RSTR_DSIRST ((uint32_t)0x08000000)
#endif /* STM32F469_479xx */
#if defined(STM32F412xG) || defined(STM32F413_423xx)
#define RCC_APB2RSTR_DFSDM1RST ((uint32_t)0x01000000)
#endif /* STM32F412xG || STM32F413_423xx */
#if defined(STM32F413_423xx)
#define RCC_APB2RSTR_DFSDM2RST ((uint32_t)0x02000000)
#endif /* STM32F413_423xx */
/* Old definitions, maintained for legacy purpose */
#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
#define RCC_APB2RSTR_DFSDMRST RCC_APB2RSTR_DFSDM1RST
/******************** Bit definition for RCC_AHB1ENR register ***************/
#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
#define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
#define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
#define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)
#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
/******************** Bit definition for RCC_AHB2ENR register ***************/
#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
/******************** Bit definition for RCC_AHB3ENR register ***************/
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
#define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
/******************** Bit definition for RCC_APB1ENR register ***************/
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
#if defined(STM32F410xx) || defined(STM32F413_423xx)
#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x00000200)
#endif /* STM32F410xx || STM32F413_423xx */
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
#if defined(STM32F446xx)
#define RCC_APB1ENR_SPDIFRXEN ((uint32_t)0x00010000)
#endif /* STM32F446xx */
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
#define RCC_APB1ENR_FMPI2C1EN ((uint32_t)0x01000000)
#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
#if defined(STM32F446xx)
#define RCC_APB1ENR_CECEN ((uint32_t)0x08000000)
#endif /* STM32F446xx */
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
#define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
#define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
/******************** Bit definition for RCC_APB2ENR register ***************/
#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
#define RCC_APB2ENR_UART9EN ((uint32_t)0x00000040)
#define RCC_APB2ENR_UART10EN ((uint32_t)0x00000080)
#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
#define RCC_APB2ENR_EXTIEN ((uint32_t)0x00008000)
#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
#if defined(STM32F446xx)
#define RCC_APB2ENR_SAI2EN ((uint32_t)0x00800000)
#endif /* STM32F446xx */
#define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)
#if defined(STM32F469_479xx)
#define RCC_APB2ENR_DSIEN ((uint32_t)0x08000000)
#endif /* STM32F469_479xx */
#if defined(STM32F412xG) || defined(STM32F413_423xx)
#define RCC_APB2ENR_DFSDM1EN ((uint32_t)0x01000000)
#endif /* STM32F412xG || STM32F413_423xx */
#if defined(STM32F413_423xx)
#define RCC_APB2ENR_DFSDM2EN ((uint32_t)0x02000000)
#endif /* STM32F413_423xx */
/******************** Bit definition for RCC_AHB1LPENR register *************/
#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
#define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
#define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
#define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
/******************** Bit definition for RCC_AHB2LPENR register *************/
#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
/******************** Bit definition for RCC_AHB3LPENR register *************/
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
#define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
#define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
#define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002)
#endif /* STM32F412xG || STM32F413_423xx || STM32F469_479xx || STM32F446xx */
/******************** Bit definition for RCC_APB1LPENR register *************/
#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
#if defined(STM32F410xx) || defined(STM32F413_423xx)
#define RCC_APB1LPENR_LPTIM1LPEN ((uint32_t)0x00000200)
#endif /* STM32F410xx || STM32F413_423xx */
#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
#if defined(STM32F446xx)
#define RCC_APB1LPENR_SPDIFRXLPEN ((uint32_t)0x00010000)
#endif /* STM32F446xx */
#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
#define RCC_APB1LPENR_FMPI2C1LPEN ((uint32_t)0x01000000)
#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
#if defined(STM32F446xx)
#define RCC_APB1LPENR_CECLPEN ((uint32_t)0x08000000)
#endif /* STM32F446xx */
#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
#define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
/******************** Bit definition for RCC_APB2LPENR register *************/
#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
#define RCC_APB2LPENR_UART9LPEN ((uint32_t)0x00000040)
#define RCC_APB2LPENR_UART10LPEN ((uint32_t)0x00000080)
#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
#define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)
#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
#define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
#define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
#if defined(STM32F446xx)
#define RCC_APB2LPENR_SAI2LPEN ((uint32_t)0x00800000)
#endif /* STM32F446xx */
#define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)
#if defined(STM32F469_479xx)
#define RCC_APB2LPENR_DSILPEN ((uint32_t)0x08000000)
#endif /* STM32F469_479xx */
#if defined(STM32F412xG) || defined(STM32F413_423xx)
#define RCC_APB2LPENR_DFSDM1LPEN ((uint32_t)0x01000000)
#endif /* STM32F412xG || STM32F413_423xx */
#if defined(STM32F413_423xx)
#define RCC_APB2LPENR_DFSDM2LPEN ((uint32_t)0x02000000)
#endif /* STM32F413_423xx */
/******************** Bit definition for RCC_BDCR register ******************/
#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
#define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
/******************** Bit definition for RCC_CSR register *******************/
#define RCC_CSR_LSION ((uint32_t)0x00000001)
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
#define RCC_CSR_RMVF ((uint32_t)0x01000000)
#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
/******************** Bit definition for RCC_SSCGR register *****************/
#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
/******************** Bit definition for RCC_PLLI2SCFGR register ************/
#define RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F)
#define RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001)
#define RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002)
#define RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004)
#define RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008)
#define RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010)
#define RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020)
#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
#define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
#define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
#define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
#define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
#if defined(STM32F412xG) || defined(STM32F413_423xx)
#define RCC_PLLI2SCFGR_PLLI2SSRC ((uint32_t)0x00400000)
#endif /* STM32F412xG || STM32F413_423xx */
#if defined(STM32F446xx)
#define RCC_PLLI2SCFGR_PLLI2SP ((uint32_t)0x00030000)
#define RCC_PLLI2SCFGR_PLLI2SP_0 ((uint32_t)0x00010000)
#define RCC_PLLI2SCFGR_PLLI2SP_1 ((uint32_t)0x00020000)
#endif /* STM32F446xx */
#define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
#define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
#define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
#define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
#define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
/******************** Bit definition for RCC_PLLSAICFGR register ************/
#if defined(STM32F446xx)
#define RCC_PLLSAICFGR_PLLSAIM ((uint32_t)0x0000003F)
#define RCC_PLLSAICFGR_PLLSAIM_0 ((uint32_t)0x00000001)
#define RCC_PLLSAICFGR_PLLSAIM_1 ((uint32_t)0x00000002)
#define RCC_PLLSAICFGR_PLLSAIM_2 ((uint32_t)0x00000004)
#define RCC_PLLSAICFGR_PLLSAIM_3 ((uint32_t)0x00000008)
#define RCC_PLLSAICFGR_PLLSAIM_4 ((uint32_t)0x00000010)
#define RCC_PLLSAICFGR_PLLSAIM_5 ((uint32_t)0x00000020)
#endif /* STM32F446xx */
#define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
#define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
#define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
#define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
#define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
#define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
#define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
#define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
#define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
#define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
#if defined(STM32F446xx) || defined(STM32F469_479xx)
#define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)
#define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)
#define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)
#endif /* STM32F446xx || STM32F469_479xx */
#define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
#define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
#define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)
#define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
#define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
#define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)
#define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)
#define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)
#define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)
/******************** Bit definition for RCC_DCKCFGR register ***************/
#define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)
#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
#if defined(STM32F412xG) || defined(STM32F413_423xx)
#define RCC_DCKCFGR_CKDFSDM1SEL ((uint32_t)0x80000000)
#define RCC_DCKCFGR_CKDFSDM1ASEL ((uint32_t)0x00008000)
#endif /* STM32F412xG || STM32F413_423xx */
#if defined(STM32F413_423xx)
#define RCC_DCKCFGR_PLLI2SDIVR ((uint32_t)0x0000001F)
#define RCC_DCKCFGR_PLLI2SDIVR_0 ((uint32_t)0x00000001)
#define RCC_DCKCFGR_PLLI2SDIVR_1 ((uint32_t)0x00000002)
#define RCC_DCKCFGR_PLLI2SDIVR_2 ((uint32_t)0x00000004)
#define RCC_DCKCFGR_PLLI2SDIVR_3 ((uint32_t)0x00000008)
#define RCC_DCKCFGR_PLLI2SDIVR_4 ((uint32_t)0x00000010)
#define RCC_DCKCFGR_PLLDIVR ((uint32_t)0x00001F00)
#define RCC_DCKCFGR_PLLDIVR_0 ((uint32_t)0x00000100)
#define RCC_DCKCFGR_PLLDIVR_1 ((uint32_t)0x00000200)
#define RCC_DCKCFGR_PLLDIVR_2 ((uint32_t)0x00000400)
#define RCC_DCKCFGR_PLLDIVR_3 ((uint32_t)0x00000800)
#define RCC_DCKCFGR_PLLDIVR_4 ((uint32_t)0x00001000)
#define RCC_DCKCFGR_CKDFSDM2ASEL ((uint32_t)0x00004000)
#endif /* STM32F413_423xx */
#define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
#define RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000)
#define RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000)
#if defined(STM32F446xx)
#define RCC_DCKCFGR_SAI1SRC ((uint32_t)0x00300000)
#define RCC_DCKCFGR_SAI1SRC_0 ((uint32_t)0x00100000)
#define RCC_DCKCFGR_SAI1SRC_1 ((uint32_t)0x00200000)
#endif /* STM32F446xx */
#define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
#define RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000)
#define RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000)
#if defined(STM32F446xx)
#define RCC_DCKCFGR_SAI2SRC ((uint32_t)0x00C00000)
#define RCC_DCKCFGR_SAI2SRC_0 ((uint32_t)0x00400000)
#define RCC_DCKCFGR_SAI2SRC_1 ((uint32_t)0x00800000)
#endif /* STM32F446xx */
#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
#if defined(STM32F469_479xx)
#define RCC_DCKCFGR_CK48MSEL ((uint32_t)0x08000000)
#define RCC_DCKCFGR_SDIOSEL ((uint32_t)0x10000000)
#define RCC_DCKCFGR_DSISEL ((uint32_t)0x20000000)
#endif /* STM32F469_479xx */
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
#define RCC_DCKCFGR_I2S1SRC ((uint32_t)0x06000000)
#define RCC_DCKCFGR_I2S1SRC_0 ((uint32_t)0x02000000)
#define RCC_DCKCFGR_I2S1SRC_1 ((uint32_t)0x04000000)
#define RCC_DCKCFGR_I2S2SRC ((uint32_t)0x18000000)
#define RCC_DCKCFGR_I2S2SRC_0 ((uint32_t)0x08000000)
#define RCC_DCKCFGR_I2S2SRC_1 ((uint32_t)0x10000000)
/******************** Bit definition for RCC_CKGATENR register ***************/
#define RCC_CKGATENR_AHB2APB1_CKEN ((uint32_t)0x00000001)
#define RCC_CKGATENR_AHB2APB2_CKEN ((uint32_t)0x00000002)
#define RCC_CKGATENR_CM4DBG_CKEN ((uint32_t)0x00000004)
#define RCC_CKGATENR_SPARE_CKEN ((uint32_t)0x00000008)
#define RCC_CKGATENR_SRAM_CKEN ((uint32_t)0x00000010)
#define RCC_CKGATENR_FLITF_CKEN ((uint32_t)0x00000020)
#define RCC_CKGATENR_RCC_CKEN ((uint32_t)0x00000040)
#if defined(STM32F412xG) || defined(STM32F413_423xx)
#define RCC_CKGATENR_RCC_EVTCTL ((uint32_t)0x00000080)
#endif /* STM32F412xG || STM32F413_423xx */
/******************** Bit definition for RCC_DCKCFGR2 register ***************/
#define RCC_DCKCFGR2_FMPI2C1SEL ((uint32_t)0x00C00000)
#define RCC_DCKCFGR2_FMPI2C1SEL_0 ((uint32_t)0x00400000)
#define RCC_DCKCFGR2_FMPI2C1SEL_1 ((uint32_t)0x00800000)
#define RCC_DCKCFGR2_CECSEL ((uint32_t)0x04000000)
#define RCC_DCKCFGR2_CK48MSEL ((uint32_t)0x08000000)
#define RCC_DCKCFGR2_SDIOSEL ((uint32_t)0x10000000)
#if defined(STM32F446xx)
#define RCC_DCKCFGR2_SPDIFRXSEL ((uint32_t)0x20000000)
#endif /* STM32F446xx */
#if defined(STM32F413_423xx)
#define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0xC0000000)
#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x40000000)
#define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x80000000)
#endif /* STM32F413_423xx */
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
#if defined(STM32F410xx)
#define RCC_DCKCFGR_I2SSRC ((uint32_t)0x06000000)
#define RCC_DCKCFGR_I2SSRC_0 ((uint32_t)0x02000000)
#define RCC_DCKCFGR_I2SSRC_1 ((uint32_t)0x04000000)
#endif /* STM32F410xx */
#if defined(STM32F410xx)
/******************** Bit definition for RCC_DCKCFGR2 register **************/
#define RCC_DCKCFGR2_FMPI2C1SEL ((uint32_t)0x00C00000)
#define RCC_DCKCFGR2_FMPI2C1SEL_0 ((uint32_t)0x00400000)
#define RCC_DCKCFGR2_FMPI2C1SEL_1 ((uint32_t)0x00800000)
#define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0xC0000000)
#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x40000000)
#define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x80000000)
#endif /* STM32F410xx */