01. 概述) C7 v" B+ [1 I* @7 a
中断是微控制器一个很常见的特性,中断由硬件产生,当中断产生以后CPU就会中断当前的流程转而去处理中断服务,Cortex-M内核的MCU提供了一个用于中断管理的嵌套向量中断控制器(NVIC)。
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Cortex-M3和M4的NVIC最多支持240个IRQ中断请求,1个不可屏蔽中断NMI、1个Systick滴答定时器中断和多个异常。
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02. 中断管理
- R0 O; T9 L, L9 W; L k/ Y+ |Cortex-M处理器有多个用于管理中断和异常的可编程寄存器,这些寄存器大多数都在NVIC和系统控制块SCB中,CMSIS将这些寄存器定义为结构体。以STM32F407为例,打开core_cm4.h,有以下两个结构体。
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NVIC_Type类型9 \6 _4 _+ p; p9 ^6 w* Y
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- /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC)., G$ Q1 }/ r/ L9 ? Z8 ~: r
- */
' _- K7 k6 d0 Q0 @$ u) m5 I) h) x/ r - typedef struct
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- __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
& q9 H9 C7 Y8 q d2 t+ [; j - uint32_t RESERVED0[24];
( W% H( I) m( z3 h$ y5 i - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
/ D+ S8 D9 f& \/ X - uint32_t RSERVED1[24];
) s% R* L$ ?+ N' C - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */2 p2 a; N" w! \, _
- uint32_t RESERVED2[24];9 }3 @. S6 m- {) l2 n
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */1 Z2 W5 v- R/ c6 E3 @# @: }/ d
- uint32_t RESERVED3[24];3 j/ H, g7 S- Z6 Y
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
: D9 }1 C! [) o+ M1 S3 z - uint32_t RESERVED4[56];4 l$ l* T7 v$ e& L
- __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */. z" ^0 c5 m5 L8 f1 N( ^
- uint32_t RESERVED5[644];
; w. a! S) B/ B3 S* C - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */; t1 [+ m/ G+ R; K9 i5 n) h# P
- } NVIC_Type;
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: z; Z) d" G: q' s4 C6 jSCB_Type类型) x6 F% [ d4 ~; b! Q* I' ^1 d
6 P3 V7 |5 |0 `, J+ @: M- /** \brief Structure type to access the System Control Block (SCB).. O; r( M* Y4 |" M; X
- */
$ x3 C, `' `- v8 k0 w- I' ^ - typedef struct8 j V1 E/ K) d0 r1 k4 r
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- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
/ X* Q. E, Z2 _7 f4 j, K' D5 l - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
1 e) f% y3 V( ]+ y. G9 t - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
/ j1 n2 k( y& B3 P Q1 B - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
8 i; A2 w8 G4 j9 d6 I+ g - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
, F8 o- ~# c, ]; D. i - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
/ C1 T: b) u! `5 n2 w1 V: w - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
" {( C) k/ w0 s/ Q( h2 T. T \, N* r& } - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */1 n$ m- D2 f8 E6 Y8 w: J( Y! [5 Y
- __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
" l% ]) `' c- g" l# ^) H - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
1 i2 r9 V) q+ w - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
& f9 o ]9 l" Q4 B: ]2 F0 y - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */. f' p5 H' E1 Q9 k
- __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */5 E/ ]4 i$ @( p/ [
- __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
. c* h! t0 m# S& j, C! @; j. i - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
6 Z8 {- W9 C" m) |1 P" j! O% I& U - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
8 G. e: c' n5 [ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
: o4 p. n( K) L8 _/ P - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
$ t# T% B3 P1 T* k9 q8 I - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ K$ h8 `& y( B7 y Z' C" Q4 a2 V6 r - uint32_t RESERVED0[5];2 h% F- f: `5 A. W% U; |
- __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */3 Z# r' j+ U+ @. l: Y, G
- } SCB_Type;
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NVIC和SCB都位于系统控制空间SCS内,SCS的地址从0xe000e000开始,scb和NVIC的地址也在core_cm4.h中有定义
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- /* Memory mapping of Cortex-M4 Hardware */
/ {* P. a1 [8 l& v. h# U - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */) y# B s5 ^5 Y: X
- #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */% f) T6 C/ M4 X7 E
- #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */. ~: h" P; u9 S& I9 G# l1 a. V- N3 A
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- #define SCnSCB ((SCnSCB_Type*)SCS_BASE) /*!< System control Register not in SCB */
8 K( f7 n6 Z" L# k - #define SCB ((SCB_Type*)SCB_BASE) /*!< SCB configuration struct */6 X: f p7 v' n# R# ~! w
- #define NVIC ((NVIC_Type*)NVIC_BASE) /*!< NVIC configuration struct */
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: D+ Z7 i C" T, H; ^03. 优先级分组4 H! d! p7 \( \! P7 k X
当多个中断来临的时候处理器应该响应哪一个中断是由中断的优先级决定的,高优先级的中断(优先级编号小)肯定是首先得到响应,而且高优先级的中断可以抢占低优先级的中断,这个就是中断嵌套。Cortex-M处理器的有些中断是具有固定的优先级的,比如复位、NMI、HardFault,这些中断的优先级都是负数,优先级也是最高的。
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Cortex-M处理器有是三个固定优先级和256个可编程的优先级,最多有128个抢占等级,但是实际的优先级数量是有芯片厂商来决定的。但是绝大多数的芯片都会精简设计的,导致实际上支持的优先级会更少,如8级、16级、32级等等。比如stm32就只有16级优先级。在设计芯片的时候会裁掉表达优先级的几个低端有效位,以减少优先级数,所以不管用多少位来表示优先级,都是MSB对齐的。下图都是用三位来表示优先级。! k' l1 D* G) i
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$ U( g' k% z% [优先级配置寄存器是位宽的,为什么只有128个抢占等级?8位不应该是256个抢占等级吗?为了是抢占机能变得更可控,cortex-M处理器还把256个优先级按位分为高低两段:抢占优先级(分组优先级)和亚优先级(子优先级),NVIC中有一个寄存器是“应用程序中断及复位控制寄存器(AIRCR)”,AIRCR寄存器里面有个位段名为“优先级组”。
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STM32使用了4位,因此最多有5组优先级分组设置,在msic.h中有定义:
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- /** @defgroup MISC_Preemption_Priority_Group 9 G, m5 g- r1 y& o; I
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- #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority, @/ J9 e9 J! E
- 4 bits for subpriority */
9 K( M+ z7 C% i - #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
q% U3 i) m T - 3 bits for subpriority */
* V3 C) B( F- }1 t. r) z ] - #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
$ o4 D8 F+ S0 e% y ^& t. |9 H - 2 bits for subpriority */+ t$ o3 V ~5 z; m
- #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority% u$ n" c0 v+ C; U
- 1 bits for subpriority */
' C7 Y8 \4 d# z; ~$ T - #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
* y+ _+ x/ |; d, N/ y - 0 bits for subpriority */
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; E+ W0 Z* y' E- g! m- #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \1 Q4 T4 v7 w$ H9 l% a8 K
- ((GROUP) == NVIC_PriorityGroup_1) || \0 j3 @4 z( s5 U' I6 j \) [/ H' t
- ((GROUP) == NVIC_PriorityGroup_2) || \ l5 `7 i/ u6 X- |8 I+ Y% F/ N
- ((GROUP) == NVIC_PriorityGroup_3) || \( g& M' |# \7 B- J0 [3 t& ?) O
- ((GROUP) == NVIC_PriorityGroup_4))
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04. 优先级设置
3 E5 \* H$ i# B5 M4 a4 W/ o, k( g每个外部中断都有一个对应的优先级寄存器,每个寄存器占8位,因此最大宽度是8位,但是最小为3位。4个相邻的优先级寄存器拼成1个32位寄存器。如前所述,根据优先级组的设置,优先级又可以分为高低两个位段,分别是抢占优先级和亚优先级。STM32我们已经设置位组4,所以就只有抢占优先级了。优先级就餐器都可以按字节访问,当然也可以按半字、字来访问,有意义的优先级寄存器数目由芯片厂商来实现。; A" X# Q* p L, b+ L4 ~: O
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05. 特殊寄存器" }" |+ _+ O7 ]
5.1 PRIMASK和FAULTMASK寄存器: z& s) S0 i9 B; }
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5.2 BASEPRI寄存器
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$ v7 {( C, ^3 Z7 J8 b06. FreeRTOS中断配置宏
: Z' Q3 a1 t* U/ o4 Y0 q6.1 configPRIO_BITS
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此宏用来设置MCU使用几位优先级,STM32使用的是4位,因此该宏为4。; S0 m( M% t* ^; `
6 W' u; i; W* C5 j3 V8 _2 G- #define configPRIO_BITS 4 /* 15 priority levels */
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6.2 configLIBRARY_LOWEST_INTERRUPT_PRIORITY
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- /* The lowest interrupt priority that can be used in a call to a "set priority"4 O7 v; }9 ^' X a' n: N6 Q
- function. */
4 _( _/ w5 o s1 r$ y - #define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf
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7 z# k7 z0 c+ i9 Y/ r# L6 g该宏用来设置最低优先级,STM32优先级使用了4位,而且STM32配置的使用组4,也就是4位都是抢占优先级。因此优先级数数就是16个,最低优先级就是15。所以该值为15。不同的MCU,此值不同,具体是多少要看所使用的MCU的架构。
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6.3 configKERNEL_INTERRUPT_PRIORITY1 H, m9 O2 M5 m+ {2 a/ @1 u. t
9 `8 B% t9 `( m. Z( W( A- /* Interrupt priorities used by the kernel port layer itself. These are generic
$ ~$ h+ ]! I5 U& j' I% Y' n - to all Cortex-M ports, and do not rely on any particular library functions. */% V9 X# Q0 w- ~: N/ Q7 l
- #define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
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9 T2 ]6 f& C* }+ r" u: E该宏用来设置内核中断优先级。
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$ B! {& H& x2 x# P6 x+ z) x6.4 configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY- /* The highest interrupt priority that can be used by any interrupt service7 K8 C6 c K, w+ Q3 }0 B V
- routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL' R3 J( C0 h% Y
- INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER& |3 u: `# r# H' f+ A
- PRIORITY THAN THIS! (higher priorities are lower numeric values. */
& f; ?) z4 e: Q: P/ `/ |6 s/ N - #define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
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此宏用来设置FreeRTOS系统可管理的最大优先级,就是我们之前讲解的BASEPRI寄存器说的那个阈值优先级,这个可以自由设置,我们这里设置为5.也就是高于5的优先级(优先级小于5)不归FreeRTOS管理。' q7 \3 ~$ ~/ Q4 R$ @& y
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6.5 configMAX_SYSCALL_INTERRUPT_PRIORITY
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- #define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
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此宏设置好以后,低于此优先级的中断可以安全的调用FreeRTOS的API函数,高于此优先级的中断FreeRTOS是不能禁止的。中断服务函数也不能调用FreeRTOS的API函数。2 G6 t' [; z3 x0 o# g1 v2 B9 O, v
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2 A* H1 @3 P9 c6 p07. FreeRTOS开关中断
6 l( V" b) c" b, z1 r( nFreeRTOS开关中断函数为portDISABLE_INTERRUPTS()和portENABLE_INTERRUPTS(),这两个函数在portmacro.h文件中有定义。7 s- I7 }1 f& u& l) P" L
3 K0 e1 G2 M' g8 T- #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()* n& |$ n: z6 a1 D9 P* v
- #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
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可以看出开关中断实际上是通过函数vPortSetBASEPRI( 0 )和vPortRaiseBASEPRI()来实现的,这两个函数如下:9 X% |7 S, E( Y) p* L3 l$ @5 t
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- static portFORCE_INLINE void vPortRaiseBASEPRI( void )8 \0 n9 S! |+ k6 d' `+ u
- {
* P1 I* `9 H; a1 J( |$ j$ }) c - uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
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- __asm7 i$ k7 g# R' E! \ T
- {
5 g/ K" m$ C! j$ n- L - /* Set BASEPRI to the max syscall priority to effect a critical b2 n$ G! ?& i/ W
- * section. */
) Q* _( p9 }9 B/ d - /* *INDENT-OFF* */
3 L: g/ q3 \* {6 @ D/ L - msr basepri, ulNewBASEPRI& N; w/ F: h9 Y! l1 G' l' i/ ]/ U* M
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- /* *INDENT-ON* */8 ]5 U4 a. A* z; ^6 O1 J8 K
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- }
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1 b9 H, L2 [# W- static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )3 D* C0 _! a) @
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- __asm
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- /* Barrier instructions are not used as this function is only used to
. O9 l) F) y# [, C" p* w - * lower the BASEPRI value. */9 D, n% D3 S, W6 ~
- /* *INDENT-OFF* */1 l* e" R5 N- r
- msr basepri, ulBASEPRI
& t1 F8 w3 E0 F. T - /* *INDENT-ON* */7 m( O+ f. m" g( h# C
- }
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