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This example describes how to configure the FMC controller to access the SDRAM memory in low power mode

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吴海红11 提问时间:2025-7-11 08:27 / 未解决

The purpose is to show how the SDRAM can retain data written after entering STOP mode. STOP mode is a CPU low power mode which stops all peripherals clocks in the 1.2V domain. Only internal SRAM and registers content are preserved in this mode.

After SDRAM initialization, the data is written to the memory and a "self refresh" command is sent to the SDRAM. The program waits for USER button to be pushed to enter the CPU in STOP mode, the LED3/LED4 are then turned ON. The wakeup from STOP mode is done when pushing USER Button again (LED3/LED4 switch off) and the CPU returns to RUN mode. At this time, the system clock is reconfigured using the function SystemClock_Config().

Finally, a "normal mode" command is send to SDRAM memory to exit self refresh mode. The data written to SDRAM is read back and checked.

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