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STM32_深圳峰会_黑客松,奖品开箱

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ghost110 发布时间:2021-5-12 10:19
感谢管理“Seven”,因为工作原因不能实地参加STM32的深圳会议,在seven管理的热心组织下,通过线上直播让我了解了这一次的技术盛况,从开始的技术讲解到后期的竞赛直播,各个阶段都充分体现了专业性、素养性。不但使我学习了知识,同时也更好的了解了STM32的相关技术和使用场景,对我个人是一个很大的提升,在此对ST公司和seven管理再次表示感谢。
0 B1 q' D! Z# d" }/ n3 X0 k( Q# D在黑客松的比赛中通过各个参赛队伍的作品,看到了不同的创意,产品技术是固定的,关键看人怎么使用。同样的平台,不同的思考方向,差异化的使用方法,打造出不同的产品方案。十分棒。在观看的过程中有幸获得抽奖奖品“STM32G474”,目前已经收到。谢谢。0 p0 D9 g, ^0 L4 f! j/ X
希望以后的活动更加丰富,开发出更多的产品。
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( S9 C, |- ~; F4 J. Y: D2 v描述+ r- a* g" ?6 U# S$ t0 A5 z3 [0 x2 V
The STM32G474xB/xC/xE devices are based on the high-performance Arm® Cortex®-M4 32-bit RISC core. They operate at a frequency of up to 170 MHz. The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all the Arm single-precision data-processing instructions and all the data types. It also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) which enhances the application’s security.% D9 A9 Q* }, V2 e
These devices embed high-speed memories (512 Kbytes of Flash memory, and 128 Kbytes of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad SPI Flash memory interface, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.: J  L! z* `& F/ I5 L8 Y
The devices also embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, securable memory area and proprietary code readout protection.5 o  w- N$ }3 R; G
The devices embed peripherals allowing mathematical/arithmetic function acceleration (CORDIC for trigonometric functions and FMAC unit for filter functions).6 Y# i+ z- [7 w' y8 E' y; X
They offer five fast 12-bit ADCs (5 Msps), seven comparators, six operational amplifiers, seven DAC channels (3 external and 4 internal), an internal voltage reference buffer, a low-power RTC, two general-purpose 32-bit timers, three 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and one 16-bit low-power timer, and high resolution timer with 184 ps resolution.+ m' v" z. Z5 [. F( P# R
They also feature standard and advanced communication interfaces such as:
% [8 S: m" }; r+ }! B6 b3 Z% o所有功能# I' X2 Q% r, k( d* `0 r8 N
Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 170 MHz with 213 DMIPS, MPU, DSP instructions2 _5 ], o6 o/ `3 z
Operating conditions:
: A' Y8 }& a! R# a$ R8 W: }VDD, VDDA voltage range: 1.71 V to 3.6 V9 y2 ]0 _& k% T2 E' b: n# Q
Mathematical hardware accelerators
3 A- N9 r) l  _* C1 z# K9 `CORDIC for trigonometric functions acceleration0 X5 b, L5 i) Y5 W
FMAC: filter mathematical accelerator6 T0 ~3 T3 h9 v# b
Memories
6 o. k. f: ~" O* S7 X" F512 Kbytes of Flash memory with ECC support, two banks read-while-write, proprietary code readout protection (PCROP), securable memory area, 1 Kbyte OTP
  G0 t/ l+ V( K7 B/ V96 Kbytes of SRAM, with hardware parity check implemented on the first 32 Kbytes
6 X, C* b8 D6 q, O  p9 Z* VRoutine booster: 32 Kbytes of SRAM on instruction and data bus, with hardware parity check (CCM SRAM)7 I1 S7 A, Z- h+ h" f" C, ?% G; S
External memory interface for static memories FSMC supporting SRAM, PSRAM, NOR and NAND memories/ x+ ~* _+ s! F  a# W
Quad-SPI memory interface
! V! s* P, g9 j- C  s4 y7 KReset and supply management
3 D$ ?3 }- K* l6 l- R8 H5 f* VPower-on/power-down reset (POR/PDR/BOR)
  d- x/ j/ x7 l+ }! z  |Programmable voltage detector (PVD)
% \. q$ ?. x; E& L" B; LLow-power modes: sleep, stop, standby and shutdown( t  f  R( ?, I8 d, s- u
VBAT supply for RTC and backup registers
" @8 Y& ~* q7 h# W$ K+ E- z. MClock management0 V  s6 d4 A0 e+ o
4 to 48 MHz crystal oscillator
9 k7 w5 n7 M6 B32 kHz oscillator with calibration# T0 _( ^( x" \/ R) c
Internal 16 MHz RC with PLL option (± 1%)
$ _& M# k  O6 }$ n" @( x9 jInternal 32 kHz RC oscillator (± 5%)- n, V3 x' ?# J. }5 {: b' S5 @$ J
Up to 107 fast I/Os8 x( ?* g) q- E+ U, h# n
All mappable on external interrupt vectors
1 U1 U# a3 Q" ^7 g2 kSeveral I/Os with 5 V tolerant capability
7 U; J4 ~2 C4 ~1 I3 KInterconnect matrix
- E* X( g) O6 ~9 A; j: t) o16-channel DMA controller
  B7 ^, I2 W' t& U. _- ]5 \* n5 x 12-bit ADCs 0.25 µs, up to 42 channels. Resolution up to 16-bit with hardware oversampling, 0 to 3.6 V conversion range6 S8 i' c* Q' A0 k, w" n2 n+ a
7 x 12-bit DAC channels
7 i' B8 k+ Y3 g2 |8 y/ G' r3 x buffered external channels 1 MSPS( T- ^: x2 [  ~: B3 C) d8 ^
4 x unbuffered internal channels 15 MSPS/ ^; w" \. u* E1 L6 J
7 x ultra-fast rail-to-rail analog comparators3 Q7 L; g0 Z( M
6 x operational amplifiers that can be used in PGA mode, all terminals accessible! D! O. z  L9 H+ i' m
Internal voltage reference buffer (VREFBUF) supporting three output voltages (2.048 V, 2.5 V, 2.95 V)
9 D4 F$ X, o! q17 timers:9 j8 r4 t3 e& r- S( K
HRTIM (Hi-Resolution and complex waveform builder): 6 x16-bit counters, 184 ps resolution, 12 PWM
! y5 J, r# D. k- c2 r$ Y! u+ K, s2 x 32-bit timer and 2 x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
/ h0 I, [/ b7 L1 b3 x 16-bit 8-channel advanced motor control timers, with up to 8 x PWM channels, dead time generation and emergency stop$ H' a" f" e; w  |1 G) V' p. O/ o4 v
1 x 16-bit timer with 2 x IC/OCs, one OCN/PWM, dead time generation and emergency stop% U' O  F- h1 ~! v
2 x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop( E4 i0 V+ f2 T6 T* W, }3 R% k
2 x watchdog timers (independent, window)( t/ s3 E; Y" ^6 [* W$ f
1 x SysTick timer: 24-bit downcounter; l& D) _% G& D* }
2 x 16-bit basic timers3 k! O8 N% O* p$ x
1 x low-power timer
( n- D; m7 n/ \Calendar RTC with alarm, periodic wakeup from stop/standby
! {9 @2 T6 i, A; B- o3 pCommunication interfaces  m) u+ \% |, f; T5 p2 W7 ^
3 x FDCAN controller supporting flexible data rate
' K3 W" O, N1 z: @' ~4 x I2C Fast mode plus (1 Mbit/s) with 20 mA current sink, SMBus/PMBus, wakeup from stop4 k# x+ s/ f$ {/ l
5 x USART/UARTs (ISO 7816 interface, LIN, IrDA, modem control)
3 C+ a: _# |( O( I) `" `/ |1 x LPUART
* X. y# Z" r. u8 |4 ^4 z6 K4 x SPIs, 4 to 16 programmable bit frames, 2 x with multiplexed half duplex I2S interface% q; D, |9 [. W
1 x SAI (serial audio interface)
0 O6 K+ D0 \. B; V4 ZUSB 2.0 full-speed interface with LPM and BCD support" E) ]. S% x  D3 @) ~- L8 G3 T
IRTIM (infrared interface)7 j1 ~) X- g8 U; G& _( W
USB Type-C™ /USB power delivery controller (UCPD)
' I2 F) S2 s! S! W3 Q- K9 ?4 sTrue random number generator (RNG). |2 x/ I5 ?/ g- B% A: M* b
CRC calculation unit, 96-bit unique ID
. A2 ?- e0 ?* ~. iDevelopment support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™
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1 收藏 评论0 发布时间:2021-5-12 10:19

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