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STM32_深圳峰会_黑客松,奖品开箱

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ghost110 发布时间:2021-5-12 10:19
感谢管理“Seven”,因为工作原因不能实地参加STM32的深圳会议,在seven管理的热心组织下,通过线上直播让我了解了这一次的技术盛况,从开始的技术讲解到后期的竞赛直播,各个阶段都充分体现了专业性、素养性。不但使我学习了知识,同时也更好的了解了STM32的相关技术和使用场景,对我个人是一个很大的提升,在此对ST公司和seven管理再次表示感谢。
' I" X3 l: y3 }% {在黑客松的比赛中通过各个参赛队伍的作品,看到了不同的创意,产品技术是固定的,关键看人怎么使用。同样的平台,不同的思考方向,差异化的使用方法,打造出不同的产品方案。十分棒。在观看的过程中有幸获得抽奖奖品“STM32G474”,目前已经收到。谢谢。
1 T; B3 l2 H7 r5 b* W4 P希望以后的活动更加丰富,开发出更多的产品。* R# h) U& |) q. x2 `
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描述
& a- Y- K7 G2 X0 z  v$ HThe STM32G474xB/xC/xE devices are based on the high-performance Arm® Cortex®-M4 32-bit RISC core. They operate at a frequency of up to 170 MHz. The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all the Arm single-precision data-processing instructions and all the data types. It also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) which enhances the application’s security.# W5 y& [2 y% n+ u
These devices embed high-speed memories (512 Kbytes of Flash memory, and 128 Kbytes of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad SPI Flash memory interface, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix./ r& r, z" Z( |+ y
The devices also embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, securable memory area and proprietary code readout protection.
: e' M0 D" ?/ p5 X1 {The devices embed peripherals allowing mathematical/arithmetic function acceleration (CORDIC for trigonometric functions and FMAC unit for filter functions).
6 F, `$ z0 y* |They offer five fast 12-bit ADCs (5 Msps), seven comparators, six operational amplifiers, seven DAC channels (3 external and 4 internal), an internal voltage reference buffer, a low-power RTC, two general-purpose 32-bit timers, three 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and one 16-bit low-power timer, and high resolution timer with 184 ps resolution.
8 p% W' d" U6 v6 ZThey also feature standard and advanced communication interfaces such as:9 Z! g. l2 H" d4 ?' z$ M
所有功能8 g. o6 G8 K) B4 u3 [
Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 170 MHz with 213 DMIPS, MPU, DSP instructions
- K2 ~% I3 X7 b+ M" B5 Y: }8 F& v+ nOperating conditions:. ~& y9 T1 n: m# T; G0 t9 [
VDD, VDDA voltage range: 1.71 V to 3.6 V3 A6 G8 q$ ]' I* D' f' ?+ V% a! J
Mathematical hardware accelerators
  r. f9 ]; }, \CORDIC for trigonometric functions acceleration
5 V1 q2 G2 C, `" S' JFMAC: filter mathematical accelerator
  u0 _9 X4 [( Z4 @( DMemories8 z9 u* M. M8 j& ?% i0 Z
512 Kbytes of Flash memory with ECC support, two banks read-while-write, proprietary code readout protection (PCROP), securable memory area, 1 Kbyte OTP* v: W: F: e6 @. \# H* ]) M
96 Kbytes of SRAM, with hardware parity check implemented on the first 32 Kbytes& v) o2 ^2 q1 f  j6 E# ]
Routine booster: 32 Kbytes of SRAM on instruction and data bus, with hardware parity check (CCM SRAM)
# _1 n. D2 R, {External memory interface for static memories FSMC supporting SRAM, PSRAM, NOR and NAND memories
1 [7 {6 H6 ?  e/ n7 _Quad-SPI memory interface: C/ c# h5 o" G, g7 M6 Q7 C
Reset and supply management
' I1 D9 W, c2 {* K8 f; H0 E3 ~Power-on/power-down reset (POR/PDR/BOR)7 l& Z; }) G2 G/ k
Programmable voltage detector (PVD)
+ N' m% f0 o) u! x; zLow-power modes: sleep, stop, standby and shutdown
; I1 r- v' d* q( M" ^VBAT supply for RTC and backup registers3 g( K2 P, t+ p, D6 @4 t: d
Clock management& H1 I$ w1 f- i
4 to 48 MHz crystal oscillator
2 Y1 \' W8 b2 O. `. U0 S! e32 kHz oscillator with calibration
" _3 \5 r0 ~  e2 h- R: tInternal 16 MHz RC with PLL option (± 1%)
' c9 K; @5 q7 x# c+ `4 jInternal 32 kHz RC oscillator (± 5%)( A% V6 O( X: n- b6 Q' ~. E
Up to 107 fast I/Os
- {0 x" z2 K3 _$ \' D8 |All mappable on external interrupt vectors2 h. q- t, G% |3 u
Several I/Os with 5 V tolerant capability0 ]- C/ p2 F0 \
Interconnect matrix
2 F" W# y. c9 Z# Y16-channel DMA controller4 O/ u, @$ U4 J" f! Q
5 x 12-bit ADCs 0.25 µs, up to 42 channels. Resolution up to 16-bit with hardware oversampling, 0 to 3.6 V conversion range8 W* x' K0 F  Q
7 x 12-bit DAC channels! G- S) k- f: [
3 x buffered external channels 1 MSPS3 [( \9 S. ?  z0 V7 M
4 x unbuffered internal channels 15 MSPS
5 h( \/ p4 w; ?7 x ultra-fast rail-to-rail analog comparators
9 }+ j* ^4 e' _- n( _6 x operational amplifiers that can be used in PGA mode, all terminals accessible& f9 ~) K/ K) h( c" \( w1 j
Internal voltage reference buffer (VREFBUF) supporting three output voltages (2.048 V, 2.5 V, 2.95 V)3 g) H5 c' s7 u; m9 N) C
17 timers:5 h% F6 ?  {( _  U/ {# f* N. N  m
HRTIM (Hi-Resolution and complex waveform builder): 6 x16-bit counters, 184 ps resolution, 12 PWM
  t" e# p- E. Q2 x 32-bit timer and 2 x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input. N* S6 v/ X5 H* {6 O3 L
3 x 16-bit 8-channel advanced motor control timers, with up to 8 x PWM channels, dead time generation and emergency stop
, S& k$ U2 t1 P& W7 G: o1 x 16-bit timer with 2 x IC/OCs, one OCN/PWM, dead time generation and emergency stop0 g1 y; z8 G9 N! m
2 x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop& I& v5 _: ~3 |0 s9 l5 v
2 x watchdog timers (independent, window). _" d  I* w" }/ {2 Y, T; Q- i
1 x SysTick timer: 24-bit downcounter
- T9 ^3 Z& V9 ]$ V% M$ [2 x 16-bit basic timers
. Z/ `) x$ X6 r" r1 x low-power timer
) r4 V) \* f' ^$ g  x8 CCalendar RTC with alarm, periodic wakeup from stop/standby
$ D% n" n: y6 `/ H1 dCommunication interfaces0 i( [' h( N  ]6 ]
3 x FDCAN controller supporting flexible data rate' L( C9 _0 t. w1 P0 b- c
4 x I2C Fast mode plus (1 Mbit/s) with 20 mA current sink, SMBus/PMBus, wakeup from stop
/ {& K8 J# J; u: q' z5 x USART/UARTs (ISO 7816 interface, LIN, IrDA, modem control)8 z; l- k) P# W3 Q9 ^
1 x LPUART+ b( n' D2 b- Q6 w2 O( }- O
4 x SPIs, 4 to 16 programmable bit frames, 2 x with multiplexed half duplex I2S interface
$ o$ W, Y$ n% V  q& [4 a1 x SAI (serial audio interface)" `7 E5 n! j  [5 J2 b( e( l! E% T8 V3 S
USB 2.0 full-speed interface with LPM and BCD support
: {% ]8 m7 J7 L/ [  r0 KIRTIM (infrared interface)
$ m  H" u  J" a  i# OUSB Type-C™ /USB power delivery controller (UCPD)+ s, C1 l9 \" Y7 v/ P3 h9 M
True random number generator (RNG)4 n" G7 R1 h& j4 r* k2 _
CRC calculation unit, 96-bit unique ID
4 S+ s5 R( z% u# XDevelopment support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™
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赞 1 收藏 评论0 发布时间:2021-5-12 10:19

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