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STM32_深圳峰会_黑客松,奖品开箱

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ghost110 发布时间:2021-5-12 10:19
感谢管理“Seven”,因为工作原因不能实地参加STM32的深圳会议,在seven管理的热心组织下,通过线上直播让我了解了这一次的技术盛况,从开始的技术讲解到后期的竞赛直播,各个阶段都充分体现了专业性、素养性。不但使我学习了知识,同时也更好的了解了STM32的相关技术和使用场景,对我个人是一个很大的提升,在此对ST公司和seven管理再次表示感谢。! P0 z! O+ w% A' b
在黑客松的比赛中通过各个参赛队伍的作品,看到了不同的创意,产品技术是固定的,关键看人怎么使用。同样的平台,不同的思考方向,差异化的使用方法,打造出不同的产品方案。十分棒。在观看的过程中有幸获得抽奖奖品“STM32G474”,目前已经收到。谢谢。
' u" {# q- s8 j: A! Y希望以后的活动更加丰富,开发出更多的产品。4 m; H; |4 a5 R

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  z! p2 G8 c4 R4 z' t* \描述+ W7 f1 o* \5 t5 P+ J1 m: E" L
The STM32G474xB/xC/xE devices are based on the high-performance Arm® Cortex®-M4 32-bit RISC core. They operate at a frequency of up to 170 MHz. The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all the Arm single-precision data-processing instructions and all the data types. It also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) which enhances the application’s security.0 ^- T2 }* k$ M9 Q2 x3 G. b
These devices embed high-speed memories (512 Kbytes of Flash memory, and 128 Kbytes of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad SPI Flash memory interface, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix./ B% e8 `9 |, w/ w  ]  I, M6 B
The devices also embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, securable memory area and proprietary code readout protection.
- u0 |; T6 t* t- e( [, vThe devices embed peripherals allowing mathematical/arithmetic function acceleration (CORDIC for trigonometric functions and FMAC unit for filter functions).7 N# d1 w. Z, j1 P8 k# N
They offer five fast 12-bit ADCs (5 Msps), seven comparators, six operational amplifiers, seven DAC channels (3 external and 4 internal), an internal voltage reference buffer, a low-power RTC, two general-purpose 32-bit timers, three 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and one 16-bit low-power timer, and high resolution timer with 184 ps resolution.
4 X+ k; R" P: i$ Z7 @- iThey also feature standard and advanced communication interfaces such as:* |6 r; [. F9 \1 x* I( f( x
所有功能
# n2 E; }+ v: k" tCore: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 170 MHz with 213 DMIPS, MPU, DSP instructions
! [; O7 g: A) m5 m1 m' g* {, w2 ~Operating conditions:
* Y4 m5 H( q& y! v$ [& z5 zVDD, VDDA voltage range: 1.71 V to 3.6 V
; o5 [/ \* Q) K/ J' [! x+ M- tMathematical hardware accelerators% h: Z  @& J0 y4 e( f- K& d' s
CORDIC for trigonometric functions acceleration1 V: c3 S$ z6 D) F' y
FMAC: filter mathematical accelerator2 F1 T% O! \# q
Memories
5 m4 M' n* V" y" W5 V9 X512 Kbytes of Flash memory with ECC support, two banks read-while-write, proprietary code readout protection (PCROP), securable memory area, 1 Kbyte OTP! U$ w) N% E9 v) x* p
96 Kbytes of SRAM, with hardware parity check implemented on the first 32 Kbytes
1 W3 c% u! |1 _' N+ A  a; LRoutine booster: 32 Kbytes of SRAM on instruction and data bus, with hardware parity check (CCM SRAM)0 _) K6 S; ^/ P7 c/ N2 r
External memory interface for static memories FSMC supporting SRAM, PSRAM, NOR and NAND memories9 {' g5 {; T! I) l) x
Quad-SPI memory interface* q5 K$ s: F% t' t
Reset and supply management
( ]" o! X8 h- S  m2 yPower-on/power-down reset (POR/PDR/BOR)7 k% I( y/ R. [2 a6 Z4 y$ p! W
Programmable voltage detector (PVD)' g' \! t1 S0 _! H
Low-power modes: sleep, stop, standby and shutdown
( |% Q% w. s# n. G8 `- NVBAT supply for RTC and backup registers$ @; r3 u% J! F# e- h. J- b
Clock management
2 B- F2 X0 g' y) N  L4 R3 ^4 to 48 MHz crystal oscillator
7 X* d! \$ x( f32 kHz oscillator with calibration
3 E4 m: u$ f4 R. I+ P8 A: IInternal 16 MHz RC with PLL option (± 1%)% u4 v6 }7 ?0 A* e
Internal 32 kHz RC oscillator (± 5%)
3 R1 @5 J0 m2 Y/ q6 e1 S  VUp to 107 fast I/Os6 @/ D5 B& Q! O  s3 Q- n
All mappable on external interrupt vectors) g) B$ h& w% |" i
Several I/Os with 5 V tolerant capability8 e  F1 r- t  D- d
Interconnect matrix0 X- X. T( s$ F
16-channel DMA controller( H# V/ p7 I" m  M" _' k, B. y- Z
5 x 12-bit ADCs 0.25 µs, up to 42 channels. Resolution up to 16-bit with hardware oversampling, 0 to 3.6 V conversion range' J9 d2 i6 s* m/ S+ L4 G) K7 e7 b
7 x 12-bit DAC channels1 B5 m( t! l% o. J8 A! C
3 x buffered external channels 1 MSPS
* W9 L; f( `1 J4 c8 J# i4 x unbuffered internal channels 15 MSPS
3 f! Q3 `, D, I6 L( [9 N7 x ultra-fast rail-to-rail analog comparators
/ M# y/ Y: b1 E  {6 x operational amplifiers that can be used in PGA mode, all terminals accessible
* {* e* \/ P; o/ V% k+ |Internal voltage reference buffer (VREFBUF) supporting three output voltages (2.048 V, 2.5 V, 2.95 V)
8 a* p1 s) _0 F% V- L17 timers:& U6 w% A/ I. s
HRTIM (Hi-Resolution and complex waveform builder): 6 x16-bit counters, 184 ps resolution, 12 PWM
! I" n' s- u+ h+ m9 h- A2 x 32-bit timer and 2 x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input& C$ ?' D  J' k2 m; i4 x( S
3 x 16-bit 8-channel advanced motor control timers, with up to 8 x PWM channels, dead time generation and emergency stop
9 U! j3 T: B0 L7 G" G9 u1 x 16-bit timer with 2 x IC/OCs, one OCN/PWM, dead time generation and emergency stop. g+ d/ W; M4 b
2 x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop! d" O$ j3 F/ M" h- V* p# L( E: B
2 x watchdog timers (independent, window)
# g5 Z* h" S9 M- s! P0 i1 x SysTick timer: 24-bit downcounter
0 M' f6 [& `+ I+ w& f, ?2 x 16-bit basic timers
/ k: \4 V: M2 N# P+ X( c( |1 V1 x low-power timer
# J2 G  q" l- x) \& {' y: FCalendar RTC with alarm, periodic wakeup from stop/standby3 R! F; f6 c# A0 z7 i
Communication interfaces2 j) {0 b+ g+ l& X* Q
3 x FDCAN controller supporting flexible data rate
( w) @( v3 X: V% b  Y4 x I2C Fast mode plus (1 Mbit/s) with 20 mA current sink, SMBus/PMBus, wakeup from stop( q1 `) q, S6 I2 g* p4 C4 {! D3 S
5 x USART/UARTs (ISO 7816 interface, LIN, IrDA, modem control)1 L6 A- m5 Z- k# D
1 x LPUART
6 J2 ]2 p% \& m* i4 x SPIs, 4 to 16 programmable bit frames, 2 x with multiplexed half duplex I2S interface$ P4 P& z% b0 ~6 T6 q! a. H7 o! [$ h
1 x SAI (serial audio interface)9 l- t, L8 X' J
USB 2.0 full-speed interface with LPM and BCD support! c1 ^, {+ T- p7 Z( A- q
IRTIM (infrared interface)0 S' `2 Q% H! {2 _2 T7 K. q
USB Type-C™ /USB power delivery controller (UCPD)
! v$ y3 K4 P+ T5 v( a5 N- ITrue random number generator (RNG)  Q$ u  e3 [, \; l& K  i
CRC calculation unit, 96-bit unique ID
6 t2 S, |9 E; t7 UDevelopment support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™; g* L& W" J8 U9 ]
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1 收藏 评论0 发布时间:2021-5-12 10:19

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