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STM32_深圳峰会_黑客松,奖品开箱

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ghost110 发布时间:2021-5-12 10:19
感谢管理“Seven”,因为工作原因不能实地参加STM32的深圳会议,在seven管理的热心组织下,通过线上直播让我了解了这一次的技术盛况,从开始的技术讲解到后期的竞赛直播,各个阶段都充分体现了专业性、素养性。不但使我学习了知识,同时也更好的了解了STM32的相关技术和使用场景,对我个人是一个很大的提升,在此对ST公司和seven管理再次表示感谢。
# N7 a. m: ?% E2 p在黑客松的比赛中通过各个参赛队伍的作品,看到了不同的创意,产品技术是固定的,关键看人怎么使用。同样的平台,不同的思考方向,差异化的使用方法,打造出不同的产品方案。十分棒。在观看的过程中有幸获得抽奖奖品“STM32G474”,目前已经收到。谢谢。  D% d: G5 A) ?& i2 y' J
希望以后的活动更加丰富,开发出更多的产品。8 M9 {- t$ H7 \% ~* L. _2 W

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描述
+ v) z8 I6 t( }; c' AThe STM32G474xB/xC/xE devices are based on the high-performance Arm® Cortex®-M4 32-bit RISC core. They operate at a frequency of up to 170 MHz. The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all the Arm single-precision data-processing instructions and all the data types. It also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) which enhances the application’s security.
# v) H# l1 j& e; K. yThese devices embed high-speed memories (512 Kbytes of Flash memory, and 128 Kbytes of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad SPI Flash memory interface, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
* _  _1 k; f- _/ d& [& OThe devices also embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, securable memory area and proprietary code readout protection.' l* Q# Y/ z' p2 S8 w; E3 m
The devices embed peripherals allowing mathematical/arithmetic function acceleration (CORDIC for trigonometric functions and FMAC unit for filter functions).
" J# n! v/ \4 U# Y- o$ O: ?, IThey offer five fast 12-bit ADCs (5 Msps), seven comparators, six operational amplifiers, seven DAC channels (3 external and 4 internal), an internal voltage reference buffer, a low-power RTC, two general-purpose 32-bit timers, three 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and one 16-bit low-power timer, and high resolution timer with 184 ps resolution.
$ {$ B( g5 ^$ P( [9 Q1 I1 tThey also feature standard and advanced communication interfaces such as:
2 s2 N+ n0 _& T( ]9 e所有功能# I% x6 b; S2 d5 x4 l; |
Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 170 MHz with 213 DMIPS, MPU, DSP instructions/ V% z! m3 g( f2 [: V
Operating conditions:  x* e3 Q# f1 Y4 p1 H
VDD, VDDA voltage range: 1.71 V to 3.6 V
+ t2 j! I. `3 A; C# pMathematical hardware accelerators; c; ^7 {  }' M# k$ U+ J
CORDIC for trigonometric functions acceleration
' P9 y: A" h* H0 t$ Z& l, ]8 h2 j9 SFMAC: filter mathematical accelerator
8 B6 W% b6 l6 _. NMemories- X7 {8 Y! y# f; z
512 Kbytes of Flash memory with ECC support, two banks read-while-write, proprietary code readout protection (PCROP), securable memory area, 1 Kbyte OTP+ [( _/ }, b- }; C4 w
96 Kbytes of SRAM, with hardware parity check implemented on the first 32 Kbytes6 Z8 o8 P# |# J; k) k0 R
Routine booster: 32 Kbytes of SRAM on instruction and data bus, with hardware parity check (CCM SRAM)1 U$ w; l. O  {" W
External memory interface for static memories FSMC supporting SRAM, PSRAM, NOR and NAND memories1 y) r' Z; }7 S* y! Y
Quad-SPI memory interface
' h: ^! d8 a5 f, _$ a) L/ P$ |) OReset and supply management
3 f% J, g  d2 R" Z. M, hPower-on/power-down reset (POR/PDR/BOR)
) q. q4 J& I1 M8 DProgrammable voltage detector (PVD)& G4 x+ B' d( a
Low-power modes: sleep, stop, standby and shutdown! v3 T( N+ R0 W: _4 J
VBAT supply for RTC and backup registers
+ l6 Y; i* Y: x5 |8 }9 cClock management; R2 x% O. o  W: I$ B
4 to 48 MHz crystal oscillator  C  d. x/ P. M- l* i
32 kHz oscillator with calibration) Q0 k7 T: \& k
Internal 16 MHz RC with PLL option (± 1%)" W% q% q; r' W9 e
Internal 32 kHz RC oscillator (± 5%)
9 i& W/ v8 _# y; yUp to 107 fast I/Os
. C# x$ b; Z. R' S) ]- ZAll mappable on external interrupt vectors
$ C2 h$ d1 E$ MSeveral I/Os with 5 V tolerant capability1 h, N' h( b# X3 p) x
Interconnect matrix
; R5 ]$ m( z/ K6 f16-channel DMA controller) j/ c- G" R9 f" h& C
5 x 12-bit ADCs 0.25 µs, up to 42 channels. Resolution up to 16-bit with hardware oversampling, 0 to 3.6 V conversion range
4 X6 I% V! l" n3 I. t! d9 n7 x 12-bit DAC channels
$ a) j" Q) U! A# n' d( g3 x buffered external channels 1 MSPS
3 Q/ h9 U5 p: D4 x unbuffered internal channels 15 MSPS
! p- x, m, `+ Q3 d7 x ultra-fast rail-to-rail analog comparators2 x8 a$ U' d9 L) Z$ Z. f/ Z
6 x operational amplifiers that can be used in PGA mode, all terminals accessible" X% p5 p% z2 p' L9 W+ u, a
Internal voltage reference buffer (VREFBUF) supporting three output voltages (2.048 V, 2.5 V, 2.95 V)
5 f+ l, L+ N: h. F& k17 timers:  n+ B! ], d9 d" A' a3 P
HRTIM (Hi-Resolution and complex waveform builder): 6 x16-bit counters, 184 ps resolution, 12 PWM2 J9 V( E7 Q5 w; e: F/ W& |0 U5 G
2 x 32-bit timer and 2 x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
1 R6 `2 s7 w. |/ p3 x 16-bit 8-channel advanced motor control timers, with up to 8 x PWM channels, dead time generation and emergency stop5 O/ P, e( x2 d  c
1 x 16-bit timer with 2 x IC/OCs, one OCN/PWM, dead time generation and emergency stop1 ^. i& ]  \" K
2 x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop
% P4 J+ Y3 U0 n# M4 z/ W( I2 x watchdog timers (independent, window)
. V' w. H8 X* s) B1 x SysTick timer: 24-bit downcounter
" K. n$ i+ x8 ?( j+ M* r2 x 16-bit basic timers
) Y  G( v5 j! _( }# O4 V; c1 x low-power timer4 l% t" j& [7 A6 y/ x* M
Calendar RTC with alarm, periodic wakeup from stop/standby7 ?; ^! z/ J7 Q/ K; N1 M& I
Communication interfaces
! J9 x& b: Q( B' Y3 x FDCAN controller supporting flexible data rate
! g- v: |+ ^" r; F/ L  U4 o* ^: Q4 x I2C Fast mode plus (1 Mbit/s) with 20 mA current sink, SMBus/PMBus, wakeup from stop
7 m" t1 ?. u/ i5 x USART/UARTs (ISO 7816 interface, LIN, IrDA, modem control)+ X5 v, _& \' [/ \; U: o
1 x LPUART$ r3 C) _5 ?) o7 T) Z
4 x SPIs, 4 to 16 programmable bit frames, 2 x with multiplexed half duplex I2S interface
/ p1 @6 U! l) y( p* n1 x SAI (serial audio interface)
0 H' f3 F$ Q( `USB 2.0 full-speed interface with LPM and BCD support
2 q( W. b7 [, T3 i3 @9 qIRTIM (infrared interface); O! g  l( F7 j5 ^5 u
USB Type-C™ /USB power delivery controller (UCPD)
& p/ K& C0 |5 N! ]9 wTrue random number generator (RNG)% [: w5 _7 a; z* K
CRC calculation unit, 96-bit unique ID8 L' I2 J0 y- B. @) L$ G4 s, U) k
Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™
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1 收藏 评论0 发布时间:2021-5-12 10:19

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