01. 概述8 z" C1 H! V0 J/ V
CM4 内核支持 256 个中断，其中包含了 16 个内核中断和 240 个外部中断，并且具有256 级的可编程中断设置。但 STM32F4 并没有使用 CM4 内核的全部东西，而是只用了它的一部分。
: t1 s+ C4 L( `( ]
; Q1 y# G2 d" g( ]STM32F40xx/STM32F41xx 总共有 92 个中断，STM32F42xx/STM32F43xx 则总共有 96 个中断，STM32F40xx/STM32F41xx 的 92 个中断里面，包括 10 个内核中断和 82 个可屏蔽中断，具有16级可编程的中断优先级，而我们常用的就是这82个可屏蔽中断。# w- A6 N8 Z# f. T- D* a8 _
9 ? s$ f% X+ b y0 e5 f- b
02. 结构体声明7 _! P( s7 B/ b2 U6 _; Z$ A
core_cm4.h文件中
5 c2 W% u) N$ d8 M& |
) R" O( K7 K: `. `# |, G& o- /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
0 k. A, h, X3 ~0 R - */2 M& ?& l5 ^' E# U" I: h
- typedef struct
9 u2 T/ j0 g* ` B0 r8 F - {% m& B! x0 T4 c0 X& D4 Q( R- j* V
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */+ O% z' x6 A& d* o! J
- uint32_t RESERVED0[24];
0 V0 O2 Y+ I6 z# W* M3 T% \5 o. c - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */" J' t, @7 \% U. }
- uint32_t RSERVED1[24];
: M$ l! B% m9 x! i, z - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- n3 a: C1 [4 @) d* N4 t - uint32_t RESERVED2[24];: | d. y& ]5 T/ i7 v; }; Z! N
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ Y2 Q% f# F" c0 h3 k/ I
- uint32_t RESERVED3[24];$ ?& W# r% S( N
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */4 z7 v: O7 s. ~6 ?" V
- uint32_t RESERVED4[56];- U# X% t/ }# W6 S* H+ ?
- __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */0 e+ T, q5 c# `2 O! i5 p& Q2 P$ b7 l" i9 E
- uint32_t RESERVED5[644];
+ w: S* t: C( { - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */- i2 O B+ S% o: E3 }6 y
- } NVIC_Type;
8 T r, h/ ?4 i; FSTM32F4 的中断在这些寄存器的控制下有序的执行的。只有了解这些中断寄存器，才能方便的使用 STM32F4 的中断。
8 i$ |/ z9 p* h3 v. q; R
" G* `. l; X7 D5 g a- i! DISER[8]：ISER 全称是：Interrupt Set-Enable Registers，这是一个中断使能寄存器组。上面说了 CM4 内核支持 256 个中断，这里用 8 个 32 位寄存器来控制，每个位控制一个中断。但是STM32F4 的可屏蔽中断最多只有 82 个，所以对我们来说，有用的就是三个（ISER[0~2]），总共可以表示 96 个中断。而 STM32F4 只用了其中的前 82 个。ISER[0]的 bit0~31 分别对应中断0~31；ISER[1]的 bit0~32 对应中断 32~63；ISER[2]的 bit0~17 对应中断 64~81；这样总共 82 个中断就分别对应上了。你要使能某个中断，必须设置相应的 ISER 位为 1，使该中断被使能(这里仅仅是使能，还要配合中断分组、屏蔽、IO 口映射等设置才算是一个完整的中断设置)。具体每一位对应哪个中断，请参考 stm32f4xx.h 里面的第 188 行处。
r- Q5 N0 H9 C3 Q' f
4 V" f/ G" K' c# {7 Y" t+ M/ `1 hICER[8]：全称是：Interrupt Clear-Enable Registers，是一个中断除能寄存器组。该寄存器组与 ISER 的作用恰好相反，是用来清除某个中断的使能的。其对应位的功能，也和 ICER 一样。这里要专门设置一个 ICER 来清除中断位，而不是向 ISER 写 0 来清除，是因为 NVIC 的这些寄存器都是写 1 有效的，写 0 是无效的。
9 z: K% i+ y a# [& X8 p+ Q" K$ h) e" } e! }- F" {
ISPR[8]：全称是：Interrupt Set-Pending Registers，是一个中断挂起控制寄存器组。每个位对应的中断和 ISER 是一样的。通过置 1，可以将正在进行的中断挂起，而执行同级或更高级别的中断。写 0 是无效的。
" S, w" o! i: V, |% Z) ?/ {
/ z7 K+ L) C1 |: ZICPR[8]：全称是：Interrupt Clear-Pending Registers，是一个中断解挂控制寄存器组。其作用与 ISPR 相反，对应位也和 ISER 是一样的。通过设置 1，可以将挂起的中断接挂。写 0 无效。3 B: [' L) Y# m2 e
1 d6 K3 F: e' o, j' M# X3 B$ M9 _IABR[8]：全称是：Interrupt Active Bit Registers，是一个中断激活标志位寄存器组。对应位所代表的中断和 ISER 一样，如果为 1，则表示该位所对应的中断正在被执行。这是一个只读寄存器，通过它可以知道当前在执行的中断是哪一个。在中断执行完了由硬件自动清零。5 Q! T; d% W3 E" e- f
0 y: P2 O* x8 H& x: @IP[240]：全称是：Interrupt Priority Registers，是一个中断优先级控制的寄存器组。这个寄存器组相当重要！STM32F4 的中断分组与这个寄存器组密切相关。IP 寄存器组由 240 个 8bit的寄存器组成，每个可屏蔽中断占用 8bit，这样总共可以表示 240 个可屏蔽中断。而 STM32F4只用到了其中的 82 个。IP[81]~IP[0]分别对应中断 81~0。而每个可屏蔽中断占用的 8bit 并没有全部使用，而是只用了高 4 位。这 4 位，又分为抢占优先级和响应优先级。抢占优先级在前，响应优先级在后。而这两个优先级各占几个位又要根据 SCB->AIRCR 中的中断分组设置来决定。 S$ y/ W9 J9 b( B- H5 `
8 g- K6 ~. w9 p5 A: x9 Q
03. 中断分组
8 w5 l) H# n, z0 `- D GSTM32F4 将中断分为 5 个组，组 0~4。该分组的设置是由 SCB->AIRCR 寄存器的 bit10~8 来定义的。
6 F; n9 @1 y0 E8 b9 c6 E5 e
6 }* A" C* a5 L) p! D: S4 i |& v
" s" [# ]4 q% Z* a7 B* `* g* `- D9 a& O5 Z3 b
我们就可以清楚的看到组 0~4 对应的配置关系，例如组设置为 3，那么此时所有的 82 个中断，每个中断的中断优先寄存器的高四位中的最高 3 位是抢占优先级，低 1 位是响应优先级。每个中断，你可以设置抢占优先级为 0~7，响应优先级为 1 或 0。抢占优先级的级别高于响应优先级。而数值越小所代表的优先级就越高。
. B( @- E, K) I+ ^" s; w5 m$ Z1 W. v! m
这里需要注意两点：第一，如果两个中断的抢占优先级和响应优先级都是一样的话，则看哪个中断先发生就先执行；第二，高优先级的抢占优先级是可以打断正在进行的低抢占优先级中断的。而抢占优先级相同的中断，高优先级的响应优先级不可以打断低响应优先级的中断。
- L+ N8 c1 X0 V; |3 V
# Z9 i. c7 N0 P" f) ^5 B/ w0 [结合实例说明一下：假定设置中断优先级组为 2，然后设置中断 3(RTC_WKUP 中断)的抢占优先级为 2，响应优先级为 1。中断 6（外部中断 0）的抢占优先级为 3，响应优先级为 0。中断 7（外部中断 1）的抢占优先级为 2，响应优先级为 0。那么这 3 个中断的优先级顺序为：中断 7>中断 3>中断 6。
3 _8 v' s3 \2 ^9 y8 Q- p5 H- v) l f! V- a8 T. S" k
上面例子中的中断 3 和中断 7 都可以打断中断 6 的中断。而中断 7 和中断 3 却不可以相互打断！
: o. D6 r9 T0 ~' t2 T6 Q. O1 l: J1 ?1 E
04. 相关类型( o9 _3 ^$ N' r: }7 `0 s" E8 N: u
misc.h文件4 W$ V# i$ r6 F
; M2 Q7 Z' }; m% X, SNVIC_InitTypeDef类型7 S! T+ G# _$ P+ v/ t+ H
2 P, o3 h! x* R- v
- /**
& o4 O9 B: P: U" y - * @brief NVIC Init Structure definition ( o5 u2 f: H: T5 f* l5 ~# L1 R
- */1 C- H* B; T. v6 ~9 T4 Y% V4 {4 `
- * J$ E! `9 Y! x
- typedef struct" B3 T. i+ J1 @) r6 A2 p8 D
- {
% y: q! o7 Z$ f6 R5 s! @% a& `/ U - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled./ y2 c2 s e# C9 y7 B
- This parameter can be an enumerator of @ref IRQn_Type 5 W7 o& { k: ^! {! N
- enumeration (For the complete STM32 Devices IRQ Channels5 X. n& ~( T* o0 }
- list, please refer to stm32f4xx.h file) */( {& O1 z, A( x0 W/ j
- + g' `4 L0 \/ D. H2 V7 R5 V
- uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
T" X; d$ j- E - specified in NVIC_IRQChannel. This parameter can be a value/ a: S w& k6 O" g$ k; ?% z
- between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
8 i8 E1 ]# k* j0 x, S* \ - A lower priority value indicates a higher priority */
& l+ I# a$ p2 {) y+ s ]. _# |4 i
3 |! r) g, G3 Y' s- uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
7 e- o3 n8 v1 z! m. J - in NVIC_IRQChannel. This parameter can be a value, M# t4 V; e+ u* r) o4 U' u# f
- between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
( T! \4 ~8 Q, u$ q* O4 A - A lower priority value indicates a higher priority */8 Y2 w/ b4 u0 I( w& ?5 I
- 5 E/ z5 k# K: f
- FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel+ l' I6 G/ d1 x4 l* a" P( I; [
- will be enabled or disabled.
. t: U, p, j t5 m D, \7 r - This parameter can be set either to ENABLE or DISABLE */
. S9 c C j# ` - } NVIC_InitTypeDef;
MISC_Vector_Table_Base- /** @defgroup MISC_Vector_Table_Base
2 n7 o3 E5 B: m! |6 M- F: z+ t( V a - * @{
7 `; v ~3 j5 g6 U" \8 v - */
# U$ j6 S1 N8 J - 6 R8 U" j5 L+ J( {0 ^/ ?- M
- #define NVIC_VectTab_RAM ((uint32_t)0x20000000)
: h0 C* I P! B+ g6 { - #define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
$ R+ m7 u! w; m+ r" {, o - #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \0 h) [9 O9 o" v; f
- ((VECTTAB) == NVIC_VectTab_FLASH))
MISC_System_Low_Power5 ^( u$ m: H5 g$ f2 V
- q( R- H! H, J, G) a! G5 T
- /** @defgroup MISC_System_Low_Power
+ t, A4 q( T% V( P" \0 Z - * @{
* ? p8 s8 b3 b! r: {' V" h3 Q! b - */
7 X I$ w" q: u& u+ d( [ - - k4 h+ ]" _( B" z! D! Y0 \" U$ ^
- #define NVIC_LP_SEVONPEND ((uint8_t)0x10)
" I ] g% s( ], T* P& F$ J9 O- h( T - #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
" W$ w4 G$ h, Q( _% u) p" m _; D - #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)" d9 }# x0 K& X* Y9 ]+ w: k, \3 H
- #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \5 J/ I. Y) P3 `1 p0 q
- ((LP) == NVIC_LP_SLEEPDEEP) || \4 O e- S( y4 k x2 |
- ((LP) == NVIC_LP_SLEEPONEXIT))
MISC_Preemption_Priority_Group% d8 `6 f9 g6 b2 K& Z
5 z# @8 m; _; Z7 O- /** @defgroup MISC_Preemption_Priority_Group
" ?! k% L9 ^# U5 j* o+ ^8 @( k - * @{
: h: N4 `# z L8 l) `. v - */- f' }4 b% s5 R! y2 \% R: ^
+ G8 h1 y# ~- G7 I! i/ j$ x- #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
$ G" ^( D+ h; P: o ~: ] - 4 bits for subpriority */
+ q' U2 g6 @: t' l - #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority) j, M# _0 E) n3 ~. ]2 N3 ~# F
- 3 bits for subpriority */
0 h- D. k6 _' n, ]* `4 C - #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority& w& W, }; J7 K1 Q) g
- 2 bits for subpriority */
) l6 c7 W* S' q2 H - #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority. T3 w. H1 X1 |+ W( L
- 1 bits for subpriority */
) _. B" Y! _- j - #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority- h. t! V; e$ K* G* {! _
- 0 bits for subpriority */3 A# z: q: ^) f( E2 n8 U. N
- 5 J$ @* }% B3 y4 c1 D
- #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \0 r1 R, t3 Z1 E1 B
- ((GROUP) == NVIC_PriorityGroup_1) || \
, s4 ]* c& j l2 }+ d3 S - ((GROUP) == NVIC_PriorityGroup_2) || \0 p3 Q8 r4 z* K' ?/ l: u' z) f
- ((GROUP) == NVIC_PriorityGroup_3) || \
) K# @) p( b7 A! f - ((GROUP) == NVIC_PriorityGroup_4))
1 F8 c/ F0 A6 a4 R7 }- y - 0 u" ?9 T# O6 ^ g) W; J
- #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)# V" J" j6 j4 O2 p2 `
- ( E( P1 e+ ?* b1 X, X
- #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
% K+ x3 p5 r$ l* |& P4 a r - . }1 F! o7 `3 I1 M' g
- #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
$ ]- I' C, C* L( `$ h" _ \MISC_SysTick_clock_sourc
8 Q; Q& G1 P P) r, _) ~6 ?8 Y8 p/ g" o
- /** @defgroup MISC_SysTick_clock_source # U, G; s( `4 T9 x" I
- * @{
: ]; L2 {( g+ M& l1 a - */
3 I9 @1 ^# z$ h# y, ^
9 L1 ^' x- `. w9 u- #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
# Q4 t, a5 E" x( g - #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)2 E4 A/ Q' ^! N+ F! p) ^" u
- #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
9 [4 ]5 u7 [4 v4 K& h+ Q - ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
7 m/ s$ ?( W, M% ~. O
- ~* A4 e* F/ J中断名字(stm32f4xx.h)5 w+ N0 X% w2 n+ x% O8 ]+ X
; C8 t6 P* m) ]- m9 w$ ~& T- /**2 T+ T' K4 W3 j J( }) Z
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device
6 q, y1 q% ?& |$ Q0 k - * in @ref Library_configuration_section
' l4 ?$ S* m* K9 r - */' M3 }+ W) ^- C% _% ^7 S
- typedef enum IRQn( e. p( h6 I; Y# M- j
- {% E5 T5 G7 |) M: s
- /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
: L; S& c9 T+ U) C, u - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */" f* G( ~$ L; s% q+ W) U# j6 A+ r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
# K) v4 j8 ^' N. N Z: r1 E( b( Z - BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
, x! T2 k- B+ j* [2 z$ I3 g8 c1 ]0 |, F - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */7 z' j+ c) O" S/ A
- SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
: P0 x) ~" v6 T! I4 ] - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */0 L* P$ ]9 Z, J
- PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */3 i7 y: w2 v- J8 j
- SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */) d- \2 [. u. j' D4 {7 n
- /****** STM32 specific Interrupt Numbers **********************************************************************/
: Y+ r* P' X) c# l2 C% p - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
8 p$ @/ v- v/ ^: U; k! l3 Y - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */" A" C) Y0 }5 B8 g
- TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */! @ C2 U4 i1 |; I. W8 o
- RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */) }7 k) | u7 l/ K, E$ U1 ~
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */' d* s+ W2 h2 q9 i/ f& o2 E! Q/ Q
- RCC_IRQn = 5, /*!< RCC global Interrupt */3 @5 ~+ z" Y C( j" w9 Z
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */3 Q/ L) l3 w7 a4 C+ f
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */! M* t2 [ {8 z
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
; ~* Y) Z. o6 ?$ |" G' H- E2 ] - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */5 {5 B9 T, r3 K& m$ [6 o4 g
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */; W6 J+ C: m* u
- DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt *// E' I7 A0 T9 t, e: w. q6 d! [. B
- DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
b6 E$ @ }2 k$ e G% |( w - DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
- {* x% i p# H! b - DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
8 A) b4 P* w3 t8 G! ~* { - DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */# ^7 H* g7 I1 j9 t9 X$ j
- DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ `) D$ s: v% ]* \4 W9 }
- DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
. t! k# c% u/ _7 M5 w - ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */2 E/ ]% I1 L+ S* _ v
- , l% c* A4 a! \( w/ J
- #if defined(STM32F40_41xxx)
3 X/ _4 N; l, R. P% V* r. @4 D. ` - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
1 ~* A* g5 `$ V - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */! M1 \# q! E& _* O( p! o4 P
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
/ a" d6 G0 u5 F+ X1 ` - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
9 `* U& G5 ^! ~; R2 c3 ], p - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
" u1 c$ D2 J$ Q7 S! b2 W- [+ P3 A - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */4 R' V" T) E; y5 y: a( g
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
$ n) ?7 p& _4 a1 R" S+ j3 b - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */' t' a A2 ~3 [0 J! n) e* v
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */- D# m+ y) b5 ]& r& I+ w
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */8 w$ r& Q) M' V5 y& w S. w
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
( F" F' E8 F$ X; V; V# D3 b - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ t6 F3 W7 |3 R8 B5 v - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
$ N; ^* k- l' S; r% z" U, w0 K - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */1 v5 M5 [) m1 b; j \* a, U4 _9 ^0 [
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
/ r U; [5 x) ^/ B! m - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */$ W0 s- r- _6 o
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
: z' R# w( Z2 O$ X" I! N9 ] - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
3 Q" a- c6 u& F% j5 O, ?. z I - USART1_IRQn = 37, /*!< USART1 global Interrupt */! p. _) B3 O5 s" ~/ u2 `- ~" o+ P
- USART2_IRQn = 38, /*!< USART2 global Interrupt */8 b+ d. {+ F/ M8 [
- USART3_IRQn = 39, /*!< USART3 global Interrupt */: c# q1 G9 u1 T# Z
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
' Z/ f ]' |- Z: R+ h' A) q2 g - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
: X6 y7 M! j4 t+ w% y' n! m1 ?2 R - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */8 E/ d& [0 Q% k4 l5 I& i6 G
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
; i5 V6 H* D8 ~0 F- o/ Z M - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
0 l. m+ b) Z/ _, H- _ | - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */$ X0 j; f# ]2 }# q1 K
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */1 [1 m# o6 j9 {! m+ J! j; h- O! B
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ o, s2 N: ?+ R0 ?1 E3 Q
- FSMC_IRQn = 48, /*!< FSMC global Interrupt */. |- K+ V8 [! J) |8 k. T- n" w9 |
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
( f7 M% R' o' k6 g4 f6 c$ e - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */. m [- h' s' A6 R1 f, O: j: w7 r
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
5 c4 }5 d2 D; H8 {6 A& U - UART4_IRQn = 52, /*!< UART4 global Interrupt */
% ?$ s' d) ]$ t& n" j- T* E6 x - UART5_IRQn = 53, /*!< UART5 global Interrupt */% v3 b/ j* }5 T, Y6 n: v
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
) }$ I/ C9 H+ E. M' X3 N; T8 N; v - TIM7_IRQn = 55, /*!< TIM7 global interrupt */
" |# H5 B7 J6 C7 u) v0 G m - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */2 s1 @' g0 L* P( }
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */* `! p+ b% V, d% o/ `
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
7 u; W2 p- r+ K/ B" _ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */1 d4 r; w$ y @& N
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
/ p$ D- c% }2 c: @: d& c - ETH_IRQn = 61, /*!< Ethernet global Interrupt */
; o0 ^/ C. G+ Y# J& D0 J - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */- _8 a J+ [. P
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
; q2 }6 P% O/ V' _0 P: y, A6 r - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */% C8 D# i1 n. h' _. }* d
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
. R* O; S3 I( y$ N - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */* r( e, s3 {% X; @$ l9 j H
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
7 y$ ^( r3 u0 r - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
9 \: M8 Y: ?3 M+ O% u9 w7 B - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
* r) b o- C. K - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */3 Z1 a8 o* n% U9 P- d! y* U+ R
- USART6_IRQn = 71, /*!< USART6 global interrupt */
9 D, D! K6 m" u- N& k- ? - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
6 ~+ V# @( m5 s, {7 E3 v - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */* e" }5 {( [; S: M
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */8 u: Z' O% w5 ` y9 A, Z6 B
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */8 T; U1 p4 T* z; E( M# v
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */( l9 R2 v6 O4 _" k/ ~4 v
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */, y ]) Q% x, ?* I
- DCMI_IRQn = 78, /*!< DCMI global interrupt */4 j- A& [. l6 K/ t9 \+ e" {
- CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */. M' F/ j: [0 D6 F. [
- HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
) ]5 R$ Y8 s- s, N: j6 i/ ?7 d - FPU_IRQn = 81 /*!< FPU global interrupt */0 S9 _9 l+ J; f- R
- #endif /* STM32F40_41xxx */
2 h+ Q) Q" t/ G9 [; [. x05. 相关函数
, `) Y7 H/ K6 s7 W8 i. ~* c" X- /* Exported macro ------------------------------------------------------------*/1 u% O# i5 x0 L9 N# A
- /* Exported functions --------------------------------------------------------*/
0 z& `+ k5 ^+ [# H
# _; s' X( B, [8 m- void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);( f3 S# K8 y2 v+ l- s
- void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);3 X+ a8 ]% n8 l
- void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);! E8 V! k; J0 v2 z0 ?0 }1 y" V# [
- void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
6 A0 z M. o0 E& v. T2 I7 o% I; t# T - void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+ H9 Y3 V- i: k s! { J( I: x* Q$ C
|
.png)
STMCU小助手
发布时间：2022-4-1 15:20
微信公众号
手机版
