【经验分享】STM32 定时器相关函数和类型

STMCU小助手 · 2022-06-13T09:40:04+00:00

01. TIM概述0 P6 {1 N; [5 z% a: } stm32f4xx_tim.h和stm32f4xx_tim.c文件中 * M9 x8 Y8 {! V8 y5 G' \/ q. r% {( x7 M 02. 相关类型1 x/ }: Z; [" a/ u* n TIM_TimeBaseInitTypeDef b0 f0 C) P. n7 u8 @& R: V1 ~& [0 q% u 4 b8 {9 M3 V8 t) r& V/ }/** % m1 [. W2 }5 Y# S/ |2 E: Z0 r9 {3 u * @brief TIM Time Base Init structure definition 7 J0 L! v4 \; e * @note This structure is used with all TIMx except for TIM6 and TIM7. * g* u2 f) T% P */3 v2 E* j8 s; } . W. I) X: q" @- x0 B, J" g typedef struct ' N0 S3 F2 S0 L) b0 g" J& s8 I* {{ 4 F( U8 c) O) ~ uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. j# s/ ?2 X2 j' m5 O This parameter can be a number between 0x0000 and 0xFFFF */) l: U3 e. G4 H; o , w7 o! w+ G$ a" w; K# U s2 s uint16_t TIM_CounterMode; /*!< Specifies the counter mode.# P* j# ~2 @: J: }5 \" G; ? This parameter can be a value of @ref TIM_Counter_Mode */ 0 |. {4 f% }7 U6 g; I# Z * M& O" A' {3 n6 Q: d& y4 s8 b uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active 5 q9 X, F' g+ n6 u% V' a) L* O; p Auto-Reload Register at the next update event. + i3 w# B0 u% @) @% z: f" e This parameter must be a number between 0x0000 and 0xFFFF. */ + X( C* m* e- f5 ^, N# q 7 R1 _& E8 @! g uint16_t TIM_ClockDivision; /*!< Specifies the clock division.1 Q1 L3 P- o& V! L( P+ i5 l This parameter can be a value of @ref TIM_Clock_Division_CKD */2 Z) ]! U7 L1 }2 h " A5 L4 o5 n- Z4 [) M7 ~( }: d9 a uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter$ ]3 F8 `7 S3 H1 ^8 P3 T3 z' g reaches zero, an update event is generated and counting restarts k! g- j( f% s8 T4 n- Z from the RCR value (N).4 B6 R) m3 I3 ?& k0 h This means in PWM mode that (N+1) corresponds to:# V) [" y! i+ ]6 E - the number of PWM periods in edge-aligned mode 7 L) n% d ~+ d) X- s% T4 B - the number of half PWM period in center-aligned mode9 N v0 S, z7 o7 r! C1 b This parameter must be a number between 0x00 and 0xFF. 9 O7 F- r" J; B @note This parameter is valid only for TIM1 and TIM8. */7 i4 y% y; R$ G+ J } TIM_TimeBaseInitTypeDef; 复制代码 9 O0 p" r; D6 ~TIM_OCInitTypeDef! K- O7 P7 p. s( E' t4 b! `3 w + W2 j1 |0 N8 p7 q0 h3 C( u! Z. X /** 4 T7 o8 I& @# @6 H * @brief TIM Output Compare Init structure definition ( u, W! V) ]/ o3 x, X: s */+ c& U" \1 E/ @8 u. G* m9 S $ n( L# x/ r/ p: `6 [5 h+ T) Ctypedef struct . W* Z7 q9 O$ z) g( D{6 \/ ~. X0 T' Z6 h G2 l4 v uint16_t TIM_OCMode; /*!< Specifies the TIM mode., q6 N: O+ V$ c7 t This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */) t0 ? N% P; u) c$ p # e+ O5 Q) j; J2 }6 T7 X1 ] uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. 9 @+ Q1 F& o. M$ l/ | This parameter can be a value of @ref TIM_Output_Compare_State */* {) D5 A1 ]9 ]6 [2 ]" k % E$ v& }, g* E5 |4 R' H uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. + `3 a- S1 X3 p" o) j6 J% i This parameter can be a value of @ref TIM_Output_Compare_N_State 8 g1 R& M2 O! ^& X: K @note This parameter is valid only for TIM1 and TIM8. */- {8 k6 |% l& T4 O' e4 V - m8 O' {3 _4 z& ]3 w2 T$ E6 u uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + |' ^! Y/ ]& F$ u8 P" S This parameter can be a number between 0x0000 and 0xFFFF */ 2 j+ a* C* a! Z3 i1 l/ D4 @ # ?- C) B; S( } V( P' w uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.4 {- a7 Q: `- z7 X5 ~ This parameter can be a value of @ref TIM_Output_Compare_Polarity */* g5 {! v" \4 ^0 P8 F* A+ r, K ' j7 l! }3 |: Q1 w% A- M uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. ( G% ^: @; V' |9 {0 c% P This parameter can be a value of @ref TIM_Output_Compare_N_Polarity " S: X1 @" B! D0 F6 n, p; ^/ C @note This parameter is valid only for TIM1 and TIM8. */" B) u6 _ s% G1 `' v/ O, Q3 P ) `' f7 o! U% W, t2 V uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 1 n( ?$ p7 q7 `+ u2 z* N This parameter can be a value of @ref TIM_Output_Compare_Idle_State, x# [4 m$ i) [6 B, j7 z0 y9 L* Y5 N @note This parameter is valid only for TIM1 and TIM8. */4 I s3 {! Z5 C& I# U 7 i E' L7 l/ W# C uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. % J7 y h) j- c9 ] This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State9 D+ w# c3 H/ ]1 s* r @note This parameter is valid only for TIM1 and TIM8. */ ! s+ ]% t) c. ^) Q, `; J} TIM_OCInitTypeDef;复制代码# o S. f: f- p6 h9 ^( y& E& W' O TIM_ICInitTypeDef1 I( V9 A! O9 U7 U 1 y2 i4 G+ H* b# O ~ /** 1 w% O$ y0 U# O' l' w. Q" H) t, t * @brief TIM Input Capture Init structure definition % M7 d2 l% w! ~) o# s/ q */ 5 i" F5 l, N) t! T/ p # n9 W2 m0 O5 e$ L# htypedef struct ; e3 p* h7 p$ F. A6 S* v{; e: \# ]2 X/ O% o 7 W- N5 J, R8 w3 E, [& d" E3 B: V5 { uint16_t TIM_Channel; /*!< Specifies the TIM channel. 3 U7 g J1 K( s9 C" c+ Z This parameter can be a value of @ref TIM_Channel */2 {: Y/ C8 Q2 c( a7 r 3 y) v+ q# u+ B$ l7 W3 L1 H% J) ^3 \3 T uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal./ J8 C$ X) i6 n* x r$ y" X This parameter can be a value of @ref TIM_Input_Capture_Polarity */9 O K( f; G+ d; w# o - V/ M M: t+ X# O uint16_t TIM_ICSelection; /*!< Specifies the input. $ u# U! ?' H! W4 G; | This parameter can be a value of @ref TIM_Input_Capture_Selection */ # j0 A) Z! x1 U# f( N % C4 p7 p- t/ U1 b. h uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.1 O' Q* z4 f; S This parameter can be a value of @ref TIM_Input_Capture_Prescaler */8 ~' E! `2 m0 ~0 r! \ 2 t/ `/ E: P) g7 Q) ^- w: J uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. T4 m/ y9 ]0 ~4 p9 g3 z. ]1 _- ` This parameter can be a number between 0x0 and 0xF */ $ j, y3 v" J( X! y} TIM_ICInitTypeDef;复制代码 ) Z* P" Z9 C" @TIM_BDTRInitTypeDef 1 l* @2 i; c8 x' [8 D4 f) K$ E. i* a0 k* p3 w9 E1 e( v /** 4 }! i% I- B) s) R$ N3 {6 y4 p * @brief BDTR structure definition ( ?/ `! b* k2 O. S9 x( b, N * @note This structure is used only with TIM1 and TIM8. : f. | x8 Q" q& l' B */ 8 s3 M2 }* J. o$ D) g5 ^: i5 ?& |5 e7 d3 `8 ^+ _) H; F typedef struct . \# r6 w0 ]5 s9 w1 k6 z{ # \8 i/ j' `$ B5 q; w; C3 f0 \! C% V uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.' l2 Y- h+ h% h. c* A This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */, Q t; w& M# Y7 o # ^) L4 I# F5 K0 }1 Z uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.+ Q$ K% [. B8 \) m! _ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */" K: n4 J" w9 T3 I9 P3 i; u: \ 8 b8 Q5 l! l9 y! g$ }9 f3 J L uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. 7 k# j2 [; b% f This parameter can be a value of @ref TIM_Lock_level */ * p P( T& B6 x& |. h. m5 [( [9 l6 b uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the " H! w1 o' ]. \3 _- Z8 U switching-on of the outputs. ' L: a$ N _" f This parameter can be a number between 0x00 and 0xFF */) ^; u% Q1 K' s$ M; _7 f N$ a 5 c$ M: u8 ?5 Q+ D uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. - Y! w1 w0 y# c3 q n* q; x" b This parameter can be a value of @ref TIM_Break_Input_enable_disable */6 E0 C; o/ h% t w: K9 I+ c & ?2 b6 Z A' ] T5 D7 m6 y' | uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.- Y; P/ c! k [. o" R3 l9 R0 I# b This parameter can be a value of @ref TIM_Break_Polarity */ 5 {0 I; `& M5 R7 ^. c& s! |, k- D8 y/ @7 @$ n1 P. E- n" k uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 7 q4 M- I+ N% |0 B This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */% @4 I, ^1 q! d' H# {+ a) P } TIM_BDTRInitTypeDef;复制代码. G! U1 b w2 R- o* P* W TIM, f, U4 R8 V! K- T9 I4 X7 Q ' w8 o* L5 r2 n1 m/** @defgroup TIM_Exported_constants # {1 M7 f, }" a' Z* i! {8 a7 h8 v * @{ 4 a# M7 M. o! ?4 z% _* c */ " E& C+ X+ x: ^. _ s% `4 _+ N/ |: i: |6 |0 I #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \/ j1 F. t2 p3 M( P ((PERIPH) == TIM2) || \ , F A% v) v+ o- M, } Z ((PERIPH) == TIM3) || \ 5 f4 g; j9 {8 A" y) c ((PERIPH) == TIM4) || \ : a2 [' z' c* k' ^6 P, w- u- Q ((PERIPH) == TIM5) || \ - b" _$ z4 V2 K2 v+ D/ F! |; V ((PERIPH) == TIM6) || $ g- M! u: `/ S1 @2 w! e6 l- P% ^ ((PERIPH) == TIM7) || \ n% D1 s4 a2 _ ((PERIPH) == TIM8) || \9 o/ K& `/ B$ f- n ((PERIPH) == TIM9) || \ 7 Q1 }9 q% S2 P* R ((PERIPH) == TIM10) || \ 7 p& L7 Q7 w2 m; {9 \ ((PERIPH) == TIM11) || \ 6 z8 d- V+ e) [( y ((PERIPH) == TIM12) || \ / l Q/ V c$ F( K8 _. m (((PERIPH) == TIM13) || \( s8 `+ l/ Z2 V' Q ((PERIPH) == TIM14))), q* y1 B/ J; p! \ i6 A /* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */ - P0 g: c- E. ~+ _: l #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \: O% F" T; c. _- a) L4 C- E ((PERIPH) == TIM2) || $ x% N4 \1 [! b7 {- V7 Q ((PERIPH) == TIM3) || \5 r- K; e" e& C: g7 L ((PERIPH) == TIM4) || \! l- t# T: a* |" t# Y! O1 y ((PERIPH) == TIM5) || \ * N. L% C2 ]* k. e ((PERIPH) == TIM8) || \ ; L' x: a, f! {0 j; ^% y; \3 o ((PERIPH) == TIM9) || \8 Y* |" I9 {4 C4 k9 M& X; Z ((PERIPH) == TIM10) || \" f! @) i% w- \- x: p ((PERIPH) == TIM11) || \* W% Q+ y' j9 u7 } ((PERIPH) == TIM12) || \ / e4 K( }: M: p/ {! \" v4 m ((PERIPH) == TIM13) || \ 6 [# S& q% e+ ^; Y4 `9 J; j. w: y ((PERIPH) == TIM14)) 7 }3 j: {* L6 }! ^8 p2 R; U. G / d3 G& M' P/ V9 { F/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */ 7 z; E7 P% p$ T$ q2 J' |0 U#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \! K) b$ @- u8 n8 r# A/ r5 ? ((PERIPH) == TIM2) || \ 0 F8 [- H2 e; B: L' r ((PERIPH) == TIM3) || \ $ f8 j/ a% u& `% T0 @, u' {9 V ((PERIPH) == TIM4) || \ 0 d: n* r. J- Q3 H3 @* f ((PERIPH) == TIM5) || \ ( ]7 u$ w. l5 P2 z) q1 L ((PERIPH) == TIM8) || \% {5 D: |2 Q, @5 B7 s& O1 p ((PERIPH) == TIM9) || \+ b2 w. \# q* K2 e8 R ((PERIPH) == TIM12)) % j) F5 p9 B F% c' w/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */ " w7 B9 c; S T; w% I& [#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 1 ]: H2 ]7 t% ?( A ((PERIPH) == TIM2) || \ 4 W) t4 ~" G/ z ((PERIPH) == TIM3) || \ + o0 V# k# Y5 z7 ]3 P1 j' M5 O ((PERIPH) == TIM4) || \( f) O4 p2 _, E' Z5 e1 g T ((PERIPH) == TIM5) || \ - U( c% K8 x/ r) ]5 \8 ? ((PERIPH) == TIM8)) + ?- z% g' [5 C6 u7 b$ M/* LIST4: TIM1 and TIM8 */ . K' u- x0 m" y @! @. m3 z#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \9 ~( J3 v W3 X. p4 E8 u ((PERIPH) == TIM8))- G5 C( ~* ~) f* u /* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */ % ~! b _& j; K' P. P; t# ~. C#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \" b6 ?. H3 {& j7 |$ e( y ((PERIPH) == TIM2) || \% ?0 c" Z6 _, s1 ~1 _ ((PERIPH) == TIM3) || \ * a M5 C* ~* [6 V5 \: {; H. t: @( Z ((PERIPH) == TIM4) || \, m5 j( V. R. D' J( T' B ((PERIPH) == TIM5) || \ " Q- J# m$ a& N- f# z4 G ((PERIPH) == TIM6) || \/ j0 s' |$ G4 ?0 e ((PERIPH) == TIM7) || \ * ~0 Q, V$ S6 P* }6 }0 S ((PERIPH) == TIM8))" @: W9 F# v$ |$ D* a4 C5 s* j /* LIST6: TIM2, TIM5 and TIM11 */ 9 T$ d# W7 G; S2 h4 p#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \7 _1 {; J# @- `/ V8 ^3 z ] ((TIMx) == TIM5) || \$ f' P$ \2 ~3 y* {$ A- B3 m ((TIMx) == TIM11))复制代码 7 Y) m5 J* O" S' u# \ ~ I' d+ DTIM_Output_Compare_and_PWM_modes. I% {& y: Q4 w& ?% g9 G + W' w" N6 \% e' ? /** @defgroup TIM_Output_Compare_and_PWM_modes 5 V, i+ p+ p9 v) S * @{ ) t( U* a- P8 H$ u' S1 M */ ; ^, h" h/ R' f/ F R5 x- L- P 2 {; M0 v$ X" \0 g6 i' ~, a) Q+ w% o#define TIM_OCMode_Timing ((uint16_t)0x0000): L1 y5 h: k0 L/ J #define TIM_OCMode_Active ((uint16_t)0x0010)1 F, I* W6 d) o #define TIM_OCMode_Inactive ((uint16_t)0x0020)5 O+ Y. E; O2 u$ I3 O2 Z. M #define TIM_OCMode_Toggle ((uint16_t)0x0030) 3 {3 \ l6 ~( H8 O( u! T1 g#define TIM_OCMode_PWM1 ((uint16_t)0x0060) * u, O+ V/ Z; s+ R* T( ~3 G#define TIM_OCMode_PWM2 ((uint16_t)0x0070)- y" \: S9 M1 }8 Y6 i8 V$ i9 n' J' O #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ " `- P: z2 a: k ((MODE) == TIM_OCMode_Active) || \ $ q9 ]2 y4 U0 l. L5 n7 H: T6 ` ((MODE) == TIM_OCMode_Inactive) || \% g I+ R* {+ G" L" m- M( X& _( x ((MODE) == TIM_OCMode_Toggle)|| \ 5 @/ K8 Z9 b$ l" ` ((MODE) == TIM_OCMode_PWM1) || \ ! g% V. w7 B0 e& { ((MODE) == TIM_OCMode_PWM2)) ! O. o6 W9 W( T1 ?#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \# n, N3 L4 `, [0 l ((MODE) == TIM_OCMode_Active) || \% j7 K) N" M1 Y9 o2 ~5 A, v' ] ((MODE) == TIM_OCMode_Inactive) || \ 0 I2 x, t$ v4 j8 Q# N3 ^6 J ((MODE) == TIM_OCMode_Toggle)|| \ / S! g/ G3 E. P7 n+ J" a ((MODE) == TIM_OCMode_PWM1) || \ 2 `# @9 {) O0 E# l: B' F2 A ((MODE) == TIM_OCMode_PWM2) || \7 e, a4 G9 f+ a( P ((MODE) == TIM_ForcedAction_Active) || \9 v2 j% `! X% F ((MODE) == TIM_ForcedAction_InActive))复制代码( s* ]& W/ u9 Z5 {/ j( t/ _6 E TIM_One_Pulse_Mode ( u" F( X' c% @, s9 w. P5 T; J) e( b /** @defgroup TIM_One_Pulse_Mode 5 M u6 R' K2 d- q0 i * @{: } f) t; h) O | */9 X1 {# C) M! T; k; y( S 0 a' z) j& r6 D/ l/ u #define TIM_OPMode_Single ((uint16_t)0x0008)8 O2 o6 i/ q/ ~( T7 h3 @# V #define TIM_OPMode_Repetitive ((uint16_t)0x0000); p' m; q* A4 _, C #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \4 y) K9 j- E( Y3 Z7 U ((MODE) == TIM_OPMode_Repetitive))复制代码/ Y5 s g1 C( U# X" { TIM_Channel ) o" r" p; e3 b- h+ F* W1 U5 N! y, }) I0 G /** @defgroup TIM_Channel ( x* |$ a9 m9 a4 D! T * @{7 x3 ^- z; c0 ~! b3 p */ & w* V" {1 z. o6 J" `" E; H. o0 K" `7 { #define TIM_Channel_1 ((uint16_t)0x0000); N2 |: l0 P9 E# ^0 } #define TIM_Channel_2 ((uint16_t)0x0004) ( X$ [# K0 k: O1 k* l( n' T#define TIM_Channel_3 ((uint16_t)0x0008) % Y* Z+ c& N; `/ A/ z#define TIM_Channel_4 ((uint16_t)0x000C)/ O" z( p. J# x % m, D2 L$ s9 U% `0 q#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \5 [. d0 C! W8 r# c ((CHANNEL) == TIM_Channel_2) || \% g( M4 i. @# ]5 W8 T ((CHANNEL) == TIM_Channel_3) || \ ) B7 w. O. T! C ((CHANNEL) == TIM_Channel_4))3 {: q1 u O1 y; z- l o7 U - c# T W/ x+ _: I0 y #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 3 q) I8 o6 P& B+ m ((CHANNEL) == TIM_Channel_2))+ H. n* A' x& l' i9 h #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ * Z1 D, G9 o9 L- c ((CHANNEL) == TIM_Channel_2) || \ 9 b; h( g: `- m2 c3 e E ((CHANNEL) == TIM_Channel_3))! T1 q" S$ Y D( R 复制代码3 M& p+ m; [6 Y( _( i TIM_Clock_Division_CKD: o+ `& L! R& M) d1 p+ R% p, x# V - l9 }! k& w" r3 n% r, h /** @defgroup TIM_Clock_Division_CKD 0 D5 N/ S9 f& ^ * @{ " z3 m" H) |. B8 C+ J7 J/ J */ 0 F# u& _$ G# J, g; X6 Q. Z3 @/ T4 B$ S: D( `6 Z7 B/ L #define TIM_CKD_DIV1 ((uint16_t)0x0000)* a0 h i q" q& l4 h #define TIM_CKD_DIV2 ((uint16_t)0x0100) " k% m; ]9 y0 c1 L#define TIM_CKD_DIV4 ((uint16_t)0x0200) # S, F; L4 i1 Y& Z, A2 u$ A# S#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \: F7 \, E- ^( i2 l& Q { ((DIV) == TIM_CKD_DIV2) || \ 2 d4 s/ b n. t% |2 z ((DIV) == TIM_CKD_DIV4))复制代码! M, C0 t; I& N, H n TIM_Counter_Mode) n6 H3 k/ ]0 w# p$ E) W( o: e - l) b* g1 v6 u& H" Z4 R9 K' J/** @defgroup TIM_Counter_Mode 8 `8 q& k* R. k9 e# _ * @{& I& x& o# M8 U* d& x* X% K */ ; m: d. _! K: V* B/ |. e5 n 2 S* d. f1 y8 p& {7 ^#define TIM_CounterMode_Up ((uint16_t)0x0000)$ s5 i( w, X0 | e9 M9 Y #define TIM_CounterMode_Down ((uint16_t)0x0010)8 b6 F9 A" j" }4 F( x7 y #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) & _- B( \7 X' j0 O( g0 K7 R Z9 C#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) 3 R4 m/ e. {- {! D8 \2 l3 ]: ^#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)# c7 L" q0 u% \7 N9 v #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ 1 | N3 h, U4 e" U9 V' R* d ((MODE) == TIM_CounterMode_Down) || \ : w7 \3 P$ h2 }" W- B2 | ((MODE) == TIM_CounterMode_CenterAligned1) || \7 B* a, j$ z) O9 X3 x9 N, S ((MODE) == TIM_CounterMode_CenterAligned2) || \3 q; |! l; B: d1 G ((MODE) == TIM_CounterMode_CenterAligned3))复制代码. a# W2 q! y! ]* [8 h TIM_Output_Compare_Polarity 2 b/ }5 Y! A9 @7 G5 Y6 l5 Y) D# R* s! I+ d9 q /** @defgroup TIM_Output_Compare_Polarity & `' }( C4 f, L4 Y * @{& e1 ? r8 Q4 @( e0 I% j6 R */ 1 Z0 M' m* d, C 2 X! w; h8 G4 G. M% v#define TIM_OCPolarity_High ((uint16_t)0x0000)+ p I7 I2 _% O #define TIM_OCPolarity_Low ((uint16_t)0x0002) & X8 ?7 s) @% ^& D6 M0 l#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \5 y! g/ t! l, W ((POLARITY) == TIM_OCPolarity_Low))复制代码 7 K+ b* J8 L* @' F3 fTIM_Output_Compare_N_Polarity/** @defgroup TIM_Output_Compare_N_Polarity ' F8 \2 J3 ^" k. [ * @{7 m; D# e+ H# ~% R */ & w2 B* W: S! k/ ]2 ?' \( e+ x! M3 E7 R) z3 q% ?* l# U; { #define TIM_OCNPolarity_High ((uint16_t)0x0000) ' N4 h, x. U) n1 s9 x: u) h. ~#define TIM_OCNPolarity_Low ((uint16_t)0x0008) : Y( R; Z. C6 n* R- |+ R$ _#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ $ c0 q; s7 V4 g ((POLARITY) == TIM_OCNPolarity_Low))复制代码 1 W% D- X" b4 m6 E* Z; q( oTIM_Output_Compare_State 5 `; [4 _( s9 [+ o# B S4 |; c$ T/ n3 K3 M+ W0 ?, ^* Q4 t /** @defgroup TIM_Output_Compare_State - Z6 a( \7 Y/ b* z * @{2 M. R8 n# }: y5 g( w7 @" Y */ ) u+ f3 T* l5 R4 S5 K. t) I4 {4 C0 R& @" a# q #define TIM_OutputState_Disable ((uint16_t)0x0000)$ H9 M; M% b, M4 H1 N #define TIM_OutputState_Enable ((uint16_t)0x0001)' W9 W: a+ O3 u9 r0 ] #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \1 c& T! B0 v# z0 j l ((STATE) == TIM_OutputState_Enable))复制代码 # {8 k+ }, w" {5 LTIM_Output_Compare_N_State 6 x0 o) c4 a! t ; O% ?0 U/ S3 H& M- j! j1 [: Q/ _9 U# p/** @defgroup TIM_Output_Compare_N_State 0 s" a4 Z1 w; [/ d8 T, x. l * @{ ) t! X/ k ?1 j. b' i7 _" q' ] */ 3 h) c$ T0 J3 _' n1 W4 }, F. _& v6 {( m+ w+ r2 U$ V) h4 F" A #define TIM_OutputNState_Disable ((uint16_t)0x0000) * A7 U9 p! c, d1 h' |( c#define TIM_OutputNState_Enable ((uint16_t)0x0004) 7 R! A+ P4 O9 I8 l( y- X4 m#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \+ O7 B0 |& v# U% c i: S ((STATE) == TIM_OutputNState_Enable))复制代码 * B7 l0 z+ |! f. tTIM_Capture_Compare_State 8 j3 l5 ~- k: d$ F$ D9 T; q1 ?$ m' |8 n' K( ], d# u7 J# ` /** @defgroup TIM_Capture_Compare_State " L- }: k4 ^) a# N1 ~8 H' ` * @{ 6 K3 ^) f7 b' U: M8 g */6 {* a; o( i$ p: E* J5 E0 G1 k 5 d) o3 H- G8 Y6 d4 }% S% f#define TIM_CCx_Enable ((uint16_t)0x0001) " [5 @( O: R7 W6 L# K#define TIM_CCx_Disable ((uint16_t)0x0000)! C( ^* v) P" a #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \6 _' H9 u# S1 L ((CCX) == TIM_CCx_Disable))复制代码! O% S8 q$ N; P& |' P6 |0 m1 ` TIM_Capture_Compare_N_State " c4 }$ z! T- m) V/ }3 c3 T5 @! w6 V3 D$ f' l' Y; g1 f /** @defgroup TIM_Capture_Compare_N_State/ j& a8 m- F8 g * @{ * _/ ?# m% G" \0 n */( l' w C& S9 K- }8 I* J2 A * z9 o' m Z6 L" O; L: Z/ N #define TIM_CCxN_Enable ((uint16_t)0x0004)0 `" C. v1 M3 n9 A* f3 m* y #define TIM_CCxN_Disable ((uint16_t)0x0000) 3 {$ A3 ~/ O0 X$ u#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \+ ?9 V% y' b8 ?- | ((CCXN) == TIM_CCxN_Disable))复制代码0 r5 ]$ s: q1 m! F- O TIM_Break_Input_enable_disable* C( L8 R5 K+ H# q1 { 1 u& _# J' h: B0 i$ @/** @defgroup TIM_Break_Input_enable_disable , a. s+ X+ V x' _: G3 Y- E* R * @{ 4 G; e/ j' Z, \1 L# q! U7 F */1 N* ^) o, b. p. Y' p0 m+ S0 x 2 Z6 n1 u3 p# I #define TIM_Break_Enable ((uint16_t)0x1000) " j+ w- J, r0 w- I; a#define TIM_Break_Disable ((uint16_t)0x0000)& z% H0 y$ p$ g8 @3 a% z4 `; |+ D #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \# Y& I `- Y ~ ((STATE) == TIM_Break_Disable))复制代码 4 x( B; H% X0 U1 o, jTIM_Break_Polarity 5 ^0 ?3 T/ t1 v' y8 @3 A8 N 3 O R- E2 O; ~/** @defgroup TIM_Break_Polarity 7 y# h$ H& @& N# z( K$ n) R * @{ 0 i+ s8 w& ?) u) G */ 5 P2 u9 \2 L; R( V7 j4 i J, O! L+ O% e5 w$ v, a3 {+ v7 p #define TIM_BreakPolarity_Low ((uint16_t)0x0000) ; q0 a, y, n- W8 y$ {% c#define TIM_BreakPolarity_High ((uint16_t)0x2000)0 ^- D% C* ~: H1 b7 s1 y9 \. r+ n #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \* B9 n5 f0 @* E# x/ b ((POLARITY) == TIM_BreakPolarity_High))复制代码- m4 r9 I3 {: y' y1 [ TIM_AOE_Bit_Set_Reset& P5 z8 c. p! p& z- {/ b /** @defgroup TIM_AOE_Bit_Set_Reset : J8 g% ?3 W0 t" Q5 e9 w1 ?/ c- N * @{ # w3 b: }( I+ g0 W/ R */ ' X+ D# d% i* U" d8 g& M# N) B6 b6 o- x' _4 d/ r( x #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)2 [4 Q: e; e8 I" q: n1 ~7 @ #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) ( p h: W; V% K) Y/ O; T3 |4 D3 F+ [#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \! Y) F8 M r' i ((STATE) == TIM_AutomaticOutput_Disable))复制代码 9 H: }/ ^2 e8 _# P+ Z; xTIM_Lock_level " k! ~/ M% X2 G7 g a, m. \& o d0 _8 ? /** @defgroup TIM_Lock_level 9 h% s3 z: z8 @. ?5 m * @{ P# u7 n. k' Q; ^# q */ 3 G3 C- H* N0 ]5 \7 b2 I" j4 ^; C+ J) B8 O #define TIM_LOCKLevel_OFF ((uint16_t)0x0000)4 F8 p, Q' i3 q6 x b #define TIM_LOCKLevel_1 ((uint16_t)0x0100)8 W# ]9 ?; G& E# u #define TIM_LOCKLevel_2 ((uint16_t)0x0200)2 b# @" l- e, Q/ q" U$ W7 {+ E #define TIM_LOCKLevel_3 ((uint16_t)0x0300) # v* N* V' N* E. Z9 d7 c#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \- O# k" d& A# Z& j6 O. u ((LEVEL) == TIM_LOCKLevel_1) || \) h# J9 ^- O0 [. w0 ?8 Q; ^ ((LEVEL) == TIM_LOCKLevel_2) || \" c" y# @6 i* o& h0 v) d! y2 h* z ((LEVEL) == TIM_LOCKLevel_3))复制代码 , S5 u/ _2 Z6 Q) M& E+ ~& sTIM_OSSI_Off_State_Selection_for_Idle_mode_state/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state - } K& r, y8 ]8 h' N/ U' |3 W * @{; o1 o# p9 V" ]* ~ */; H+ Y( U) C. ^$ n* Y. W . G6 P+ v: k. {- k. J) ~5 F% l #define TIM_OSSIState_Enable ((uint16_t)0x0400) # M1 Q! T7 w! }5 `, P#define TIM_OSSIState_Disable ((uint16_t)0x0000)# o; v& h+ c, d% ?, X$ }' [ #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ 8 _- [7 i! a- x0 j ((STATE) == TIM_OSSIState_Disable))复制代码 3 H+ G8 p- Z# [TIM_OSSR_Off_State_Selection_for_Run_mode_state 0 W! ]2 N" u' V7 R7 R) ?2 d1 M( K% J4 K3 a1 j) P /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state3 w! V4 _7 p9 i5 v * @{ 7 L' z* @! E- G# n4 _ */ B, M( P% K1 m8 w* I: L! \ ; t9 C A5 v8 f$ |#define TIM_OSSRState_Enable ((uint16_t)0x0800) 3 z& w/ Y! Y1 ]#define TIM_OSSRState_Disable ((uint16_t)0x0000)' R! L- I) x- }# X/ s& Q3 e2 [ #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \5 \- i4 W x: [+ ?2 l. P. m ((STATE) == TIM_OSSRState_Disable))复制代码 : u- t+ a- i; |5 M4 lTIM_Output_Compare_Idle_State6 t5 Z% O* E% O' f : r$ J/ Y! U: K9 u/ A" {/** @defgroup TIM_Output_Compare_Idle_State ; k8 M8 D, E0 C7 U3 H * @{0 w j0 O; n% N$ r& m9 Y" X */8 h( X( ^0 R2 L# `6 T0 m" n% b ! I- X& @! a/ F" W6 E# R #define TIM_OCIdleState_Set ((uint16_t)0x0100) * E. Q U! J+ @1 [#define TIM_OCIdleState_Reset ((uint16_t)0x0000) - p0 g1 y" T: k( @+ Q#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ . d1 ^" A: s! s. E: v0 H$ \ ((STATE) == TIM_OCIdleState_Reset))复制代码- n$ b5 o! D: J% `: K% e TIM_Output_Compare_N_Idle_State" U6 ~+ i2 O" b8 [ : i' i: @$ @% e3 I8 ] /** @defgroup TIM_Output_Compare_N_Idle_State 8 `4 ~8 s6 U0 W- ]# M * @{2 M. `" y. I3 q */) W& b4 c- R0 ^ 0 p$ p( V$ C3 A5 e+ Z5 ^ #define TIM_OCNIdleState_Set ((uint16_t)0x0200) 8 r3 C4 e- m2 z) @#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)! q0 b7 h# q2 K #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ & H" W: H" m! S: H ((STATE) == TIM_OCNIdleState_Reset))复制代码 + w6 z: s+ O3 a! S, e3 ITIM_Input_Capture_Polarity! v+ c+ K6 {, k/ m. H: `3 A ; N* U1 y6 Y/ ?. I/** @defgroup TIM_Input_Capture_Polarity . Q$ j+ n9 H) J/ s( t * @{2 N: ~, u; G& w% `8 e- _ */1 n( j! X" a2 B6 K6 h : ?" M" Q3 E0 r. \7 x #define TIM_ICPolarity_Rising ((uint16_t)0x0000) / m+ L! L0 U0 P# {$ [#define TIM_ICPolarity_Falling ((uint16_t)0x0002)- t! Z- B0 D f6 J #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)0 b2 E! {" A8 P) }/ V #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \7 K" ^2 l7 h1 }7 d0 B: ? ((POLARITY) == TIM_ICPolarity_Falling)|| \+ N2 y3 k3 u( L ((POLARITY) == TIM_ICPolarity_BothEdge))复制代码 , v9 f2 ^7 V5 N9 xTIM_Input_Capture_Selection , U: r" k( {1 H O% O3 X ) ?6 S% @3 @$ J0 I+ M$ ^: [; p4 j/** @defgroup TIM_Input_Capture_Selection 5 {: m$ f# @/ g) T. X * @{' Y, p9 o5 @5 a$ |7 C */4 c8 @+ k' i# `( t* @ # V8 g, a3 P& w7 i7 |) t4 j #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be 6 ~8 A7 s7 z$ t0 B4 i connected to IC1, IC2, IC3 or IC4, respectively */: `- d# q1 a1 B9 m, B+ ^ #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be & h' T; M% t- Q0 k- {8 {2 e5 ^ connected to IC2, IC1, IC4 or IC3, respectively. */ ) p: m% x. p7 c: t- z- `( L7 d: F4 @#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */( p5 _" B% t( v$ F9 \ #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \) H$ W2 v8 a4 N8 w3 l5 v3 |, C ((SELECTION) == TIM_ICSelection_IndirectTI) || \4 z; x/ Y. z1 a5 r B ((SELECTION) == TIM_ICSelection_TRC))复制代码. N" v. X- {/ T' O TIM_Input_Capture_Prescaler . [) }. x8 K: A4 B X7 [5 B7 J2 a3 _/ F, Y. l /** @defgroup TIM_Input_Capture_Prescaler ! W$ y% n" d; ` * @{0 ]. S# |) P1 J */ 9 V0 D7 L2 z' a$ ~2 G ! Q) U p$ A9 j1 Q: y% h7 `#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */: E: P, N$ R' c0 @ #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. *// \/ K# ~' ?' ^8 a# {7 a0 a7 R( S #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */! N0 B; I9 M3 ?; d) ~! V8 G9 G5 ? #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */; D' H( Q$ K1 Z- }/ v #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ 8 B$ G9 Y8 M% S ((PRESCALER) == TIM_ICPSC_DIV2) || $ E5 n$ O; $ n/ ] ((PRESCALER) == TIM_ICPSC_DIV4) || \8 I( K$ B. D4 F, g5 U8 N+ G ((PRESCALER) == TIM_ICPSC_DIV8))/ Y) }/ ^# }& `' `( ? 复制代码 : J; e( f N9 c2 t) V' _TIM_interrupt_sources3 o6 k3 C; Y. }( l2 v * O: w$ ]0 m3 c/ x0 q" Z /** @defgroup TIM_interrupt_sources ' h+ d2 s- |) _+ Q1 n( n# }- q * @{ 5 {. ~0 z% r, z8 T& S$ a */ 1 ]. H$ J# A% U2 G9 n, O1 d0 o4 F$ } #define TIM_IT_Update ((uint16_t)0x0001); S7 g3 U# ]$ Z7 T #define TIM_IT_CC1 ((uint16_t)0x0002) 8 z4 H% j3 a) Z+ D#define TIM_IT_CC2 ((uint16_t)0x0004)4 D0 y/ j8 I/ S/ q( X# F6 t #define TIM_IT_CC3 ((uint16_t)0x0008)% X) n+ z, Z( C #define TIM_IT_CC4 ((uint16_t)0x0010) . O j; }5 l) V2 D/ q) I3 A& M: Z* s#define TIM_IT_COM ((uint16_t)0x0020) / v2 N% u$ W$ P T+ g0 b6 x#define TIM_IT_Trigger ((uint16_t)0x0040) * A: `2 L# B1 T#define TIM_IT_Break ((uint16_t)0x0080)2 y8 C/ E& J, J+ e4 p- N+ N! c* C #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))' y1 |' k; B# q- S9 i% B ) @: i* }% K0 a3 J7 N #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \/ X7 p1 x3 U) R# q4 C& i2 ~ ((IT) == TIM_IT_CC1) || \+ B9 c f, i7 R4 o ((IT) == TIM_IT_CC2) || \ & Y/ S+ C( i+ i ((IT) == TIM_IT_CC3) || \ ; p# O. e; E4 t) u* r3 i2 V9 q( ` ((IT) == TIM_IT_CC4) || \* T! ^! T. p* T3 y* v- T# W. ^, y ((IT) == TIM_IT_COM) || \, D, p( d- c% h* T' c9 R ((IT) == TIM_IT_Trigger) || \ 6 ?) Q. Q; T: ]' A, p3 o( u1 a ((IT) == TIM_IT_Break)). n4 ^6 M- U& z7 ]8 d- C 复制代码 4 n: F$ a; X% a; B2 f- pTIM_DMA_Base_address # v% {# ^% e$ W7 H X9 }0 e ' L7 u' T8 f6 Z0 `. c; P/** @defgroup TIM_DMA_Base_address " y5 g* ~0 _$ \; i, j8 |) e * @{- f* T3 N; Q/ r4 u */ ( i7 g M0 A! p5 o' t * V0 n, ]* J- G, R% W) C# p) N#define TIM_DMABase_CR1 ((uint16_t)0x0000)# h2 `, i* X, O% j/ |$ d1 i #define TIM_DMABase_CR2 ((uint16_t)0x0001)0 p1 L3 B- ?! ^1 z& D0 J #define TIM_DMABase_SMCR ((uint16_t)0x0002)7 f3 O L" {& l" r #define TIM_DMABase_DIER ((uint16_t)0x0003) & c+ R" b9 b+ L+ `#define TIM_DMABase_SR ((uint16_t)0x0004) 4 T$ s& k2 J2 _6 ]8 F* E6 A#define TIM_DMABase_EGR ((uint16_t)0x0005) $ l% O7 Y7 O- Y; b7 l#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)4 Q# n% l6 W( m" A b! l& W #define TIM_DMABase_CCMR2 ((uint16_t)0x0007) 4 E( G- g8 r' P* w% f P. }#define TIM_DMABase_CCER ((uint16_t)0x0008)1 W4 T6 r( ~) Z #define TIM_DMABase_CNT ((uint16_t)0x0009) % M7 L3 L3 l- J! `6 i$ G2 J1 M#define TIM_DMABase_PSC ((uint16_t)0x000A)4 t4 f& s5 o- |( p5 g #define TIM_DMABase_ARR ((uint16_t)0x000B) - ]7 M- a5 a& ` i+ T4 S#define TIM_DMABase_RCR ((uint16_t)0x000C) & R2 _. Z' S4 I7 ?& q4 j5 X9 h#define TIM_DMABase_CCR1 ((uint16_t)0x000D)9 f; r( L! R& E( ^" J i #define TIM_DMABase_CCR2 ((uint16_t)0x000E): h9 P: L" |0 k& o2 C #define TIM_DMABase_CCR3 ((uint16_t)0x000F) / g5 x2 @/ {8 Z2 }0 L+ d#define TIM_DMABase_CCR4 ((uint16_t)0x0010)% u5 {/ a% d7 X #define TIM_DMABase_BDTR ((uint16_t)0x0011) 6 Z$ R" p; z. C2 p#define TIM_DMABase_DCR ((uint16_t)0x0012)1 ^! ?( M9 M/ v* R4 M8 B9 f- o #define TIM_DMABase_OR ((uint16_t)0x0013)/ T. \9 u+ ~* W G #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - B/ h5 e* c, A! t& m8 g ((BASE) == TIM_DMABase_CR2) || \/ j1 Y$ g# ~/ [# R) y9 d" Y ((BASE) == TIM_DMABase_SMCR) || \ % F; l6 v m1 ?# a. {& t ((BASE) == TIM_DMABase_DIER) || \ 6 t& Q% Y) Y7 |) o5 ]. ?4 Z5 w( _ ((BASE) == TIM_DMABase_SR) || \, x3 a' s; W3 H, n ((BASE) == TIM_DMABase_EGR) || \, @; s! L6 u% b ((BASE) == TIM_DMABase_CCMR1) || \ ]$ }" z0 F1 w; }1 ~( Y6 u1 l ((BASE) == TIM_DMABase_CCMR2) || \$ e+ M# y J" F" [+ ? e6 ?" h ((BASE) == TIM_DMABase_CCER) || \ 0 ~8 B! Z# I/ Y1 Y ((BASE) == TIM_DMABase_CNT) || \ " q8 Z* l9 l$ d E7 P( F) b ((BASE) == TIM_DMABase_PSC) || \ " i. m( h r5 V, h, { ((BASE) == TIM_DMABase_ARR) || \ ; ?2 S+ _, @ M {, Q* B" m ((BASE) == TIM_DMABase_RCR) || \ ; e2 ]/ D1 w( y5 b4 ^6 o ((BASE) == TIM_DMABase_CCR1) || \! L1 O3 ?# v, V: u ((BASE) == TIM_DMABase_CCR2) || \% H' ?7 r) d; _7 r5 V2 W+ E ((BASE) == TIM_DMABase_CCR3) || \6 C) |8 s! ^6 K9 ]9 a: p% D$ K1 v ((BASE) == TIM_DMABase_CCR4) || \ # \8 ^" p( B2 H' w ((BASE) == TIM_DMABase_BDTR) || \* z' g- V! F9 L6 b/ K9 e5 F- B5 t/ ~ ((BASE) == TIM_DMABase_DCR) || \ " ~( U3 L% B! |) B2 z8 j ((BASE) == TIM_DMABase_OR)) 复制代码9 t p, ]- a0 y3 Z3 \: y TIM_DMA_Burst_Length; y6 I" }0 W5 S& h) S$ } 8 m2 K- @4 S+ z+ j4 x& u /** @defgroup TIM_DMA_Burst_Length # O O3 [% t0 ^9 J5 M * @{ # S8 u" f: }; Q' {# ^; w2 f7 H* H1 V */1 y- x Z1 k1 f; H* i' N . `* B9 L- O0 ?( w% u( o6 } #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)) E- m) Y( l$ ]- Z #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) 0 |' S( T3 Q: v0 T#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)! N, E# v$ Y# x, k #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)7 j+ C; C, m% e8 O #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) $ S0 p$ N; Q# C1 ^- L' @' \#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)* v' N6 U& K5 _' O' T #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)0 F2 t, N m# \- D s #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)/ a. a. h t" E/ u! M- a# r4 B5 y0 w #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)1 O! G x0 Z# A #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)# C3 |% m' m; \- W7 ` #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) 2 z. m* f/ P# Y0 B#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) 0 }) r9 ?6 N8 e. R0 v- \* e#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)& M5 ?/ P& j- ?6 D7 F #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) , p; P4 t, x/ e#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) # n% L5 m9 |. H4 v#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) % u# _" A1 R; T: W, L' h% l! e L#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) : H4 b+ s( g8 n" H* |#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) k7 s9 \$ g* G' k; {- v8 H V #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \: o" M* _+ [. C; A; z( G; ^ ((LENGTH) == TIM_DMABurstLength_2Transfers) || \8 @6 D' s# }7 q9 ` ((LENGTH) == TIM_DMABurstLength_3Transfers) || \3 D5 ?7 [4 U* x- F! J: Q0 D. H, T* t ((LENGTH) == TIM_DMABurstLength_4Transfers) || \8 T! ^+ t2 E) [& O4 n ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ $ B* _; x8 y' c9 K4 F0 t ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ . j! E. L( e }0 y' o5 | ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ . K. ?7 x9 S+ ?. U( l6 m ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ & |) x6 X# a5 T4 A; p+ R! m ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ ; ^! ^$ Y) Y) l* \+ [ ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ . X9 z$ w% Z" N$ C% j* s0 D ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ 0 ^9 C3 [8 [: u% C1 d% i6 T ((LENGTH) == TIM_DMABurstLength_12Transfers) || \* Q; c8 U, }# {' M N8 [3 w& q ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ . _9 c' y8 o: Y1 D# K& V ((LENGTH) == TIM_DMABurstLength_14Transfers) || \, m; H; i7 J- _, L! B ((LENGTH) == TIM_DMABurstLength_15Transfers) || \# u: s3 k8 t; D% T ((LENGTH) == TIM_DMABurstLength_16Transfers) || \# M- s/ y! x' Q7 m1 { ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ 8 U6 c( X9 ]- G* p ((LENGTH) == TIM_DMABurstLength_18Transfers))复制代码 4 u# ?- Q7 A) r9 I0 j/ ETIM_DMA_sources8 K, j/ E' d9 r' U" Q: G5 A 2 {/ W4 w, \; ~, F; v- N: W/** @defgroup TIM_DMA_sources 8 F4 S' H) ` \ * @{ f9 ?4 f; r9 z% G! \, M) G) p0 v1 U */ P, h3 K+ \0 X& D5 V ' ` M$ H" A+ {' z5 h; _* u#define TIM_DMA_Update ((uint16_t)0x0100)) Z1 Y& n+ j9 e #define TIM_DMA_CC1 ((uint16_t)0x0200) 8 E1 t! c+ C/ B* i) W#define TIM_DMA_CC2 ((uint16_t)0x0400) ( O0 a5 w0 L H# L; U$ h1 ^#define TIM_DMA_CC3 ((uint16_t)0x0800) 7 b) G2 p6 H9 }" ]2 M) i#define TIM_DMA_CC4 ((uint16_t)0x1000)( U/ V4 R* \; P- K1 X' n #define TIM_DMA_COM ((uint16_t)0x2000) - s$ g8 u M/ {# i) ?( x9 u#define TIM_DMA_Trigger ((uint16_t)0x4000), `3 A8 m8 I! {! }( s9 [# {6 n B #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))复制代码 5 C/ _1 q# _/ V# @TIM_External_Trigger_Prescaler( b5 d# N! _9 l1 a' |4 @ # L5 j0 ~+ W B7 ] /** @defgroup TIM_External_Trigger_Prescaler % M' |& j' ]/ C$ d# Y * @{+ J) l8 [4 U8 w( N" t */( y' L( R8 Y: x8 B" X* E& Q , i0 v6 U+ `5 T: }* ] #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)+ q0 y T6 [1 Y, l; W9 V3 H #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000): c, z( U) {2 j$ h #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) ( R- Q% a% e0 s9 I' d0 c$ w( B#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)( I! W# u2 `3 ?6 X- ~- ]" s; P* u- D9 n #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ 4 c: ]: n% d* B ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \9 J8 G8 }- Q1 r7 M+ E" y ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \. x% I1 O* ]6 w1 I ((PRESCALER) == TIM_ExtTRGPSC_DIV8))复制代码 - q, ~! I6 i9 Z8 | G# C7 t# RTIM_Internal_Trigger_Selection * n! D7 ?# ~8 S; B; F6 |( C & w6 F# K! X% G0 m" N/** @defgroup TIM_Internal_Trigger_Selection : r. T# b( S. b' {$ @ * @{# f" V+ X0 R7 c8 U# d */ 6 C3 U4 b w. L; `$ C% j 1 y Z' T3 U( V. y4 h" z#define TIM_TS_ITR0 ((uint16_t)0x0000) ( J1 l. b$ [8 U8 e& E; x6 v# B#define TIM_TS_ITR1 ((uint16_t)0x0010)$ W5 H! K# y2 B& Z" F) e5 z; Z #define TIM_TS_ITR2 ((uint16_t)0x0020) 4 Z7 {/ Q/ a: R0 T- H#define TIM_TS_ITR3 ((uint16_t)0x0030)# Y6 }4 Z, W2 f #define TIM_TS_TI1F_ED ((uint16_t)0x0040)0 B8 J$ l, x* R' g #define TIM_TS_TI1FP1 ((uint16_t)0x0050) $ l4 w; H* j2 I- l. y#define TIM_TS_TI2FP2 ((uint16_t)0x0060)! q4 C( T' p/ ^/ r4 ^% w #define TIM_TS_ETRF ((uint16_t)0x0070)1 I2 E9 ] Q/ k( [% y2 l5 V #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ ; T- L1 k5 [$ `2 r2 [9 O+ h% F ((SELECTION) == TIM_TS_ITR1) || \ 1 u( H5 ]+ Z% P) R/ j& ~- } ((SELECTION) == TIM_TS_ITR2) || \ \9 D2 D* a8 S ((SELECTION) == TIM_TS_ITR3) || \ W5 W# p+ l( k: _ ((SELECTION) == TIM_TS_TI1F_ED) || \* i$ a( h& Z1 w' p* l; t ((SELECTION) == TIM_TS_TI1FP1) || \ 8 y. O6 [5 \4 a* h D2 i ((SELECTION) == TIM_TS_TI2FP2) || \- k1 b& l6 c) m ((SELECTION) == TIM_TS_ETRF))& X8 o# o2 J: X; i1 G #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \9 C* c4 d, r6 J9 F4 M ((SELECTION) == TIM_TS_ITR1) || \' j2 w( U( N( k6 }+ |( c: M ((SELECTION) == TIM_TS_ITR2) || \ 4 K; v3 S6 g1 m, _4 b* a ((SELECTION) == TIM_TS_ITR3))复制代码5 c! h4 B6 ]0 C TIM_TIx_External_Clock_Source$ T$ y& K- ~. Y5 o( V( V ; o. I1 M0 U. @; G2 n /** @defgroup TIM_TIx_External_Clock_Source 4 b4 i0 i4 \2 `; ~ * @{4 B$ x2 T( I3 |6 h- w */ 0 T) X7 J% w- J$ L; m- d+ ~ 7 C; z7 R! L* s0 i" H( A#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) " R* Z0 L- C3 h+ E) u#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)/ Z. L% j# P+ Z% X #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) 0 r. @+ R/ W1 c* O$ Z& @; S+ L复制代码0 M% @6 U: m4 I/ Y8 _# O% { TIM_External_Trigger_Polarity 4 T7 _$ ?! ^8 w; ^1 l* B6 W0 L% m7 F% Y /** @defgroup TIM_External_Trigger_Polarity 7 n( Z6 A. e) i * @{* }% [" c% j- M: g- V' |" X */ ) X& @9 s `' {; b#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)9 [9 z1 e: @( ^% \5 C #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)- U' n8 t; B: h% P1 ?* v; a #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ ~9 w8 a% @$ F& y8 W; X ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))复制代码 8 u* N2 Z; y$ x1 ITIM_Prescaler_Reload_Mode % W d3 f; j V# g* y; Q5 {8 ` , T" O4 K! E1 T( J4 o/** @defgroup TIM_Prescaler_Reload_Mode ( V! u+ n7 w; ~; R1 _4 i# ? * @{! ? H# X( a& ~3 z */ ; K( U6 h1 C9 O* E " J3 x1 {' _) y8 Z2 J9 b: ^#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) X$ V# H, |8 |7 r, Y9 Y7 S#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) 1 M# _7 q1 {" Q* D#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \) i% V$ c5 Z! L- { ((RELOAD) == TIM_PSCReloadMode_Immediate))复制代码6 z$ g; H* r" u; {) @ TIM_Forced_Action 9 C! {; P1 ]& O% s6 ? 9 o [- x& M: k- ^1 z2 `/** @defgroup TIM_Forced_Action * G9 h. X8 T/ H& Q * @{ 8 i; P4 u; Y) }6 L */ $ n- }; T& c( b v9 O/ g& O & F& W" w0 q1 }- b2 b#define TIM_ForcedAction_Active ((uint16_t)0x0050)' c5 l# G7 P' c$ [ #define TIM_ForcedAction_InActive ((uint16_t)0x0040) ) P s2 |5 D0 Z" F; h0 D9 ?# z#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \! G& P4 R, H w ((ACTION) == TIM_ForcedAction_InActive))复制代码 % |. c" K" Y) X0 ?: i7 B( J2 V( ~/ lTIM_Encoder_Mode 0 Q' p1 ^, m4 O% f" w: Y H, X) v0 W$ x; Y /** @defgroup TIM_Encoder_Mode + Y; \$ @' s: Y) t6 x! x6 j * @{' L% z. b' |3 H */ " J% i% W1 ]/ f1 f# M! ~ 2 D( I- t; W0 B5 J* O6 o#define TIM_EncoderMode_TI1 ((uint16_t)0x0001). @" u2 X# ?) Q1 A/ \, W0 N #define TIM_EncoderMode_TI2 ((uint16_t)0x0002)5 R! l4 t7 Q) ?' ]/ V6 G, k: g. I #define TIM_EncoderMode_TI12 ((uint16_t)0x0003) ' t/ i- e {9 m6 Y" x#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ 3 z& J. q( o( w2 P1 F* a6 C ((MODE) == TIM_EncoderMode_TI2) || \! C' }, |$ C3 v, _5 ]9 H. f; [( L ((MODE) == TIM_EncoderMode_TI12))复制代码 % u# M0 q. B: x$ D) O) VTIM_Event_Source; n" T. c {/ S% x& x4 P 8 ]' }, |' t# G4 r+ W/** @defgroup TIM_Event_Source % r2 B9 K( k7 E l * @{# x& P2 V6 z5 F3 x. b- q6 N( [1 L */2 D2 f! M( X, a" U3 Q# j * k, P) w+ A; D$ X1 ?& y) o #define TIM_EventSource_Update ((uint16_t)0x0001) ; a4 F6 K9 G& [7 ~ W#define TIM_EventSource_CC1 ((uint16_t)0x0002) * ?) D. U- }8 D* T9 K' x#define TIM_EventSource_CC2 ((uint16_t)0x0004) & P* T8 Q7 C/ P#define TIM_EventSource_CC3 ((uint16_t)0x0008)& v4 v& w. }1 L #define TIM_EventSource_CC4 ((uint16_t)0x0010) # M& e4 R" y& p2 C6 _# X/ ?% n* r#define TIM_EventSource_COM ((uint16_t)0x0020) , o. l/ n Y1 q/ m4 X#define TIM_EventSource_Trigger ((uint16_t)0x0040)5 m9 V# q# z) d3 v: e5 S" H #define TIM_EventSource_Break ((uint16_t)0x0080) ( W8 s9 Q7 P. r8 b8 H% M#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) 复制代码1 Q. g/ Y9 N1 ?! r+ y TIM_Update_Source & z- ?5 [: Y' X# |7 e) L+ b/ N6 n1 t, p" e9 {) m) b/ ?: b /** @defgroup TIM_Update_Source : a1 R5 R4 W5 n/ R+ | * @{ . _1 q7 t. i, |' Z( z' X */8 p: N( ?: H+ z" I( m; m 3 e; Z i' `, L: P #define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow $ f( X' ]' q" B& p& l' M8 z or the setting of UG bit, or an update generation / H: G# I U ]3 ~% { N7 Q9 B through the slave mode controller. */ ! O6 |. `- g$ t#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ M c- q; I+ |& a# H+ n! k #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \1 g. ?3 b9 u V4 d/ q: Y: K ((SOURCE) == TIM_UpdateSource_Regular))复制代码$ M+ I' R3 g$ M$ A/ M- Z7 a TIM_Output_Compare_Preload_State 9 E( K3 E6 z4 J4 N( d* h- _1 U# {7 q" M4 ], }7 J /** @defgroup TIM_Output_Compare_Preload_State . ]. d8 h8 T# F! \ X! i * @{ ' ?6 a/ P- y' M% A! X */2 F, V$ l1 `& c+ J+ X" Q+ { 9 u8 I E r( s# A#define TIM_OCPreload_Enable ((uint16_t)0x0008)" K/ k8 N+ S! r4 L' U7 f6 g5 T& m #define TIM_OCPreload_Disable ((uint16_t)0x0000)* Z1 ~+ ?% }' q! l' L #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \$ K; G5 F- |; C. t2 D ((STATE) == TIM_OCPreload_Disable))复制代码 * j; t1 L, O! |0 lTIM_Output_Compare_Fast_State1 M" N: D0 ]) O* Q+ B* k ; Y0 {; S1 [7 H# g) X; H; C/** @defgroup TIM_Output_Compare_Fast_State * ]2 C! l6 ]8 x/ D0 h; ` * @{: c1 c! N0 c" K. r% Q8 W' D3 j */" g6 m" F4 k& }' O4 Y b/ b; B# L3 E( n8 {+ `. c #define TIM_OCFast_Enable ((uint16_t)0x0004) % }* j1 I2 e, c; I: Q, F: o#define TIM_OCFast_Disable ((uint16_t)0x0000)3 i! `7 [; R) W2 t #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ 0 q7 m* H; b4 O. j ((STATE) == TIM_OCFast_Disable))复制代码9 n- a* S0 ]1 P: d( } TIM_Output_Compare_Clear_State2 A( J* T+ S N0 q! C ( R, s4 y4 n$ ?& \# z/ g/** @defgroup TIM_Output_Compare_Clear_State ' }$ w4 \# R- f4 w% K( i* p * @{# ~' n7 y0 l6 ~% |7 N) ^" e* t */' ?* {0 a! [1 _/ t- e+ V / u! {0 j' k" L3 j4 d#define TIM_OCClear_Enable ((uint16_t)0x0080)7 B" s1 }. s* x+ F6 f/ \' ^1 G #define TIM_OCClear_Disable ((uint16_t)0x0000)% T6 T# B* s% W+ I4 [( s #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ 0 l& h! I8 E+ _; p) f ((STATE) == TIM_OCClear_Disable))复制代码 : P( \) h: M8 A. q- R. N6 PTIM_Trigger_Output_Source6 M+ q+ |; v9 B. R! _ - b0 r( \/ @- v: ~0 d) Z /** @defgroup TIM_Trigger_Output_Source : S* L$ y/ K2 Y) U7 _ * @{3 ^1 j" M" N; n2 _1 Y+ B( n */ + V. Z' P& D% N) E 0 n5 E: r$ x8 r' c9 g' w1 V. r4 D#define TIM_TRGOSource_Reset ((uint16_t)0x0000) : g; }6 g: J) I# u' x3 o! P/ d#define TIM_TRGOSource_Enable ((uint16_t)0x0010)* u) v& g$ H1 R% N- z1 x #define TIM_TRGOSource_Update ((uint16_t)0x0020)2 ^& m/ `+ T3 l' H. P' h4 \ #define TIM_TRGOSource_OC1 ((uint16_t)0x0030) % V, s6 l: s: N1 ]#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)& W5 d6 O6 u4 d- K #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)+ ~. X& M1 h4 R9 X0 y- l! Q7 @: J #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)" G, B0 }5 T& X) L #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + e d% w1 ~; B. x5 L9 {#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ Y: v# N+ B0 j5 R/ ^ ((SOURCE) == TIM_TRGOSource_Enable) || \* g0 z! q9 g; g& k7 P0 V ((SOURCE) == TIM_TRGOSource_Update) || \' Y1 V6 v4 T o$ ?3 f* | ((SOURCE) == TIM_TRGOSource_OC1) || \ M, I: C. }' ]3 {0 ~; q& j, U ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ 5 u9 Q' {5 ?, S' Z6 n4 N) o6 _2 Q7 T ((SOURCE) == TIM_TRGOSource_OC2Ref) || \6 F# l2 f4 b7 T* K* w3 W+ L ((SOURCE) == TIM_TRGOSource_OC3Ref) || \- t7 ~$ N) b: ^. d. |% S$ o ((SOURCE) == TIM_TRGOSource_OC4Ref))复制代码; l7 w3 v* s# U7 J0 V. c TIM_Slave_Mode ! X! f; u% ? T% T( C $ N; f) X6 f" c5 u' m. m ^/** @defgroup TIM_Slave_Mode - t, t4 o- c3 w0 K8 v. }2 x. g * @{9 i% q* W% U" |9 k */$ [+ _+ E8 f, J5 d: V6 p; k; ^ 7 ~" R6 k5 C. S# I' f#define TIM_SlaveMode_Reset ((uint16_t)0x0004)! X8 G9 p( Y; K; g+ _$ F #define TIM_SlaveMode_Gated ((uint16_t)0x0005)1 K W4 ]" T4 e3 X: I #define TIM_SlaveMode_Trigger ((uint16_t)0x0006), s4 t% w9 N) }( Q+ \ #define TIM_SlaveMode_External1 ((uint16_t)0x0007)" F+ m$ t" P2 W" E# V #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ 0 L0 U, a: g( P* k7 y ((MODE) == TIM_SlaveMode_Gated) || \ 9 v- c( G- k! i6 J0 d" N, Q1 @4 | ((MODE) == TIM_SlaveMode_Trigger) || \* |% x# J, W9 X) v# \ ((MODE) == TIM_SlaveMode_External1))复制代码2 N1 ? ^5 H* @& E TIM_Master_Slave_Mode- T- E- ^" }- ^" X 3 ?0 l- F/ H. g! A( j/** @defgroup TIM_Master_Slave_Mode ' u8 \' Y* E3 M1 f& w * @{ H& L1 _6 u# e+ L. c */ + m; l+ [ g; v& J- ^- m7 b! B" X! D8 l w0 T7 d" f #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)+ ~2 d2 n% @$ I# O/ f6 l #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) ]% D1 c( A" Q: w#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ 0 ?, M0 z) O t$ ~4 K ((STATE) == TIM_MasterSlaveMode_Disable))复制代码/ c k0 A: d$ n( ~3 H7 l TIM_Remap8 Z" r" l4 [: j+ Y. h3 W/ ?5 D # ~. F, A* q/ g# _: I/** @defgroup TIM_Remap # L% f9 J4 N* x/ A {% F * @{ $ [7 a/ H: a' F, s. c */$ s3 Y8 [; K& T, z& Z8 k ) |$ g- F2 F4 j- r( K" @( i4 @#define TIM2_TIM8_TRGO ((uint16_t)0x0000): b. D+ W- ^! g" O5 p5 ` #define TIM2_ETH_PTP ((uint16_t)0x0400)( M1 T8 F4 {- a6 H {- g3 P& Y \ #define TIM2_USBFS_SOF ((uint16_t)0x0800) 5 r# g7 l' e8 ?. P#define TIM2_USBHS_SOF ((uint16_t)0x0C00)) ?% E+ i9 w# x. ?1 P , J' D7 K& E( d#define TIM5_GPIO ((uint16_t)0x0000)* T, x0 H% b0 v #define TIM5_LSI ((uint16_t)0x0040)1 J% X7 ]2 k7 V9 c3 Y7 u( T& h #define TIM5_LSE ((uint16_t)0x0080)( y. a4 t+ A# {' a% O# I) s #define TIM5_RTC ((uint16_t)0x00C0)$ h& D* `4 C. c, T3 }0 O Z% ~! O- @2 T, ]$ ?: |& p#define TIM11_GPIO ((uint16_t)0x0000)2 V8 h( [* u: t4 L$ s9 X4 l* a3 F #define TIM11_HSE ((uint16_t)0x0002)8 n% ]' Q- ~4 j0 }) x5 [ * f& r4 d0 G3 W5 c4 {: \) O #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\ * V. r3 \" g* \- m v ((TIM_REMAP) == TIM2_ETH_PTP)||\* J: u' e& Y+ z0 b. {8 _ ((TIM_REMAP) == TIM2_USBFS_SOF)||\ : f+ ?0 c6 n/ p, |5 l- O ((TIM_REMAP) == TIM2_USBHS_SOF)||\ , o; x8 N s0 A( N" T _ ((TIM_REMAP) == TIM5_GPIO)||\+ ?& y* {5 r+ G j ((TIM_REMAP) == TIM5_LSI)||\ / x7 c9 x0 }7 }9 V; y2 j ((TIM_REMAP) == TIM5_LSE)||\ 9 @/ |8 t4 Y( A1 \; T6 T ((TIM_REMAP) == TIM5_RTC)||\ 0 e2 x4 h: S( p* q0 ]; ^% y ((TIM_REMAP) == TIM11_GPIO)||\ % r. r; U/ e7 `/ ~+ r) }; q ((TIM_REMAP) == TIM11_HSE))复制代码$ @0 P4 p* w. [ TIM_Flags s. V' s r- {) o! l" Z# v8 z ] ) `/ p+ f- h8 X/** @defgroup TIM_Flags ( O3 L2 s, p4 R- A3 F. o * @{ + h7 o2 m) F3 N A2 E# A5 w% w */ 3 i) C+ ^) ]; c+ V7 N) i* e5 z 2 n1 R" h" I8 j1 m#define TIM_FLAG_Update ((uint16_t)0x0001)1 J" C& d/ @; c8 ?* N4 f5 Z #define TIM_FLAG_CC1 ((uint16_t)0x0002) ! p; G/ W1 ?1 v; x% `+ l' o#define TIM_FLAG_CC2 ((uint16_t)0x0004)1 P' e, a" ~& W9 D9 e0 k+ d. t #define TIM_FLAG_CC3 ((uint16_t)0x0008)" h& z, l9 W8 M U, N- [ #define TIM_FLAG_CC4 ((uint16_t)0x0010)) f) M* | X% c2 Z #define TIM_FLAG_COM ((uint16_t)0x0020); V. X% x# h4 H3 T #define TIM_FLAG_Trigger ((uint16_t)0x0040) * x3 |7 ]7 g" C7 d% f6 m' `#define TIM_FLAG_Break ((uint16_t)0x0080)8 E1 A+ t+ R/ p& l3 F #define TIM_FLAG_CC1OF ((uint16_t)0x0200)" O1 P( |4 s4 s) J, n) O: S #define TIM_FLAG_CC2OF ((uint16_t)0x0400)- Y% v7 w: `) K; u* C$ x #define TIM_FLAG_CC3OF ((uint16_t)0x0800)- ~. y- m( R" w& d; e #define TIM_FLAG_CC4OF ((uint16_t)0x1000) 6 ?/ C3 h- ]1 ]+ c+ Z/ G#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \2 b* J' T/ E1 O ((FLAG) == TIM_FLAG_CC1) || \ $ @2 v9 b6 t, A5 | X$ y ((FLAG) == TIM_FLAG_CC2) || \9 ?1 j8 s' h) R. h4 |. G ((FLAG) == TIM_FLAG_CC3) || \- y& w' j. K% O$ {5 N1 g ((FLAG) == TIM_FLAG_CC4) || \ I) C" ?' F9 I2 t5 f* t! ~$ N; P ((FLAG) == TIM_FLAG_COM) || \4 J# I* z% {# W ((FLAG) == TIM_FLAG_Trigger) || \- I5 R# k* \( k6 w! z3 l' C ((FLAG) == TIM_FLAG_Break) || \2 A3 B8 u2 |7 q0 x ((FLAG) == TIM_FLAG_CC1OF) || \ 1 w6 P9 u+ V2 k, s0 Z ((FLAG) == TIM_FLAG_CC2OF) || \ 9 { |9 c' Q- R6 T ((FLAG) == TIM_FLAG_CC3OF) || \2 R* M8 `% C' l2 {5 a ((FLAG) == TIM_FLAG_CC4OF))复制代码 9 m# N3 S6 z }! p其它1 ~ w* E; i8 w: {% P1 f * W" {# { D9 v* L* U, h: m( l1 H /** @defgroup TIM_Input_Capture_Filer_Value + @4 s5 j/ s0 h * @{% u* q% r8 D+ w */8 L i. x+ H) c( T ( ?% s& h0 m& Q4 P: q6 q; w/ [6 M! p, G#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 0 S5 n u: @. I- U* k/** 2 i# C) Q8 q' K0 T- X * @}) k% Q! k) D7 ^3 s* h */ $ j/ Z" V; n+ j3 }3 i + A# M+ K( A: E) e6 V1 e: c+ m/** @defgroup TIM_External_Trigger_Filter . e0 A3 M: L$ `9 E" E( K4 [ * @{7 L9 V( _( V6 B */5 {+ I: L- b! ?. q/ ] 6 T/ M6 P( A7 |. {4 g #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF); f: _+ ]6 r; E9 ? /**( I9 H" d8 z; S: Y6 | * @}/ w0 f- Z; g8 V9 m; U1 i/ r G */ , i/ \: V0 v# @/ q3 O7 x8 \# T/ o/ J" p /** @defgroup TIM_Legacy 4 a/ p: d3 v2 u/ U) H8 s * @{ , G; |! w2 o5 ~1 U */ ) S5 R: x1 Q# E# k6 l6 V( w. Q5 Y" @; b1 T! Y |+ ~% @* l: W. t0 l #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer& z4 R( a' _5 U+ p3 e$ f: D. ]2 w #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers1 e- ^ n% Z& m4 u9 [1 L. e Y/ d #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers ( c5 q3 `+ j( e# p4 k, D#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers) A6 g! o4 @! b) Z& E R* L #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers9 c7 m" |1 C; t: [ #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers 8 M" o8 X2 \; }* D- _/ @0 l, }, C#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers0 @# S7 q; c7 H% r7 O7 | #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers9 b4 o1 k2 _6 h E, `1 e* ] #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers: R# |6 n( j( E+ O* ?, W, ^ #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers / _+ C0 n8 z2 ]. P1 K8 a#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers! D8 H, I. r) r4 d$ i #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers, v) |% Q7 P4 B' H #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers. {: @- E7 @$ O. P #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers# g1 m4 v( ~$ B8 q" ~1 p6 K0 Y$ M #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers . R4 S' R) {8 v; ~4 h( q#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers 8 J1 ~" W3 f- Y& b) C+ p#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers # M) j& M5 Q, P7 Q l#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers复制代码8 F, y7 P' B' Y; Z2 T 03. 相关函数 ( S. P3 F0 @3 L5 x2 r0 ^9 i/* TimeBase management ********************************************************/! [5 j) h0 k* p0 n B void TIM_DeInit(TIM_TypeDef* TIMx); ! w2 V# n3 {: I% pvoid TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); , S) v9 L P3 H3 L% evoid TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); ; q! z) o/ Q9 X0 y* T$ G- s% ~void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);! s9 |3 S+ a. g. J void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);5 c7 C& @. Q& `, s! z# r void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); 9 ?/ z: U$ ?: V$ E3 H' ovoid TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);7 ^$ u6 h9 v( t2 m$ {- \3 g. g4 A uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); 0 u" a9 q2 \2 U6 s# z# puint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); 5 h1 ] H0 `* A. E( v- D$ Nvoid TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);6 v2 V: W; c/ \4 k: W9 a" L void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); L8 ^) Z# Y+ K6 ]/ w3 s% c void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);# A. O8 D: E* p! ]+ o# y+ y0 R void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);) i/ Q! g2 {7 G) y" t void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); a X% C5 Q# M& I% k2 e) ~void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); u6 a1 k% E$ _0 u! `2 s1 w ! y' F4 l% p: o2 I S# B+ f% Q. } /* Output Compare management **************************************************/. p( y& I6 I9 e/ J7 K$ l void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);) J# W" @( S5 I# S; @) l void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);# i- b8 O/ Q% V+ H! q6 u5 v, E: s. P void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 8 U O* _6 N, k$ R) [; Wvoid TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 6 y: }5 N9 ^( s% q& W4 ^void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); 1 X" Z V0 K- Ivoid TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); # F: ^% T3 F2 r# M" A7 A& y: fvoid TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);! a: M/ Q+ c: k7 A, g( S void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); 7 v! r' n, ?9 \' f% n) z' Ivoid TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);1 N* K6 Z9 y& ]! M0 J8 [/ [ void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); 8 s+ g, q( @9 Z! Xvoid TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); # D) a% q# s3 a8 e; ~6 u+ mvoid TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);4 G) J, y* {9 q- N# s void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); % m) B, H: N! y$ d: w1 Y$ cvoid TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);8 X5 ?3 c. N' y \. b$ s5 R [ void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); + W: q9 |% U6 j9 o, n v, Cvoid TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); . p7 [8 ~0 j" L: _# W1 {! @void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);, U' j2 H. a$ q6 z$ e m; ?+ x void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); & s8 F& r n) s: P7 S; t# avoid TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);) o2 Z! J$ F# l) s Y void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); ! }- C; C9 Z- L6 F' c+ Z) [7 _void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 1 ^- W* s# [2 [. lvoid TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);$ F. w) X. G" K void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 8 l0 I+ u5 W% ?3 _& Mvoid TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);, n' B$ l, [6 e6 M( p6 ~ void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); ! D! V$ g$ i" l' ~void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);6 K+ n6 o! ]: {+ } void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);- y6 M* R, }9 C" }7 g2 v void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); 9 Q. | r1 t, x Y: o5 V4 W5 c3 @void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 4 _: {: A4 f- A" U qvoid TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);" ^5 M# [' T! X' H void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); i% B7 g1 U" D. v" O void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);( C( Q/ \" I2 j& j3 a void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);/ p% x2 f" D" w) g, ]6 G void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); 2 a- z- S+ j2 }- W& K6 mvoid TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); - c& u( X( }9 Y, l! A* R4 k; }0 C: B; X /* Input Capture management ***************************************************/ ; p/ Z1 m; Z+ i0 c9 mvoid TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);3 v4 O( J& `6 y7 y/ Y) S7 I. g void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); / c5 ]3 O! ]! hvoid TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);' d# ]) n3 Q# y4 I; E, F uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); ' ?9 W$ w9 E# M) ?3 Suint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);8 i2 ^# [5 [/ U uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); . b- Z5 `) f @( K) huint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); + b% w, S7 C! Kvoid TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);! e2 |% [- Q7 _0 _* T$ ^ void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);9 r5 W; z/ P. o3 P. R8 @: g* B void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 7 Y. }4 T! W& h3 k7 P' O; t+ kvoid TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);, S2 H+ ^5 z% Z7 `) \ + |5 ?" g4 E9 R7 I6 {6 K/ X/* Advanced-control timers (TIM1 and TIM8) specific features ******************/ $ E$ ~. T6 a: j2 s& T k5 I, ?void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);2 O# X2 m1 j s* H" u9 ~. P* o( [ void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);8 u0 B* ?1 Z1 s void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); 8 \- `3 a- @' [1 Kvoid TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);+ ?. V* s* h' Z% T void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);- O0 n- U5 [* O5 a! o# ] 6 ~0 f' ~/ z" [+ M* d /* Interrupts, DMA and flags management ***************************************/ 8 `, g4 N7 N& l3 Xvoid TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);) o: {% H- t; y5 [* U3 T: D) O void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);# Z8 J2 ^/ J3 z9 K4 ]( r FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);2 u( `3 f0 W% @; P' J. R" ^1 b void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);* s9 ?5 c% f/ S* h ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);; s t$ p) s2 w0 k3 y void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); , v3 U9 J0 D' ovoid TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);/ d8 Y, J% `! \8 D( @ void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);' X1 O0 R; l0 M$ w$ L+ w void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); & t0 c4 U$ b* w' m) ?( I 4 k6 ?6 {; }& |/ n9 I/ o* w5 O- R/* Clocks management **********************************************************/0 p. ~" ?* n9 |) X; j7 p: t void TIM_InternalClockConfig(TIM_TypeDef* TIMx);+ `4 b9 K/ R, A void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); 2 G( f: l6 w0 c; ]6 `$ R" Fvoid TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, 9 m( J" A6 p; y( [; D uint16_t TIM_ICPolarity, uint16_t ICFilter); 1 }. R1 b' y5 P- [- G. `+ l1 tvoid TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 4 R( W7 y3 i. w! F1 p% f uint16_t ExtTRGFilter);5 N& F0 u3 F: [* W, ` void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 0 D1 M4 Q* E" U' u& m uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); 3 a9 ]5 O; m5 r( u* |2 U$ }' |2 i# C" c! V. U /* Synchronization management *************************************************/ 8 w1 {, I1 L7 pvoid TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); # G, h8 C f" {void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); 1 M) N- x; J' g* e$ U0 e0 nvoid TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); x# L& ]( ~( ?" B void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); / z7 G: n; _5 d+ O: j+ @& z8 Nvoid TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,2 Q( n8 u% s+ b) l) e4 ` uint16_t ExtTRGFilter);# I0 V1 I% E9 f' G$ b" E+ y* ^, t 4 E! E4 P8 o2 ] /* Specific interface management **********************************************/ " r% K! C1 i( z4 c3 ^3 j' U' @void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - w0 U; N& k: I) Y uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); ' _* A0 ~" x0 a8 d" l3 ^7 Lvoid TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);/ L2 y; L5 K' F/ x/ s # r+ w" n d: t$ Z% e& _/* Specific remapping management **********************************************/ . L2 \- |) Q( w& Q, xvoid TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);复制代码 " V9 P/ M# E+ R6 Q$ k$ S: J3 M04. 结构体封装 ' h* ?. R6 y; o# f) g e/** 2 c' ]- R7 ?4 _$ x: @, h * @brief TIM4 Q4 b1 _0 d5 q4 q */+ Q, L2 e0 d: q7 U0 V* l 5 I5 w7 U: V. q) N3 Jtypedef struct # i. s+ ~9 Z4 f6 t. I% k9 E{ 0 |( c7 F/ B2 L8 o; j: }+ B __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */4 D' A% e. c) d/ {3 P8 p+ U0 n9 Y uint16_t RESERVED0; /*!< Reserved, 0x02 */8 r8 G& N5 B7 Q6 r0 S: g __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */( R, D0 w0 @! y$ [( n$ d. G uint16_t RESERVED1; /*!< Reserved, 0x06 */7 F g" n# a4 U& z g4 j __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */% M' r' e8 X6 Z9 f, J1 ^( r uint16_t RESERVED2; /*!< Reserved, 0x0A */$ f. ]3 ?! a( [5 p2 N+ b __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 0 F! |" @, D+ M4 Y uint16_t RESERVED3; /*!< Reserved, 0x0E */ 2 G/ P' g% R4 c' w __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 *// B5 |# i! g6 q/ j uint16_t RESERVED4; /*!< Reserved, 0x12 */8 u3 W) N! z6 Q4 T# z# H __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 5 _3 I% M/ `6 `0 _2 n uint16_t RESERVED5; /*!< Reserved, 0x16 */% ]0 i. [7 s' Y __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */$ O6 w. \& G, }" H: O' o uint16_t RESERVED6; /*!< Reserved, 0x1A */" @0 v4 n2 R5 @( `% U __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ % x) x; Y4 s1 G; {/ X uint16_t RESERVED7; /*!< Reserved, 0x1E */ W$ N) Y" k2 I __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ ; u2 P6 m& F9 v/ O8 q uint16_t RESERVED8; /*!< Reserved, 0x22 */" w) Z: ^; E5 {* I k, E __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */: r2 ^% n$ l7 q7 ?% D __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ 5 _! o% N8 b1 I$ N# ?* L uint16_t RESERVED9; /*!< Reserved, 0x2A */ + s: [! a3 u1 r2 _ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 9 R) E; m; X. g& n' z+ _: A& z __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 4 o& w0 @/ m/ y& I, W# Z7 L+ _7 k: l uint16_t RESERVED10; /*!< Reserved, 0x32 */3 i9 ^" g$ O" w) U" s __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 8 \/ F. m- B) l __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */2 r3 O; i- X) R) C __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */" n& d. n4 d6 F4 b __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ ! l- z2 Z: @! j! j* ~. `- V: m, K __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */% ?! } R; T& l9 U9 r uint16_t RESERVED11; /*!< Reserved, 0x46 */ " X' t2 n3 l n7 x __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */& ^; ?4 [. ^) H( z1 Q- K8 { uint16_t RESERVED12; /*!< Reserved, 0x4A */ 9 W8 l3 ?+ z! D) w2 `) e) f __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */0 M& R+ F9 p" K( P uint16_t RESERVED13; /*!< Reserved, 0x4E */ / m/ c7 C' A- [0 ~1 e. [$ k4 a __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */8 P$ b# D) [' r9 g uint16_t RESERVED14; /*!< Reserved, 0x52 */* U* l7 k9 _# E2 {3 F } TIM_TypeDef;复制代码 1 `% R- {! j* [8 N+ F+ |6 B; B+ c& W0 X6 V- E( B! V ! B+ |) y) G' C3 u1 H0 j7 j& ~, p) s

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STMCU小助手发布时间：2022-6-13 17:40

技术帖
文章封面:
文章简介:	STM32 定时器相关函数和类型

01. TIM概述
stm32f4xx_tim.h和stm32f4xx_tim.c文件中

02. 相关类型
TIM_TimeBaseInitTypeDef

/** % m1 [. W2 }5 Y# S/ |2 E: Z0 r9 {3 u
* @brief TIM Time Base Init structure definition 7 J0 L! v4 \; e
* @note This structure is used with all TIMx except for TIM6 and TIM7. * g* u2 f) T% P
*/3 v2 E* j8 s; }
. W. I) X: q" @- x0 B, J" g
typedef struct
' N0 S3 F2 S0 L) b0 g" J& s8 I* {
{
4 F( U8 c) O) ~
uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
j# s/ ?2 X2 j' m5 O
This parameter can be a number between 0x0000 and 0xFFFF */) l: U3 e. G4 H; o
, w7 o! w+ G$ a" w; K# U s2 s
uint16_t TIM_CounterMode; /*!< Specifies the counter mode.# P* j# ~2 @: J: }5 \" G; ?
This parameter can be a value of @ref TIM_Counter_Mode */
0 |. {4 f% }7 U6 g; I# Z
* M& O" A' {3 n6 Q: d& y4 s8 b
uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
5 q9 X, F' g+ n6 u% V' a) L* O; p
Auto-Reload Register at the next update event.
+ i3 w# B0 u% @) @% z: f" e
This parameter must be a number between 0x0000 and 0xFFFF. */ + X( C* m* e- f5 ^, N# q
7 R1 _& E8 @! g
uint16_t TIM_ClockDivision; /*!< Specifies the clock division.1 Q1 L3 P- o& V! L( P+ i5 l
This parameter can be a value of @ref TIM_Clock_Division_CKD */2 Z) ]! U7 L1 }2 h
" A5 L4 o5 n- Z4 [) M7 ~( }: d9 a
uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter$ ]3 F8 `7 S3 H1 ^8 P3 T3 z' g
reaches zero, an update event is generated and counting restarts k! g- j( f% s8 T4 n- Z
from the RCR value (N).4 B6 R) m3 I3 ?& k0 h
This means in PWM mode that (N+1) corresponds to:# V) [" y! i+ ]6 E
- the number of PWM periods in edge-aligned mode
7 L) n% d ~+ d) X- s% T4 B
- the number of half PWM period in center-aligned mode9 N v0 S, z7 o7 r! C1 b
This parameter must be a number between 0x00 and 0xFF. 9 O7 F- r" J; B
@note This parameter is valid only for TIM1 and TIM8. */7 i4 y% y; R$ G+ J
} TIM_TimeBaseInitTypeDef;

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TIM_OCInitTypeDef

/** 4 T7 o8 I& @# @6 H
* @brief TIM Output Compare Init structure definition
( u, W! V) ]/ o3 x, X: s
*/+ c& U" \1 E/ @8 u. G* m9 S
$ n( L# x/ r/ p: `6 [5 h+ T) C
typedef struct
. W* Z7 q9 O$ z) g( D
{6 \/ ~. X0 T' Z6 h G2 l4 v
uint16_t TIM_OCMode; /*!< Specifies the TIM mode., q6 N: O+ V$ c7 t
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */) t0 ? N% P; u) c$ p
# e+ O5 Q) j; J2 }6 T7 X1 ]
uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
9 @+ Q1 F& o. M$ l/ |
This parameter can be a value of @ref TIM_Output_Compare_State */* {) D5 A1 ]9 ]6 [2 ]" k
% E$ v& }, g* E5 |4 R' H
uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
+ `3 a- S1 X3 p" o) j6 J% i
This parameter can be a value of @ref TIM_Output_Compare_N_State
8 g1 R& M2 O! ^& X: K
@note This parameter is valid only for TIM1 and TIM8. */- {8 k6 |% l& T4 O' e4 V
- m8 O' {3 _4 z& ]3 w2 T$ E6 u
uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + |' ^! Y/ ]& F$ u8 P" S
This parameter can be a number between 0x0000 and 0xFFFF */
2 j+ a* C* a! Z3 i1 l/ D4 @
# ?- C) B; S( } V( P' w
uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.4 {- a7 Q: `- z7 X5 ~
This parameter can be a value of @ref TIM_Output_Compare_Polarity */* g5 {! v" \4 ^0 P8 F* A+ r, K
' j7 l! }3 |: Q1 w% A- M
uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
( G% ^: @; V' |9 {0 c% P
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
" S: X1 @" B! D0 F6 n, p; ^/ C
@note This parameter is valid only for TIM1 and TIM8. */" B) u6 _ s% G1 `' v/ O, Q3 P
) `' f7 o! U% W, t2 V
uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
1 n( ?$ p7 q7 `+ u2 z* N
This parameter can be a value of @ref TIM_Output_Compare_Idle_State, x# [4 m$ i) [6 B, j7 z0 y9 L* Y5 N
@note This parameter is valid only for TIM1 and TIM8. */4 I s3 {! Z5 C& I# U
7 i E' L7 l/ W# C
uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
% J7 y h) j- c9 ]
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State9 D+ w# c3 H/ ]1 s* r
@note This parameter is valid only for TIM1 and TIM8. */
! s+ ]% t) c. ^) Q, `; J
} TIM_OCInitTypeDef;

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TIM_ICInitTypeDef

/**
1 w% O$ y0 U# O' l' w. Q" H) t, t
* @brief TIM Input Capture Init structure definition
% M7 d2 l% w! ~) o# s/ q
*/
5 i" F5 l, N) t! T/ p
# n9 W2 m0 O5 e$ L# h
typedef struct
; e3 p* h7 p$ F. A6 S* v
{; e: \# ]2 X/ O% o
7 W- N5 J, R8 w3 E, [& d" E3 B: V5 {
uint16_t TIM_Channel; /*!< Specifies the TIM channel.
3 U7 g J1 K( s9 C" c+ Z
This parameter can be a value of @ref TIM_Channel */2 {: Y/ C8 Q2 c( a7 r
3 y) v+ q# u+ B$ l7 W3 L1 H% J) ^3 \3 T
uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal./ J8 C$ X) i6 n* x r$ y" X
This parameter can be a value of @ref TIM_Input_Capture_Polarity */9 O K( f; G+ d; w# o
- V/ M M: t+ X# O
uint16_t TIM_ICSelection; /*!< Specifies the input.
$ u# U! ?' H! W4 G; |
This parameter can be a value of @ref TIM_Input_Capture_Selection */
# j0 A) Z! x1 U# f( N
% C4 p7 p- t/ U1 b. h
uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.1 O' Q* z4 f; S
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */8 ~' E! `2 m0 ~0 r! \
2 t/ `/ E: P) g7 Q) ^- w: J
uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
T4 m/ y9 ]0 ~4 p9 g3 z. ]1 _- `
This parameter can be a number between 0x0 and 0xF */
$ j, y3 v" J( X! y
} TIM_ICInitTypeDef;

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TIM_BDTRInitTypeDef

/** 4 }! i% I- B) s) R$ N3 {6 y4 p
* @brief BDTR structure definition ( ?/ `! b* k2 O. S9 x( b, N
* @note This structure is used only with TIM1 and TIM8.
: f. | x8 Q" q& l' B
*/
8 s3 M2 }* J. o$ D) g5 ^: i5 ?
& |5 e7 d3 `8 ^+ _) H; F
typedef struct
. \# r6 w0 ]5 s9 w1 k6 z
{
# \8 i/ j' `$ B
5 q; w; C3 f0 \! C% V
uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.' l2 Y- h+ h% h. c* A
This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */, Q t; w& M# Y7 o
# ^) L4 I# F5 K0 }1 Z
uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.+ Q$ K% [. B8 \) m! _
This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */" K: n4 J" w9 T3 I9 P3 i; u: \
8 b8 Q5 l! l9 y! g$ }9 f3 J L
uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
7 k# j2 [; b% f
This parameter can be a value of @ref TIM_Lock_level */
* p P( T& B6 x& |
. h. m5 [( [9 l6 b
uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
" H! w1 o' ]. \3 _- Z8 U
switching-on of the outputs.
' L: a$ N _" f
This parameter can be a number between 0x00 and 0xFF */) ^; u% Q1 K' s$ M; _7 f N$ a
5 c$ M: u8 ?5 Q+ D
uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. - Y! w1 w0 y# c3 q n* q; x" b
This parameter can be a value of @ref TIM_Break_Input_enable_disable */6 E0 C; o/ h% t w: K9 I+ c
& ?2 b6 Z A' ] T5 D7 m6 y' |
uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.- Y; P/ c! k [. o" R3 l9 R0 I# b
This parameter can be a value of @ref TIM_Break_Polarity */
5 {0 I; `& M5 R7 ^. c& s! |
, k- D8 y/ @7 @$ n1 P. E- n" k
uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
7 q4 M- I+ N% |0 B
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */% @4 I, ^1 q! d' H# {+ a) P
} TIM_BDTRInitTypeDef;

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TIM

/** @defgroup TIM_Exported_constants
# {1 M7 f, }" a' Z* i! {8 a7 h8 v
* @{
4 a# M7 M. o! ?4 z% _* c
*/
" E& C+ X+ x: ^. _ s% `4 _+ N
/ |: i: |6 |0 I
#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \/ j1 F. t2 p3 M( P
((PERIPH) == TIM2) || \
, F A% v) v+ o- M, } Z
((PERIPH) == TIM3) || \
5 f4 g; j9 {8 A" y) c
((PERIPH) == TIM4) || \
: a2 [' z' c* k' ^6 P, w- u- Q
((PERIPH) == TIM5) || \
- b" _$ z4 V2 K2 v+ D/ F! |; V
((PERIPH) == TIM6) || \( g- M! u: `/ S1 @2 w! e6 l- P% ^
((PERIPH) == TIM7) || \ n% D1 s4 a2 _
((PERIPH) == TIM8) || \9 o/ K& `/ B$ f- n
((PERIPH) == TIM9) || \
7 Q1 }9 q% S2 P* R
((PERIPH) == TIM10) || \
7 p& L7 Q7 w2 m; {9 \
((PERIPH) == TIM11) || \
6 z8 d- V+ e) [( y
((PERIPH) == TIM12) || \
/ l Q/ V c$ F( K8 _. m
(((PERIPH) == TIM13) || \( s8 `+ l/ Z2 V' Q
((PERIPH) == TIM14))), q* y1 B/ J; p! \ i6 A
/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */ - P0 g: c- E. ~+ _: l
#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \: O% F" T; c. _- a) L4 C- E
((PERIPH) == TIM2) || \) x% N4 \1 [! b7 {- V7 Q
((PERIPH) == TIM3) || \5 r- K; e" e& C: g7 L
((PERIPH) == TIM4) || \! l- t# T: a* |" t# Y! O1 y
((PERIPH) == TIM5) || \
* N. L% C2 ]* k. e
((PERIPH) == TIM8) || \
; L' x: a, f! {0 j; ^% y; \3 o
((PERIPH) == TIM9) || \8 Y* |" I9 {4 C4 k9 M& X; Z
((PERIPH) == TIM10) || \" f! @) i% w- \- x: p
((PERIPH) == TIM11) || \* W% Q+ y' j9 u7 }
((PERIPH) == TIM12) || \
/ e4 K( }: M: p/ {! \" v4 m
((PERIPH) == TIM13) || \
6 [# S& q% e+ ^; Y4 `9 J; j. w: y
((PERIPH) == TIM14))
7 }3 j: {* L6 }! ^8 p2 R; U. G
/ d3 G& M' P/ V9 { F
/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */
7 z; E7 P% p$ T$ q2 J' |0 U
#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \! K) b$ @- u8 n8 r# A/ r5 ?
((PERIPH) == TIM2) || \
0 F8 [- H2 e; B: L' r
((PERIPH) == TIM3) || \
$ f8 j/ a% u& `% T0 @, u' {9 V
((PERIPH) == TIM4) || \
0 d: n* r. J- Q3 H3 @* f
((PERIPH) == TIM5) || \
( ]7 u$ w. l5 P2 z) q1 L
((PERIPH) == TIM8) || \% {5 D: |2 Q, @5 B7 s& O1 p
((PERIPH) == TIM9) || \+ b2 w. \# q* K2 e8 R
((PERIPH) == TIM12))
% j) F5 p9 B F% c' w
/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */
" w7 B9 c; S T; w% I& [
#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
1 ]: H2 ]7 t% ?( A
((PERIPH) == TIM2) || \
4 W) t4 ~" G/ z
((PERIPH) == TIM3) || \
+ o0 V# k# Y5 z7 ]3 P1 j' M5 O
((PERIPH) == TIM4) || \( f) O4 p2 _, E' Z5 e1 g T
((PERIPH) == TIM5) || \
- U( c% K8 x/ r) ]5 \8 ?
((PERIPH) == TIM8))
+ ?- z% g' [5 C6 u7 b$ M
/* LIST4: TIM1 and TIM8 */
. K' u- x0 m" y @! @. m3 z
#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \9 ~( J3 v W3 X. p4 E8 u
((PERIPH) == TIM8))- G5 C( ~* ~) f* u
/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
% ~! b _& j; K' P. P; t# ~. C
#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \" b6 ?. H3 {& j7 |$ e( y
((PERIPH) == TIM2) || \% ?0 c" Z6 _, s1 ~1 _
((PERIPH) == TIM3) || \
* a M5 C* ~* [6 V5 \: {; H. t: @( Z
((PERIPH) == TIM4) || \, m5 j( V. R. D' J( T' B
((PERIPH) == TIM5) || \
" Q- J# m$ a& N- f# z4 G
((PERIPH) == TIM6) || \/ j0 s' |$ G4 ?0 e
((PERIPH) == TIM7) || \
* ~0 Q, V$ S6 P* }6 }0 S
((PERIPH) == TIM8))" @: W9 F# v$ |$ D* a4 C5 s* j
/* LIST6: TIM2, TIM5 and TIM11 */
9 T$ d# W7 G; S2 h4 p
#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \7 _1 {; J# @- `/ V8 ^3 z ]
((TIMx) == TIM5) || \$ f' P$ \2 ~3 y* {$ A- B3 m
((TIMx) == TIM11))

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TIM_Output_Compare_and_PWM_modes

/** @defgroup TIM_Output_Compare_and_PWM_modes
5 V, i+ p+ p9 v) S
* @{
) t( U* a- P8 H$ u' S1 M
*/
; ^, h" h/ R' f/ F R5 x- L- P
2 {; M0 v$ X" \0 g6 i' ~, a) Q+ w% o
#define TIM_OCMode_Timing ((uint16_t)0x0000): L1 y5 h: k0 L/ J
#define TIM_OCMode_Active ((uint16_t)0x0010)1 F, I* W6 d) o
#define TIM_OCMode_Inactive ((uint16_t)0x0020)5 O+ Y. E; O2 u$ I3 O2 Z. M
#define TIM_OCMode_Toggle ((uint16_t)0x0030)
3 {3 \ l6 ~( H8 O( u! T1 g
#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
* u, O+ V/ Z; s+ R* T( ~3 G
#define TIM_OCMode_PWM2 ((uint16_t)0x0070)- y" \: S9 M1 }8 Y6 i8 V$ i9 n' J' O
#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
" `- P: z2 a: k
((MODE) == TIM_OCMode_Active) || \
$ q9 ]2 y4 U0 l. L5 n7 H: T6 `
((MODE) == TIM_OCMode_Inactive) || \% g I+ R* {+ G" L" m- M( X& _( x
((MODE) == TIM_OCMode_Toggle)|| \
5 @/ K8 Z9 b$ l" `
((MODE) == TIM_OCMode_PWM1) || \
! g% V. w7 B0 e& {
((MODE) == TIM_OCMode_PWM2))
! O. o6 W9 W( T1 ?
#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \# n, N3 L4 `, [0 l
((MODE) == TIM_OCMode_Active) || \% j7 K) N" M1 Y9 o2 ~5 A, v' ]
((MODE) == TIM_OCMode_Inactive) || \
0 I2 x, t$ v4 j8 Q# N3 ^6 J
((MODE) == TIM_OCMode_Toggle)|| \
/ S! g/ G3 E. P7 n+ J" a
((MODE) == TIM_OCMode_PWM1) || \
2 `# @9 {) O0 E# l: B' F2 A
((MODE) == TIM_OCMode_PWM2) || \7 e, a4 G9 f+ a( P
((MODE) == TIM_ForcedAction_Active) || \9 v2 j% `! X% F
((MODE) == TIM_ForcedAction_InActive))

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TIM_One_Pulse_Mode

/** @defgroup TIM_One_Pulse_Mode 5 M u6 R' K2 d- q0 i
* @{: } f) t; h) O |
*/9 X1 {# C) M! T; k; y( S
0 a' z) j& r6 D/ l/ u
#define TIM_OPMode_Single ((uint16_t)0x0008)8 O2 o6 i/ q/ ~( T7 h3 @# V
#define TIM_OPMode_Repetitive ((uint16_t)0x0000); p' m; q* A4 _, C
#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \4 y) K9 j- E( Y3 Z7 U
((MODE) == TIM_OPMode_Repetitive))

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TIM_Channel

/** @defgroup TIM_Channel ( x* |$ a9 m9 a4 D! T
* @{7 x3 ^- z; c0 ~! b3 p
*/
& w* V" {1 z. o6 J
" `" E; H. o0 K" `7 {
#define TIM_Channel_1 ((uint16_t)0x0000); N2 |: l0 P9 E# ^0 }
#define TIM_Channel_2 ((uint16_t)0x0004)
( X$ [# K0 k: O1 k* l( n' T
#define TIM_Channel_3 ((uint16_t)0x0008)
% Y* Z+ c& N; `/ A/ z
#define TIM_Channel_4 ((uint16_t)0x000C)/ O" z( p. J# x
% m, D2 L$ s9 U% `0 q
#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \5 [. d0 C! W8 r# c
((CHANNEL) == TIM_Channel_2) || \% g( M4 i. @# ]5 W8 T
((CHANNEL) == TIM_Channel_3) || \
) B7 w. O. T! C
((CHANNEL) == TIM_Channel_4))3 {: q1 u O1 y; z- l o7 U
- c# T W/ x+ _: I0 y
#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
3 q) I8 o6 P& B+ m
((CHANNEL) == TIM_Channel_2))+ H. n* A' x& l' i9 h
#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
* Z1 D, G9 o9 L- c
((CHANNEL) == TIM_Channel_2) || \
9 b; h( g: `- m2 c3 e E
((CHANNEL) == TIM_Channel_3))! T1 q" S$ Y D( R

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TIM_Clock_Division_CKD

/** @defgroup TIM_Clock_Division_CKD 0 D5 N/ S9 f& ^
* @{
" z3 m" H) |. B8 C+ J7 J/ J
*/
0 F# u& _$ G# J, g; X6 Q. Z
3 @/ T4 B$ S: D( `6 Z7 B/ L
#define TIM_CKD_DIV1 ((uint16_t)0x0000)* a0 h i q" q& l4 h
#define TIM_CKD_DIV2 ((uint16_t)0x0100)
" k% m; ]9 y0 c1 L
#define TIM_CKD_DIV4 ((uint16_t)0x0200)
# S, F; L4 i1 Y& Z, A2 u$ A# S
#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \: F7 \, E- ^( i2 l& Q {
((DIV) == TIM_CKD_DIV2) || \
2 d4 s/ b n. t% |2 z
((DIV) == TIM_CKD_DIV4))

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TIM_Counter_Mode

/** @defgroup TIM_Counter_Mode
8 `8 q& k* R. k9 e# _
* @{& I& x& o# M8 U* d& x* X% K
*/
; m: d. _! K: V* B/ |. e5 n
2 S* d. f1 y8 p& {7 ^
#define TIM_CounterMode_Up ((uint16_t)0x0000)$ s5 i( w, X0 | e9 M9 Y
#define TIM_CounterMode_Down ((uint16_t)0x0010)8 b6 F9 A" j" }4 F( x7 y
#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
& _- B( \7 X' j0 O( g0 K7 R Z9 C
#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
3 R4 m/ e. {- {! D8 \2 l3 ]: ^
#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)# c7 L" q0 u% \7 N9 v
#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
1 | N3 h, U4 e" U9 V' R* d
((MODE) == TIM_CounterMode_Down) || \
: w7 \3 P$ h2 }" W- B2 |
((MODE) == TIM_CounterMode_CenterAligned1) || \7 B* a, j$ z) O9 X3 x9 N, S
((MODE) == TIM_CounterMode_CenterAligned2) || \3 q; |! l; B: d1 G
((MODE) == TIM_CounterMode_CenterAligned3))

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TIM_Output_Compare_Polarity

/** @defgroup TIM_Output_Compare_Polarity
& `' }( C4 f, L4 Y
* @{& e1 ? r8 Q4 @( e0 I% j6 R
*/
1 Z0 M' m* d, C
2 X! w; h8 G4 G. M% v
#define TIM_OCPolarity_High ((uint16_t)0x0000)+ p I7 I2 _% O
#define TIM_OCPolarity_Low ((uint16_t)0x0002)
& X8 ?7 s) @% ^& D6 M0 l
#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \5 y! g/ t! l, W
((POLARITY) == TIM_OCPolarity_Low))

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TIM_Output_Compare_N_Polarity

/** @defgroup TIM_Output_Compare_N_Polarity ' F8 \2 J3 ^" k. [
* @{7 m; D# e+ H# ~% R
*/
& w2 B* W: S! k/ ]2 ?
' \( e+ x! M3 E7 R) z3 q% ?* l# U; {
#define TIM_OCNPolarity_High ((uint16_t)0x0000)
' N4 h, x. U) n1 s9 x: u) h. ~
#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
: Y( R; Z. C6 n* R- |+ R$ _
#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
$ c0 q; s7 V4 g
((POLARITY) == TIM_OCNPolarity_Low))

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TIM_Output_Compare_State

/** @defgroup TIM_Output_Compare_State
- Z6 a( \7 Y/ b* z
* @{2 M. R8 n# }: y5 g( w7 @" Y
*/
) u+ f3 T* l5 R4 S5 K. t
) I4 {4 C0 R& @" a# q
#define TIM_OutputState_Disable ((uint16_t)0x0000)$ H9 M; M% b, M4 H1 N
#define TIM_OutputState_Enable ((uint16_t)0x0001)' W9 W: a+ O3 u9 r0 ]
#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \1 c& T! B0 v# z0 j l
((STATE) == TIM_OutputState_Enable))

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TIM_Output_Compare_N_State

/** @defgroup TIM_Output_Compare_N_State
0 s" a4 Z1 w; [/ d8 T, x. l
* @{
) t! X/ k ?1 j. b' i7 _" q' ]
*/
3 h) c$ T0 J3 _' n1 W4 }
, F. _& v6 {( m+ w+ r2 U$ V) h4 F" A
#define TIM_OutputNState_Disable ((uint16_t)0x0000)
* A7 U9 p! c, d1 h' |( c
#define TIM_OutputNState_Enable ((uint16_t)0x0004)
7 R! A+ P4 O9 I8 l( y- X4 m
#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \+ O7 B0 |& v# U% c i: S
((STATE) == TIM_OutputNState_Enable))

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TIM_Capture_Compare_State

/** @defgroup TIM_Capture_Compare_State
" L- }: k4 ^) a# N1 ~8 H' `
* @{
6 K3 ^) f7 b' U: M8 g
*/6 {* a; o( i$ p: E* J5 E0 G1 k
5 d) o3 H- G8 Y6 d4 }% S% f
#define TIM_CCx_Enable ((uint16_t)0x0001)
" [5 @( O: R7 W6 L# K
#define TIM_CCx_Disable ((uint16_t)0x0000)! C( ^* v) P" a
#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \6 _' H9 u# S1 L
((CCX) == TIM_CCx_Disable))

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TIM_Capture_Compare_N_State

/** @defgroup TIM_Capture_Compare_N_State/ j& a8 m- F8 g
* @{
* _/ ?# m% G" \0 n
*/( l' w C& S9 K- }8 I* J2 A
* z9 o' m Z6 L" O; L: Z/ N
#define TIM_CCxN_Enable ((uint16_t)0x0004)0 `" C. v1 M3 n9 A* f3 m* y
#define TIM_CCxN_Disable ((uint16_t)0x0000)
3 {$ A3 ~/ O0 X$ u
#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \+ ?9 V% y' b8 ?- |
((CCXN) == TIM_CCxN_Disable))

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TIM_Break_Input_enable_disable

/** @defgroup TIM_Break_Input_enable_disable , a. s+ X+ V x' _: G3 Y- E* R
* @{
4 G; e/ j' Z, \1 L# q! U7 F
*/1 N* ^) o, b. p. Y' p0 m+ S0 x
2 Z6 n1 u3 p# I
#define TIM_Break_Enable ((uint16_t)0x1000)
" j+ w- J, r0 w- I; a
#define TIM_Break_Disable ((uint16_t)0x0000)& z% H0 y$ p$ g8 @3 a% z4 `; |+ D
#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \# Y& I `- Y ~
((STATE) == TIM_Break_Disable))

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TIM_Break_Polarity

/** @defgroup TIM_Break_Polarity
7 y# h$ H& @& N# z( K$ n) R
* @{
0 i+ s8 w& ?) u) G
*/
5 P2 u9 \2 L; R( V7 j4 i J
, O! L+ O% e5 w$ v, a3 {+ v7 p
#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
; q0 a, y, n- W8 y$ {% c
#define TIM_BreakPolarity_High ((uint16_t)0x2000)0 ^- D% C* ~: H1 b7 s1 y9 \. r+ n
#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \* B9 n5 f0 @* E# x/ b
((POLARITY) == TIM_BreakPolarity_High))

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TIM_AOE_Bit_Set_Reset

/** @defgroup TIM_AOE_Bit_Set_Reset
: J8 g% ?3 W0 t" Q5 e9 w1 ?/ c- N
* @{
# w3 b: }( I+ g0 W/ R
*/
' X+ D# d% i* U" d8 g& M
# N) B6 b6 o- x' _4 d/ r( x
#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)2 [4 Q: e; e8 I" q: n1 ~7 @
#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
( p h: W; V% K) Y/ O; T3 |4 D3 F+ [
#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \! Y) F8 M r' i
((STATE) == TIM_AutomaticOutput_Disable))

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TIM_Lock_level

/** @defgroup TIM_Lock_level
9 h% s3 z: z8 @. ?5 m
* @{ P# u7 n. k' Q; ^# q
*/
3 G3 C- H* N0 ]5 \7 b
2 I" j4 ^; C+ J) B8 O
#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)4 F8 p, Q' i3 q6 x b
#define TIM_LOCKLevel_1 ((uint16_t)0x0100)8 W# ]9 ?; G& E# u
#define TIM_LOCKLevel_2 ((uint16_t)0x0200)2 b# @" l- e, Q/ q" U$ W7 {+ E
#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
# v* N* V' N* E. Z9 d7 c
#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \- O# k" d& A# Z& j6 O. u
((LEVEL) == TIM_LOCKLevel_1) || \) h# J9 ^- O0 [. w0 ?8 Q; ^
((LEVEL) == TIM_LOCKLevel_2) || \" c" y# @6 i* o& h0 v) d! y2 h* z
((LEVEL) == TIM_LOCKLevel_3))

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TIM_OSSI_Off_State_Selection_for_Idle_mode_state

/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
- } K& r, y8 ]8 h' N/ U' |3 W
* @{; o1 o# p9 V" ]* ~
*/; H+ Y( U) C. ^$ n* Y. W
. G6 P+ v: k. {- k. J) ~5 F% l
#define TIM_OSSIState_Enable ((uint16_t)0x0400)
# M1 Q! T7 w! }5 `, P
#define TIM_OSSIState_Disable ((uint16_t)0x0000)# o; v& h+ c, d% ?, X$ }' [
#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
8 _- [7 i! a- x0 j
((STATE) == TIM_OSSIState_Disable))

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TIM_OSSR_Off_State_Selection_for_Run_mode_state

/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state3 w! V4 _7 p9 i5 v
* @{
7 L' z* @! E- G# n4 _
*/
B, M( P% K1 m8 w* I: L! \
; t9 C A5 v8 f$ |
#define TIM_OSSRState_Enable ((uint16_t)0x0800)
3 z& w/ Y! Y1 ]
#define TIM_OSSRState_Disable ((uint16_t)0x0000)' R! L- I) x- }# X/ s& Q3 e2 [
#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \5 \- i4 W x: [+ ?2 l. P. m
((STATE) == TIM_OSSRState_Disable))

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TIM_Output_Compare_Idle_State

/** @defgroup TIM_Output_Compare_Idle_State ; k8 M8 D, E0 C7 U3 H
* @{0 w j0 O; n% N$ r& m9 Y" X
*/8 h( X( ^0 R2 L# `6 T0 m" n% b
! I- X& @! a/ F" W6 E# R
#define TIM_OCIdleState_Set ((uint16_t)0x0100)
* E. Q U! J+ @1 [
#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
- p0 g1 y" T: k( @+ Q
#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
. d1 ^" A: s! s. E: v0 H$ \
((STATE) == TIM_OCIdleState_Reset))

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TIM_Output_Compare_N_Idle_State

/** @defgroup TIM_Output_Compare_N_Idle_State 8 `4 ~8 s6 U0 W- ]# M
* @{2 M. `" y. I3 q
*/) W& b4 c- R0 ^
0 p$ p( V$ C3 A5 e+ Z5 ^
#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
8 r3 C4 e- m2 z) @
#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)! q0 b7 h# q2 K
#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
& H" W: H" m! S: H
((STATE) == TIM_OCNIdleState_Reset))

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TIM_Input_Capture_Polarity

/** @defgroup TIM_Input_Capture_Polarity . Q$ j+ n9 H) J/ s( t
* @{2 N: ~, u; G& w% `8 e- _
*/1 n( j! X" a2 B6 K6 h
: ?" M" Q3 E0 r. \7 x
#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
/ m+ L! L0 U0 P# {$ [
#define TIM_ICPolarity_Falling ((uint16_t)0x0002)- t! Z- B0 D f6 J
#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)0 b2 E! {" A8 P) }/ V
#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \7 K" ^2 l7 h1 }7 d0 B: ?
((POLARITY) == TIM_ICPolarity_Falling)|| \+ N2 y3 k3 u( L
((POLARITY) == TIM_ICPolarity_BothEdge))

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TIM_Input_Capture_Selection

/** @defgroup TIM_Input_Capture_Selection
5 {: m$ f# @/ g) T. X
* @{' Y, p9 o5 @5 a$ |7 C
*/4 c8 @+ k' i# `( t* @
# V8 g, a3 P& w7 i7 |) t4 j
#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
6 ~8 A7 s7 z$ t0 B4 i
connected to IC1, IC2, IC3 or IC4, respectively */: `- d# q1 a1 B9 m, B+ ^
#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
& h' T; M% t- Q0 k- {8 {2 e5 ^
connected to IC2, IC1, IC4 or IC3, respectively. */
) p: m% x. p7 c: t- z- `( L7 d: F4 @
#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */( p5 _" B% t( v$ F9 \
#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \) H$ W2 v8 a4 N8 w3 l5 v3 |, C
((SELECTION) == TIM_ICSelection_IndirectTI) || \4 z; x/ Y. z1 a5 r B
((SELECTION) == TIM_ICSelection_TRC))

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TIM_Input_Capture_Prescaler

/** @defgroup TIM_Input_Capture_Prescaler ! W$ y% n" d; `
* @{0 ]. S# |) P1 J
*/
9 V0 D7 L2 z' a$ ~2 G
! Q) U p$ A9 j1 Q: y% h7 `
#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */: E: P, N$ R' c0 @
#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. *// \/ K# ~' ?' ^8 a# {7 a0 a7 R( S
#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */! N0 B; I9 M3 ?; d) ~! V8 G9 G5 ?
#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */; D' H( Q$ K1 Z- }/ v
#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
8 B$ G9 Y8 M% S
((PRESCALER) == TIM_ICPSC_DIV2) || $ E5 n$ O; $ n/ ]
((PRESCALER) == TIM_ICPSC_DIV4) || \8 I( K$ B. D4 F, g5 U8 N+ G
((PRESCALER) == TIM_ICPSC_DIV8))/ Y) }/ ^# }& `' `( ?

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TIM_interrupt_sources

/** @defgroup TIM_interrupt_sources
' h+ d2 s- |) _+ Q1 n( n# }- q
* @{
5 {. ~0 z% r, z8 T& S$ a
*/
1 ]. H$ J# A% U2 G9 n
, O1 d0 o4 F$ }
#define TIM_IT_Update ((uint16_t)0x0001); S7 g3 U# ]$ Z7 T
#define TIM_IT_CC1 ((uint16_t)0x0002)
8 z4 H% j3 a) Z+ D
#define TIM_IT_CC2 ((uint16_t)0x0004)4 D0 y/ j8 I/ S/ q( X# F6 t
#define TIM_IT_CC3 ((uint16_t)0x0008)% X) n+ z, Z( C
#define TIM_IT_CC4 ((uint16_t)0x0010)
. O j; }5 l) V2 D/ q) I3 A& M: Z* s
#define TIM_IT_COM ((uint16_t)0x0020)
/ v2 N% u$ W$ P T+ g0 b6 x
#define TIM_IT_Trigger ((uint16_t)0x0040)
* A: `2 L# B1 T
#define TIM_IT_Break ((uint16_t)0x0080)2 y8 C/ E& J, J+ e4 p- N+ N! c* C
#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))' y1 |' k; B# q- S9 i% B
) @: i* }% K0 a3 J7 N
#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \/ X7 p1 x3 U) R# q4 C& i2 ~
((IT) == TIM_IT_CC1) || \+ B9 c f, i7 R4 o
((IT) == TIM_IT_CC2) || \
& Y/ S+ C( i+ i
((IT) == TIM_IT_CC3) || \
; p# O. e; E4 t) u* r3 i2 V9 q( `
((IT) == TIM_IT_CC4) || \* T! ^! T. p* T3 y* v- T# W. ^, y
((IT) == TIM_IT_COM) || \, D, p( d- c% h* T' c9 R
((IT) == TIM_IT_Trigger) || \
6 ?) Q. Q; T: ]' A, p3 o( u1 a
((IT) == TIM_IT_Break)). n4 ^6 M- U& z7 ]8 d- C

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TIM_DMA_Base_address

/** @defgroup TIM_DMA_Base_address " y5 g* ~0 _$ \; i, j8 |) e
* @{- f* T3 N; Q/ r4 u
*/
( i7 g M0 A! p5 o' t
* V0 n, ]* J- G, R% W) C# p) N
#define TIM_DMABase_CR1 ((uint16_t)0x0000)# h2 `, i* X, O% j/ |$ d1 i
#define TIM_DMABase_CR2 ((uint16_t)0x0001)0 p1 L3 B- ?! ^1 z& D0 J
#define TIM_DMABase_SMCR ((uint16_t)0x0002)7 f3 O L" {& l" r
#define TIM_DMABase_DIER ((uint16_t)0x0003)
& c+ R" b9 b+ L+ `
#define TIM_DMABase_SR ((uint16_t)0x0004)
4 T$ s& k2 J2 _6 ]8 F* E6 A
#define TIM_DMABase_EGR ((uint16_t)0x0005)
$ l% O7 Y7 O- Y; b7 l
#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)4 Q# n% l6 W( m" A b! l& W
#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
4 E( G- g8 r' P* w% f P. }
#define TIM_DMABase_CCER ((uint16_t)0x0008)1 W4 T6 r( ~) Z
#define TIM_DMABase_CNT ((uint16_t)0x0009)
% M7 L3 L3 l- J! `6 i$ G2 J1 M
#define TIM_DMABase_PSC ((uint16_t)0x000A)4 t4 f& s5 o- |( p5 g
#define TIM_DMABase_ARR ((uint16_t)0x000B)
- ]7 M- a5 a& ` i+ T4 S
#define TIM_DMABase_RCR ((uint16_t)0x000C)
& R2 _. Z' S4 I7 ?& q4 j5 X9 h
#define TIM_DMABase_CCR1 ((uint16_t)0x000D)9 f; r( L! R& E( ^" J i
#define TIM_DMABase_CCR2 ((uint16_t)0x000E): h9 P: L" |0 k& o2 C
#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
/ g5 x2 @/ {8 Z2 }0 L+ d
#define TIM_DMABase_CCR4 ((uint16_t)0x0010)% u5 {/ a% d7 X
#define TIM_DMABase_BDTR ((uint16_t)0x0011)
6 Z$ R" p; z. C2 p
#define TIM_DMABase_DCR ((uint16_t)0x0012)1 ^! ?( M9 M/ v* R4 M8 B9 f- o
#define TIM_DMABase_OR ((uint16_t)0x0013)/ T. \9 u+ ~* W G
#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
- B/ h5 e* c, A! t& m8 g
((BASE) == TIM_DMABase_CR2) || \/ j1 Y$ g# ~/ [# R) y9 d" Y
((BASE) == TIM_DMABase_SMCR) || \
% F; l6 v m1 ?# a. {& t
((BASE) == TIM_DMABase_DIER) || \
6 t& Q% Y) Y7 |) o5 ]. ?4 Z5 w( _
((BASE) == TIM_DMABase_SR) || \, x3 a' s; W3 H, n
((BASE) == TIM_DMABase_EGR) || \, @; s! L6 u% b
((BASE) == TIM_DMABase_CCMR1) || \ ]$ }" z0 F1 w; }1 ~( Y6 u1 l
((BASE) == TIM_DMABase_CCMR2) || \$ e+ M# y J" F" [+ ? e6 ?" h
((BASE) == TIM_DMABase_CCER) || \
0 ~8 B! Z# I/ Y1 Y
((BASE) == TIM_DMABase_CNT) || \
" q8 Z* l9 l$ d E7 P( F) b
((BASE) == TIM_DMABase_PSC) || \
" i. m( h r5 V, h, {
((BASE) == TIM_DMABase_ARR) || \
; ?2 S+ _, @ M {, Q* B" m
((BASE) == TIM_DMABase_RCR) || \
; e2 ]/ D1 w( y5 b4 ^6 o
((BASE) == TIM_DMABase_CCR1) || \! L1 O3 ?# v, V: u
((BASE) == TIM_DMABase_CCR2) || \% H' ?7 r) d; _7 r5 V2 W+ E
((BASE) == TIM_DMABase_CCR3) || \6 C) |8 s! ^6 K9 ]9 a: p% D$ K1 v
((BASE) == TIM_DMABase_CCR4) || \
# \8 ^" p( B2 H' w
((BASE) == TIM_DMABase_BDTR) || \* z' g- V! F9 L6 b/ K9 e5 F- B5 t/ ~
((BASE) == TIM_DMABase_DCR) || \
" ~( U3 L% B! |) B2 z8 j
((BASE) == TIM_DMABase_OR))

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TIM_DMA_Burst_Length

/** @defgroup TIM_DMA_Burst_Length # O O3 [% t0 ^9 J5 M
* @{
# S8 u" f: }; Q' {# ^; w2 f7 H* H1 V
*/1 y- x Z1 k1 f; H* i' N
. `* B9 L- O0 ?( w% u( o6 }
#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)) E- m) Y( l$ ]- Z
#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
0 |' S( T3 Q: v0 T
#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)! N, E# v$ Y# x, k
#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)7 j+ C; C, m% e8 O
#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
$ S0 p$ N; Q# C1 ^- L' @' \
#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)* v' N6 U& K5 _' O' T
#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)0 F2 t, N m# \- D s
#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)/ a. a. h t" E/ u! M- a# r4 B5 y0 w
#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)1 O! G x0 Z# A
#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)# C3 |% m' m; \- W7 `
#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
2 z. m* f/ P# Y0 B
#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
0 }) r9 ?6 N8 e. R0 v- \* e
#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)& M5 ?/ P& j- ?6 D7 F
#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
, p; P4 t, x/ e
#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
# n% L5 m9 |. H4 v
#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
% u# _" A1 R; T: W, L' h% l! e L
#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
: H4 b+ s( g8 n" H* |
#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) k7 s9 \$ g* G' k; {- v8 H V
#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \: o" M* _+ [. C; A; z( G; ^
((LENGTH) == TIM_DMABurstLength_2Transfers) || \8 @6 D' s# }7 q9 `
((LENGTH) == TIM_DMABurstLength_3Transfers) || \3 D5 ?7 [4 U* x- F! J: Q0 D. H, T* t
((LENGTH) == TIM_DMABurstLength_4Transfers) || \8 T! ^+ t2 E) [& O4 n
((LENGTH) == TIM_DMABurstLength_5Transfers) || \
$ B* _; x8 y' c9 K4 F0 t
((LENGTH) == TIM_DMABurstLength_6Transfers) || \
. j! E. L( e }0 y' o5 |
((LENGTH) == TIM_DMABurstLength_7Transfers) || \
. K. ?7 x9 S+ ?. U( l6 m
((LENGTH) == TIM_DMABurstLength_8Transfers) || \
& |) x6 X# a5 T4 A; p+ R! m
((LENGTH) == TIM_DMABurstLength_9Transfers) || \
; ^! ^$ Y) Y) l* \+ [
((LENGTH) == TIM_DMABurstLength_10Transfers) || \
. X9 z$ w% Z" N$ C% j* s0 D
((LENGTH) == TIM_DMABurstLength_11Transfers) || \
0 ^9 C3 [8 [: u% C1 d% i6 T
((LENGTH) == TIM_DMABurstLength_12Transfers) || \* Q; c8 U, }# {' M N8 [3 w& q
((LENGTH) == TIM_DMABurstLength_13Transfers) || \
. _9 c' y8 o: Y1 D# K& V
((LENGTH) == TIM_DMABurstLength_14Transfers) || \, m; H; i7 J- _, L! B
((LENGTH) == TIM_DMABurstLength_15Transfers) || \# u: s3 k8 t; D% T
((LENGTH) == TIM_DMABurstLength_16Transfers) || \# M- s/ y! x' Q7 m1 {
((LENGTH) == TIM_DMABurstLength_17Transfers) || \
8 U6 c( X9 ]- G* p
((LENGTH) == TIM_DMABurstLength_18Transfers))

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TIM_DMA_sources

/** @defgroup TIM_DMA_sources
8 F4 S' H) ` \
* @{ f9 ?4 f; r9 z% G! \, M) G) p0 v1 U
*/
P, h3 K+ \0 X& D5 V
' ` M$ H" A+ {' z5 h; _* u
#define TIM_DMA_Update ((uint16_t)0x0100)) Z1 Y& n+ j9 e
#define TIM_DMA_CC1 ((uint16_t)0x0200)
8 E1 t! c+ C/ B* i) W
#define TIM_DMA_CC2 ((uint16_t)0x0400)
( O0 a5 w0 L H# L; U$ h1 ^
#define TIM_DMA_CC3 ((uint16_t)0x0800)
7 b) G2 p6 H9 }" ]2 M) i
#define TIM_DMA_CC4 ((uint16_t)0x1000)( U/ V4 R* \; P- K1 X' n
#define TIM_DMA_COM ((uint16_t)0x2000)
- s$ g8 u M/ {# i) ?( x9 u
#define TIM_DMA_Trigger ((uint16_t)0x4000), `3 A8 m8 I! {! }( s9 [# {6 n B
#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))

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TIM_External_Trigger_Prescaler

/** @defgroup TIM_External_Trigger_Prescaler
% M' |& j' ]/ C$ d# Y
* @{+ J) l8 [4 U8 w( N" t
*/( y' L( R8 Y: x8 B" X* E& Q
, i0 v6 U+ `5 T: }* ]
#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)+ q0 y T6 [1 Y, l; W9 V3 H
#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000): c, z( U) {2 j$ h
#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
( R- Q% a% e0 s9 I' d0 c$ w( B
#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)( I! W# u2 `3 ?6 X- ~- ]" s; P* u- D9 n
#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
4 c: ]: n% d* B
((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \9 J8 G8 }- Q1 r7 M+ E" y
((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \. x% I1 O* ]6 w1 I
((PRESCALER) == TIM_ExtTRGPSC_DIV8))

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TIM_Internal_Trigger_Selection

/** @defgroup TIM_Internal_Trigger_Selection : r. T# b( S. b' {$ @
* @{# f" V+ X0 R7 c8 U# d
*/
6 C3 U4 b w. L; `$ C% j
1 y Z' T3 U( V. y4 h" z
#define TIM_TS_ITR0 ((uint16_t)0x0000)
( J1 l. b$ [8 U8 e& E; x6 v# B
#define TIM_TS_ITR1 ((uint16_t)0x0010)$ W5 H! K# y2 B& Z" F) e5 z; Z
#define TIM_TS_ITR2 ((uint16_t)0x0020)
4 Z7 {/ Q/ a: R0 T- H
#define TIM_TS_ITR3 ((uint16_t)0x0030)# Y6 }4 Z, W2 f
#define TIM_TS_TI1F_ED ((uint16_t)0x0040)0 B8 J$ l, x* R' g
#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
$ l4 w; H* j2 I- l. y
#define TIM_TS_TI2FP2 ((uint16_t)0x0060)! q4 C( T' p/ ^/ r4 ^% w
#define TIM_TS_ETRF ((uint16_t)0x0070)1 I2 E9 ] Q/ k( [% y2 l5 V
#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
; T- L1 k5 [$ `2 r2 [9 O+ h% F
((SELECTION) == TIM_TS_ITR1) || \
1 u( H5 ]+ Z% P) R/ j& ~- }
((SELECTION) == TIM_TS_ITR2) || \
\9 D2 D* a8 S
((SELECTION) == TIM_TS_ITR3) || \ W5 W# p+ l( k: _
((SELECTION) == TIM_TS_TI1F_ED) || \* i$ a( h& Z1 w' p* l; t
((SELECTION) == TIM_TS_TI1FP1) || \
8 y. O6 [5 \4 a* h D2 i
((SELECTION) == TIM_TS_TI2FP2) || \- k1 b& l6 c) m
((SELECTION) == TIM_TS_ETRF))& X8 o# o2 J: X; i1 G
#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \9 C* c4 d, r6 J9 F4 M
((SELECTION) == TIM_TS_ITR1) || \' j2 w( U( N( k6 }+ |( c: M
((SELECTION) == TIM_TS_ITR2) || \
4 K; v3 S6 g1 m, _4 b* a
((SELECTION) == TIM_TS_ITR3))

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TIM_TIx_External_Clock_Source

/** @defgroup TIM_TIx_External_Clock_Source 4 b4 i0 i4 \2 `; ~
* @{4 B$ x2 T( I3 |6 h- w
*/
0 T) X7 J% w- J$ L; m- d+ ~
7 C; z7 R! L* s0 i" H( A
#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
" R* Z0 L- C3 h+ E) u
#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)/ Z. L% j# P+ Z% X
#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
0 r. @+ R/ W1 c* O$ Z& @; S+ L

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TIM_External_Trigger_Polarity

/** @defgroup TIM_External_Trigger_Polarity
7 n( Z6 A. e) i
* @{* }% [" c% j- M: g- V' |" X
*/
) X& @9 s `' {; b
#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)9 [9 z1 e: @( ^% \5 C
#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)- U' n8 t; B: h% P1 ?* v; a
#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
~9 w8 a% @$ F& y8 W; X
((POLARITY) == TIM_ExtTRGPolarity_NonInverted))

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TIM_Prescaler_Reload_Mode

/** @defgroup TIM_Prescaler_Reload_Mode
( V! u+ n7 w; ~; R1 _4 i# ?
* @{! ? H# X( a& ~3 z
*/
; K( U6 h1 C9 O* E
" J3 x1 {' _) y8 Z2 J9 b: ^
#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
X$ V# H, |8 |7 r, Y9 Y7 S
#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
1 M# _7 q1 {" Q* D
#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \) i% V$ c5 Z! L- {
((RELOAD) == TIM_PSCReloadMode_Immediate))

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TIM_Forced_Action

/** @defgroup TIM_Forced_Action * G9 h. X8 T/ H& Q
* @{
8 i; P4 u; Y) }6 L
*/
$ n- }; T& c( b v9 O/ g& O
& F& W" w0 q1 }- b2 b
#define TIM_ForcedAction_Active ((uint16_t)0x0050)' c5 l# G7 P' c$ [
#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
) P s2 |5 D0 Z" F; h0 D9 ?# z
#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \! G& P4 R, H w
((ACTION) == TIM_ForcedAction_InActive))

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TIM_Encoder_Mode

/** @defgroup TIM_Encoder_Mode + Y; \$ @' s: Y) t6 x! x6 j
* @{' L% z. b' |3 H
*/
" J% i% W1 ]/ f1 f# M! ~
2 D( I- t; W0 B5 J* O6 o
#define TIM_EncoderMode_TI1 ((uint16_t)0x0001). @" u2 X# ?) Q1 A/ \, W0 N
#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)5 R! l4 t7 Q) ?' ]/ V6 G, k: g. I
#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
' t/ i- e {9 m6 Y" x
#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
3 z& J. q( o( w2 P1 F* a6 C
((MODE) == TIM_EncoderMode_TI2) || \! C' }, |$ C3 v, _5 ]9 H. f; [( L
((MODE) == TIM_EncoderMode_TI12))

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TIM_Event_Source

/** @defgroup TIM_Event_Source % r2 B9 K( k7 E l
* @{# x& P2 V6 z5 F3 x. b- q6 N( [1 L
*/2 D2 f! M( X, a" U3 Q# j
* k, P) w+ A; D$ X1 ?& y) o
#define TIM_EventSource_Update ((uint16_t)0x0001)
; a4 F6 K9 G& [7 ~ W
#define TIM_EventSource_CC1 ((uint16_t)0x0002)
* ?) D. U- }8 D* T9 K' x
#define TIM_EventSource_CC2 ((uint16_t)0x0004)
& P* T8 Q7 C/ P
#define TIM_EventSource_CC3 ((uint16_t)0x0008)& v4 v& w. }1 L
#define TIM_EventSource_CC4 ((uint16_t)0x0010)
# M& e4 R" y& p2 C6 _# X/ ?% n* r
#define TIM_EventSource_COM ((uint16_t)0x0020)
, o. l/ n Y1 q/ m4 X
#define TIM_EventSource_Trigger ((uint16_t)0x0040)5 m9 V# q# z) d3 v: e5 S" H
#define TIM_EventSource_Break ((uint16_t)0x0080)
( W8 s9 Q7 P. r8 b8 H% M
#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))

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TIM_Update_Source

/** @defgroup TIM_Update_Source : a1 R5 R4 W5 n/ R+ |
* @{
. _1 q7 t. i, |' Z( z' X
*/8 p: N( ?: H+ z" I( m; m
3 e; Z i' `, L: P
#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
$ f( X' ]' q" B& p& l' M8 z
or the setting of UG bit, or an update generation
/ H: G# I U ]3 ~% { N7 Q9 B
through the slave mode controller. */
! O6 |. `- g$ t
#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ M c- q; I+ |& a# H+ n! k
#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \1 g. ?3 b9 u V4 d/ q: Y: K
((SOURCE) == TIM_UpdateSource_Regular))

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TIM_Output_Compare_Preload_State

/** @defgroup TIM_Output_Compare_Preload_State . ]. d8 h8 T# F! \ X! i
* @{
' ?6 a/ P- y' M% A! X
*/2 F, V$ l1 `& c+ J+ X" Q+ {
9 u8 I E r( s# A
#define TIM_OCPreload_Enable ((uint16_t)0x0008)" K/ k8 N+ S! r4 L' U7 f6 g5 T& m
#define TIM_OCPreload_Disable ((uint16_t)0x0000)* Z1 ~+ ?% }' q! l' L
#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \$ K; G5 F- |; C. t2 D
((STATE) == TIM_OCPreload_Disable))

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TIM_Output_Compare_Fast_State

/** @defgroup TIM_Output_Compare_Fast_State * ]2 C! l6 ]8 x/ D0 h; `
* @{: c1 c! N0 c" K. r% Q8 W' D3 j
*/" g6 m" F4 k& }' O4 Y
b/ b; B# L3 E( n8 {+ `. c
#define TIM_OCFast_Enable ((uint16_t)0x0004)
% }* j1 I2 e, c; I: Q, F: o
#define TIM_OCFast_Disable ((uint16_t)0x0000)3 i! `7 [; R) W2 t
#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
0 q7 m* H; b4 O. j
((STATE) == TIM_OCFast_Disable))

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TIM_Output_Compare_Clear_State

/** @defgroup TIM_Output_Compare_Clear_State
' }$ w4 \# R- f4 w% K( i* p
* @{# ~' n7 y0 l6 ~% |7 N) ^" e* t
*/' ?* {0 a! [1 _/ t- e+ V
/ u! {0 j' k" L3 j4 d
#define TIM_OCClear_Enable ((uint16_t)0x0080)7 B" s1 }. s* x+ F6 f/ \' ^1 G
#define TIM_OCClear_Disable ((uint16_t)0x0000)% T6 T# B* s% W+ I4 [( s
#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
0 l& h! I8 E+ _; p) f
((STATE) == TIM_OCClear_Disable))

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TIM_Trigger_Output_Source

/** @defgroup TIM_Trigger_Output_Source
: S* L$ y/ K2 Y) U7 _
* @{3 ^1 j" M" N; n2 _1 Y+ B( n
*/
+ V. Z' P& D% N) E
0 n5 E: r$ x8 r' c9 g' w1 V. r4 D
#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
: g; }6 g: J) I# u' x3 o! P/ d
#define TIM_TRGOSource_Enable ((uint16_t)0x0010)* u) v& g$ H1 R% N- z1 x
#define TIM_TRGOSource_Update ((uint16_t)0x0020)2 ^& m/ `+ T3 l' H. P' h4 \
#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
% V, s6 l: s: N1 ]
#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)& W5 d6 O6 u4 d- K
#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)+ ~. X& M1 h4 R9 X0 y- l! Q7 @: J
#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)" G, B0 }5 T& X) L
#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
+ e d% w1 ~; B. x5 L9 {
#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
Y: v# N+ B0 j5 R/ ^
((SOURCE) == TIM_TRGOSource_Enable) || \* g0 z! q9 g; g& k7 P0 V
((SOURCE) == TIM_TRGOSource_Update) || \' Y1 V6 v4 T o$ ?3 f* |
((SOURCE) == TIM_TRGOSource_OC1) || \ M, I: C. }' ]3 {0 ~; q& j, U
((SOURCE) == TIM_TRGOSource_OC1Ref) || \
5 u9 Q' {5 ?, S' Z6 n4 N) o6 _2 Q7 T
((SOURCE) == TIM_TRGOSource_OC2Ref) || \6 F# l2 f4 b7 T* K* w3 W+ L
((SOURCE) == TIM_TRGOSource_OC3Ref) || \- t7 ~$ N) b: ^. d. |% S$ o
((SOURCE) == TIM_TRGOSource_OC4Ref))

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TIM_Slave_Mode

/** @defgroup TIM_Slave_Mode
- t, t4 o- c3 w0 K8 v. }2 x. g
* @{9 i% q* W% U" |9 k
*/$ [+ _+ E8 f, J5 d: V6 p; k; ^
7 ~" R6 k5 C. S# I' f
#define TIM_SlaveMode_Reset ((uint16_t)0x0004)! X8 G9 p( Y; K; g+ _$ F
#define TIM_SlaveMode_Gated ((uint16_t)0x0005)1 K W4 ]" T4 e3 X: I
#define TIM_SlaveMode_Trigger ((uint16_t)0x0006), s4 t% w9 N) }( Q+ \
#define TIM_SlaveMode_External1 ((uint16_t)0x0007)" F+ m$ t" P2 W" E# V
#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
0 L0 U, a: g( P* k7 y
((MODE) == TIM_SlaveMode_Gated) || \
9 v- c( G- k! i6 J0 d" N, Q1 @4 |
((MODE) == TIM_SlaveMode_Trigger) || \* |% x# J, W9 X) v# \
((MODE) == TIM_SlaveMode_External1))

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TIM_Master_Slave_Mode

/** @defgroup TIM_Master_Slave_Mode
' u8 \' Y* E3 M1 f& w
* @{ H& L1 _6 u# e+ L. c
*/
+ m; l+ [ g; v& J- ^- m
7 b! B" X! D8 l w0 T7 d" f
#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)+ ~2 d2 n% @$ I# O/ f6 l
#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
]% D1 c( A" Q: w
#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
0 ?, M0 z) O t$ ~4 K
((STATE) == TIM_MasterSlaveMode_Disable))

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TIM_Remap

/** @defgroup TIM_Remap
# L% f9 J4 N* x/ A {% F
* @{
$ [7 a/ H: a' F, s. c
*/$ s3 Y8 [; K& T, z& Z8 k
) |$ g- F2 F4 j- r( K" @( i4 @
#define TIM2_TIM8_TRGO ((uint16_t)0x0000): b. D+ W- ^! g" O5 p5 `
#define TIM2_ETH_PTP ((uint16_t)0x0400)( M1 T8 F4 {- a6 H {- g3 P& Y \
#define TIM2_USBFS_SOF ((uint16_t)0x0800)
5 r# g7 l' e8 ?. P
#define TIM2_USBHS_SOF ((uint16_t)0x0C00)) ?% E+ i9 w# x. ?1 P
, J' D7 K& E( d
#define TIM5_GPIO ((uint16_t)0x0000)* T, x0 H% b0 v
#define TIM5_LSI ((uint16_t)0x0040)1 J% X7 ]2 k7 V9 c3 Y7 u( T& h
#define TIM5_LSE ((uint16_t)0x0080)( y. a4 t+ A# {' a% O# I) s
#define TIM5_RTC ((uint16_t)0x00C0)$ h& D* `4 C. c, T3 }0 O
Z% ~! O- @2 T, ]$ ?: |& p
#define TIM11_GPIO ((uint16_t)0x0000)2 V8 h( [* u: t4 L$ s9 X4 l* a3 F
#define TIM11_HSE ((uint16_t)0x0002)8 n% ]' Q- ~4 j0 }) x5 [
* f& r4 d0 G3 W5 c4 {: \) O
#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\
* V. r3 \" g* \- m v
((TIM_REMAP) == TIM2_ETH_PTP)||\* J: u' e& Y+ z0 b. {8 _
((TIM_REMAP) == TIM2_USBFS_SOF)||\
: f+ ?0 c6 n/ p, |5 l- O
((TIM_REMAP) == TIM2_USBHS_SOF)||\
, o; x8 N s0 A( N" T _
((TIM_REMAP) == TIM5_GPIO)||\+ ?& y* {5 r+ G j
((TIM_REMAP) == TIM5_LSI)||\
/ x7 c9 x0 }7 }9 V; y2 j
((TIM_REMAP) == TIM5_LSE)||\
9 @/ |8 t4 Y( A1 \; T6 T
((TIM_REMAP) == TIM5_RTC)||\
0 e2 x4 h: S( p* q0 ]; ^% y
((TIM_REMAP) == TIM11_GPIO)||\
% r. r; U/ e7 `/ ~+ r) }; q
((TIM_REMAP) == TIM11_HSE))

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TIM_Flags

/** @defgroup TIM_Flags
( O3 L2 s, p4 R- A3 F. o
* @{
+ h7 o2 m) F3 N A2 E# A5 w% w
*/
3 i) C+ ^) ]; c+ V7 N) i* e5 z
2 n1 R" h" I8 j1 m
#define TIM_FLAG_Update ((uint16_t)0x0001)1 J" C& d/ @; c8 ?* N4 f5 Z
#define TIM_FLAG_CC1 ((uint16_t)0x0002)
! p; G/ W1 ?1 v; x% `+ l' o
#define TIM_FLAG_CC2 ((uint16_t)0x0004)1 P' e, a" ~& W9 D9 e0 k+ d. t
#define TIM_FLAG_CC3 ((uint16_t)0x0008)" h& z, l9 W8 M U, N- [
#define TIM_FLAG_CC4 ((uint16_t)0x0010)) f) M* | X% c2 Z
#define TIM_FLAG_COM ((uint16_t)0x0020); V. X% x# h4 H3 T
#define TIM_FLAG_Trigger ((uint16_t)0x0040)
* x3 |7 ]7 g" C7 d% f6 m' `
#define TIM_FLAG_Break ((uint16_t)0x0080)8 E1 A+ t+ R/ p& l3 F
#define TIM_FLAG_CC1OF ((uint16_t)0x0200)" O1 P( |4 s4 s) J, n) O: S
#define TIM_FLAG_CC2OF ((uint16_t)0x0400)- Y% v7 w: `) K; u* C$ x
#define TIM_FLAG_CC3OF ((uint16_t)0x0800)- ~. y- m( R" w& d; e
#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
6 ?/ C3 h- ]1 ]+ c+ Z/ G
#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \2 b* J' T/ E1 O
((FLAG) == TIM_FLAG_CC1) || \
$ @2 v9 b6 t, A5 | X$ y
((FLAG) == TIM_FLAG_CC2) || \9 ?1 j8 s' h) R. h4 |. G
((FLAG) == TIM_FLAG_CC3) || \- y& w' j. K% O$ {5 N1 g
((FLAG) == TIM_FLAG_CC4) || \ I) C" ?' F9 I2 t5 f* t! ~$ N; P
((FLAG) == TIM_FLAG_COM) || \4 J# I* z% {# W
((FLAG) == TIM_FLAG_Trigger) || \- I5 R# k* \( k6 w! z3 l' C
((FLAG) == TIM_FLAG_Break) || \2 A3 B8 u2 |7 q0 x
((FLAG) == TIM_FLAG_CC1OF) || \
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((FLAG) == TIM_FLAG_CC2OF) || \
9 { |9 c' Q- R6 T
((FLAG) == TIM_FLAG_CC3OF) || \2 R* M8 `% C' l2 {5 a
((FLAG) == TIM_FLAG_CC4OF))

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其它

/** @defgroup TIM_Input_Capture_Filer_Value
+ @4 s5 j/ s0 h
* @{% u* q% r8 D+ w
*/8 L i. x+ H) c( T
( ?% s& h0 m& Q4 P: q6 q; w/ [6 M! p, G
#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
0 S5 n u: @. I- U* k
/**
2 i# C) Q8 q' K0 T- X
* @}) k% Q! k) D7 ^3 s* h
*/
$ j/ Z" V; n+ j3 }3 i
+ A# M+ K( A: E) e6 V1 e: c+ m
/** @defgroup TIM_External_Trigger_Filter . e0 A3 M: L$ `9 E" E( K4 [
* @{7 L9 V( _( V6 B
*/5 {+ I: L- b! ?. q/ ]
6 T/ M6 P( A7 |. {4 g
#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF); f: _+ ]6 r; E9 ?
/**( I9 H" d8 z; S: Y6 |
* @}/ w0 f- Z; g8 V9 m; U1 i/ r G
*/
, i/ \: V0 v# @/ q3 O
7 x8 \# T/ o/ J" p
/** @defgroup TIM_Legacy
4 a/ p: d3 v2 u/ U) H8 s
* @{
, G; |! w2 o5 ~1 U
*/
) S5 R: x1 Q# E# k6 l6 V( w. Q
5 Y" @; b1 T! Y |+ ~% @* l: W. t0 l
#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer& z4 R( a' _5 U+ p3 e$ f: D. ]2 w
#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers1 e- ^ n% Z& m4 u9 [1 L. e Y/ d
#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
( c5 q3 `+ j( e# p4 k, D
#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers) A6 g! o4 @! b) Z& E R* L
#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers9 c7 m" |1 C; t: [
#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
8 M" o8 X2 \; }* D- _/ @0 l, }, C
#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers0 @# S7 q; c7 H% r7 O7 |
#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers9 b4 o1 k2 _6 h E, `1 e* ]
#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers: R# |6 n( j( E+ O* ?, W, ^
#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
/ _+ C0 n8 z2 ]. P1 K8 a
#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers! D8 H, I. r) r4 d$ i
#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers, v) |% Q7 P4 B' H
#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers. {: @- E7 @$ O. P
#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers# g1 m4 v( ~$ B8 q" ~1 p6 K0 Y$ M
#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
. R4 S' R) {8 v; ~4 h( q
#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
8 J1 ~" W3 f- Y& b) C+ p
#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
# M) j& M5 Q, P7 Q l
#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers

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03. 相关函数

/* TimeBase management ********************************************************/! [5 j) h0 k* p0 n B
void TIM_DeInit(TIM_TypeDef* TIMx);
! w2 V# n3 {: I% p
void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
, S) v9 L P3 H3 L% e
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
; q! z) o/ Q9 X0 y* T$ G- s% ~
void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);! s9 |3 S+ a. g. J
void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);5 c7 C& @. Q& `, s! z# r
void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
9 ?/ z: U$ ?: V$ E3 H' o
void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);7 ^$ u6 h9 v( t2 m$ {- \3 g. g4 A
uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
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uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
5 h1 ] H0 `* A. E( v- D$ N
void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);6 v2 V: W; c/ \4 k: W9 a" L
void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); L8 ^) Z# Y+ K6 ]/ w3 s% c
void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);# A. O8 D: E* p! ]+ o# y+ y0 R
void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);) i/ Q! g2 {7 G) y" t
void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
a X% C5 Q# M& I% k2 e) ~
void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); u6 a1 k% E$ _0 u! `2 s1 w
! y' F4 l% p: o2 I S# B+ f% Q. }
/* Output Compare management **************************************************/. p( y& I6 I9 e/ J7 K$ l
void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);) J# W" @( S5 I# S; @) l
void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);# i- b8 O/ Q% V+ H! q6 u5 v, E: s. P
void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
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void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
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void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
1 X" Z V0 K- I
void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
# F: ^% T3 F2 r# M" A7 A& y: f
void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);! a: M/ Q+ c: k7 A, g( S
void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
7 v! r' n, ?9 \' f% n) z' I
void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);1 N* K6 Z9 y& ]! M0 J8 [/ [
void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
8 s+ g, q( @9 Z! X
void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
# D) a% q# s3 a8 e; ~6 u+ m
void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);4 G) J, y* {9 q- N# s
void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
% m) B, H: N! y$ d: w1 Y$ c
void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);8 X5 ?3 c. N' y \. b$ s5 R [
void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
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void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
. p7 [8 ~0 j" L: _# W1 {! @
void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);, U' j2 H. a$ q6 z$ e m; ?+ x
void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
& s8 F& r n) s: P7 S; t# a
void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);) o2 Z! J$ F# l) s Y
void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
! }- C; C9 Z- L6 F' c+ Z) [7 _
void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1 ^- W* s# [2 [. l
void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);$ F. w) X. G" K
void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
8 l0 I+ u5 W% ?3 _& M
void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);, n' B$ l, [6 e6 M( p6 ~
void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
! D! V$ g$ i" l' ~
void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);6 K+ n6 o! ]: {+ }
void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);- y6 M* R, }9 C" }7 g2 v
void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
9 Q. | r1 t, x Y: o5 V4 W5 c3 @
void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
4 _: {: A4 f- A" U q
void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);" ^5 M# [' T! X' H
void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); i% B7 g1 U" D. v" O
void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);( C( Q/ \" I2 j& j3 a
void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);/ p% x2 f" D" w) g, ]6 G
void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
2 a- z- S+ j2 }- W& K6 m
void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
- c& u( X( }9 Y
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/* Input Capture management ***************************************************/
; p/ Z1 m; Z+ i0 c9 m
void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);3 v4 O( J& `6 y7 y/ Y) S7 I. g
void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
/ c5 ]3 O! ]! h
void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);' d# ]) n3 Q# y4 I; E, F
uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
' ?9 W$ w9 E# M) ?3 S
uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);8 i2 ^# [5 [/ U
uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
. b- Z5 `) f @( K) h
uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
+ b% w, S7 C! K
void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);! e2 |% [- Q7 _0 _* T$ ^
void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);9 r5 W; z/ P. o3 P. R8 @: g* B
void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
7 Y. }4 T! W& h3 k7 P' O; t+ k
void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);, S2 H+ ^5 z% Z7 `) \
+ |5 ?" g4 E9 R7 I6 {6 K/ X
/* Advanced-control timers (TIM1 and TIM8) specific features ******************/
$ E$ ~. T6 a: j2 s& T k5 I, ?
void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);2 O# X2 m1 j s* H" u9 ~. P* o( [
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);8 u0 B* ?1 Z1 s
void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
8 \- `3 a- @' [1 K
void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);+ ?. V* s* h' Z% T
void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);- O0 n- U5 [* O5 a! o# ]
6 ~0 f' ~/ z" [+ M* d
/* Interrupts, DMA and flags management ***************************************/
8 `, g4 N7 N& l3 X
void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);) o: {% H- t; y5 [* U3 T: D) O
void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);# Z8 J2 ^/ J3 z9 K4 ]( r
FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);2 u( `3 f0 W% @; P' J. R" ^1 b
void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);* s9 ?5 c% f/ S* h
ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);; s t$ p) s2 w0 k3 y
void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
, v3 U9 J0 D' o
void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);/ d8 Y, J% `! \8 D( @
void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);' X1 O0 R; l0 M$ w$ L+ w
void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
& t0 c4 U$ b* w' m) ?( I
4 k6 ?6 {; }& |/ n9 I/ o* w5 O- R
/* Clocks management **********************************************************/0 p. ~" ?* n9 |) X; j7 p: t
void TIM_InternalClockConfig(TIM_TypeDef* TIMx);+ `4 b9 K/ R, A
void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
2 G( f: l6 w0 c; ]6 `$ R" F
void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
9 m( J" A6 p; y( [; D
uint16_t TIM_ICPolarity, uint16_t ICFilter);
1 }. R1 b' y5 P- [- G. `+ l1 t
void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
4 R( W7 y3 i. w! F1 p% f
uint16_t ExtTRGFilter);5 N& F0 u3 F: [* W, `
void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 0 D1 M4 Q* E" U' u& m
uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
3 a9 ]5 O; m5 r( u
* |2 U$ }' |2 i# C" c! V. U
/* Synchronization management *************************************************/
8 w1 {, I1 L7 p
void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
# G, h8 C f" {
void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
1 M) N- x; J' g* e$ U0 e0 n
void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); x# L& ]( ~( ?" B
void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
/ z7 G: n; _5 d+ O: j+ @& z8 N
void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,2 Q( n8 u% s+ b) l) e4 `
uint16_t ExtTRGFilter);# I0 V1 I% E9 f' G$ b" E+ y* ^, t
4 E! E4 P8 o2 ]
/* Specific interface management **********************************************/
" r% K! C1 i( z4 c3 ^3 j' U' @
void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
- w0 U; N& k: I) Y
uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
' _* A0 ~" x0 a8 d" l3 ^7 L
void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);/ L2 y; L5 K' F/ x/ s
# r+ w" n d: t$ Z% e& _
/* Specific remapping management **********************************************/
. L2 \- |) Q( w& Q, x
void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);

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04. 结构体封装

/**
2 c' ]- R7 ?4 _$ x: @, h
* @brief TIM4 Q4 b1 _0 d5 q4 q
*/+ Q, L2 e0 d: q7 U0 V* l
5 I5 w7 U: V. q) N3 J
typedef struct
# i. s+ ~9 Z4 f6 t. I% k9 E
{
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__IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */4 D' A% e. c) d/ {3 P8 p+ U0 n9 Y
uint16_t RESERVED0; /*!< Reserved, 0x02 */8 r8 G& N5 B7 Q6 r0 S: g
__IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */( R, D0 w0 @! y$ [( n$ d. G
uint16_t RESERVED1; /*!< Reserved, 0x06 */7 F g" n# a4 U& z g4 j
__IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */% M' r' e8 X6 Z9 f, J1 ^( r
uint16_t RESERVED2; /*!< Reserved, 0x0A */$ f. ]3 ?! a( [5 p2 N+ b
__IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
0 F! |" @, D+ M4 Y
uint16_t RESERVED3; /*!< Reserved, 0x0E */
2 G/ P' g% R4 c' w
__IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 *// B5 |# i! g6 q/ j
uint16_t RESERVED4; /*!< Reserved, 0x12 */8 u3 W) N! z6 Q4 T# z# H
__IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
5 _3 I% M/ `6 `0 _2 n
uint16_t RESERVED5; /*!< Reserved, 0x16 */% ]0 i. [7 s' Y
__IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */$ O6 w. \& G, }" H: O' o
uint16_t RESERVED6; /*!< Reserved, 0x1A */" @0 v4 n2 R5 @( `% U
__IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
% x) x; Y4 s1 G; {/ X
uint16_t RESERVED7; /*!< Reserved, 0x1E */
W$ N) Y" k2 I
__IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
; u2 P6 m& F9 v/ O8 q
uint16_t RESERVED8; /*!< Reserved, 0x22 */" w) Z: ^; E5 {* I k, E
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */: r2 ^% n$ l7 q7 ?% D
__IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
5 _! o% N8 b1 I$ N# ?* L
uint16_t RESERVED9; /*!< Reserved, 0x2A */
+ s: [! a3 u1 r2 _
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
9 R) E; m; X. g& n' z+ _: A& z
__IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
4 o& w0 @/ m/ y& I, W# Z7 L+ _7 k: l
uint16_t RESERVED10; /*!< Reserved, 0x32 */3 i9 ^" g$ O" w) U" s
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
8 \/ F. m- B) l
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */2 r3 O; i- X) R) C
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */" n& d. n4 d6 F4 b
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
! l- z2 Z: @! j! j* ~. `- V: m, K
__IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */% ?! } R; T& l9 U9 r
uint16_t RESERVED11; /*!< Reserved, 0x46 */
" X' t2 n3 l n7 x
__IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */& ^; ?4 [. ^) H( z1 Q- K8 {
uint16_t RESERVED12; /*!< Reserved, 0x4A */
9 W8 l3 ?+ z! D) w2 `) e) f
__IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */0 M& R+ F9 p" K( P
uint16_t RESERVED13; /*!< Reserved, 0x4E */
/ m/ c7 C' A- [0 ~1 e. [$ k4 a
__IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */8 P$ b# D) [' r9 g
uint16_t RESERVED14; /*!< Reserved, 0x52 */* U* l7 k9 _# E2 {3 F
} TIM_TypeDef;