STM32H7时钟配置问题
5 w. U. g5 Z7 {7 h; U设备:stm32h735VGxxx
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问题:STM32时钟配置不正确,一直没法启动。7 v% o; N6 b. ^+ P+ C4 J
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解决:原因是配置时钟的一些参数超出的范围,所以配置导致不成功。) |8 [, q' H' Y0 N
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下面是H735的时钟的一些解释,其中 Fvco 是有范围的,这边从文档上面查到,FVCO的最大配置值为836M,所以配置的时候一定要注意。
3 R# i8 O. S/ Z# u I" T并且plln, pllm,pllp,pllq,这些都是有范围限制的,如果配置错误,那么芯片将不会正常运行
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- * 时钟设置函数
8 u9 `/ `4 j7 x7 w4 n - * Fvco: VCO 频率
0 b3 ?5 s& Z; G7 ~5 | - * Fsys: 系统时钟频率,也是 PLL1 的 p 分频输出时钟频率
+ v# ^4 s, D3 d$ K - * Fq: PLL1 的 q 分频输出时钟频率, d+ |4 s% i: {! {( ]. Q0 {, X7 g( y
- * Fs: PLL 输入时钟频率,可以是 HSI,CSI,HSE 等. ' k! w, J9 J: z/ e- u: g8 x
- * Fvco = Fs * (plln/pllm) = (Fs/DIVM)*DIVN;
! x+ D5 Q! F. v: P - * Fsys = Fvco/pllp = Fs * (plln/(pllm * pllp));. T6 x( E/ E; z( S5 s( b
- * Fq = Fvco/pllq = Fs * (plln/(pllm * pllq));
; Y% I0 u/ n* Z - *
6 g0 r0 ?) \9 [# g* s - *
9 k9 `5 B. H% B( H - * plln: PLL1 倍频系数(PLL 倍频),取值范围:4~512./ ~' ]7 b, y7 d4 i% A5 p: |9 P
- * pllm: PLL1 预分频系数(进 PLL 之前的分频),取值范围:2~56.0 \4 z5 ^+ `" d) U
- * pllp: PLL1 的 p 分频系数(PLL 之后的分频),分频后作为系统时钟,取值范围:2~128) D9 B2 x% ?# U& H' |3 C' ~' V
- * pllq: PLL1 的 q 分频系数(PLL 之后的分频),取值范围:1~128.7 D- }9 ?7 }3 o7 k1 ?. W
- * CPU 频率(rcc_c_ck) = sys_d1cpre_ck = 400Mhz
9 { R7 V! Q4 t/ M+ D - * rcc_aclk = rcc_hclk3 = 200Mhz
9 U4 {" m( h2 K1 A, T* H3 c. n - * AHB1/2/3/4(rcc_hclk1/2/3/4) = 200Mhz " }/ ]" P( p, P; [; P8 z0 G3 D
- * APB1/2/3/4(rcc_pclk1/2/3/4) = 100Mhz ; q( a& t' {/ a3 Q& S9 w
- * FMC 时钟频率 =pll2_r_ck=((25/25) * 512/2) = 256Mhz7 K( c1 v- ?% ~: v
- * . W6 x* w/ W$ |8 ]
- * Example:
- L6 v% F$ P& \0 g, y/ b' p - * 外部晶振为 25M 的时候,推荐值:plln = 160, pllm = 5, pllp = 2, pllq = 4.
0 B- h" a+ Z3 D* o; } o) x9 ^ - * 得到:Fvco = 25 * (160/5) = 800Mhz' L9 R) }% p7 g4 ^9 t
- * Fsys = 800/2 = 400Mhz; K1 E- Y, I1 l9 K0 B
- * Fq = 800/4 = 200Mhz
9 o' P3 x# J& }" ` q9 C* M5 o - */
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o* M2 v$ r2 t5 A6 {+ V- #define PLL_N 160# R4 M& k+ x# X5 A9 v9 U
- #define PLL_M 5
8 R3 s: g5 n4 }1 U* |% X - #define PLL_P 23 D: V& B/ r1 n" e7 P$ e. k
- #define PLL_Q 4+ M# w) W. Y7 D6 ~' N6 T- L
- 1 K& L# M9 j6 f$ ^
- // 时钟设置函数
1 d: M0 \0 d" Q8 c5 P" |5 u - static void SystemClock_Config(void)
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. Z9 x% f7 t4 o3 R) n( e: u O - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};9 f; Q8 [: ]) c- m% h
- RCC_OscInitTypeDef RCC_OscInitStruct = {0};/ H/ a/ q$ L! z; @3 J; S. A
- HAL_StatusTypeDef ret = HAL_OK;
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- /*!< Supply configuration update enable */) S) Q- X1 W& Q: R; |
- HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);5 G+ q# {( j5 m( u% N; |( b$ T' J
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- /* The voltage scaling allows optimizing the power consumption when the device is, a! s; t2 O$ U* O) U
- clocked below the maximum system frequency, to update the voltage scaling value
8 M c6 m2 ~+ y, P4 G1 G - regarding system frequency refer to product datasheet. */) {) Z9 G5 e7 ~3 J, G; S7 K/ B
- __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);0 \& D/ K: _" v
- 9 ^$ j: S! A- g3 E6 ~) }
- while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
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$ b7 D) e. h/ y" f( l- /* Enable HSE Oscillator and activate PLL with HSE as source */4 F% d9 o) W5 V" M2 V
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
! [+ A2 Z; d1 u8 R5 _' \, L( l6 t1 B - RCC_OscInitStruct.HSEState = RCC_HSE_ON;
7 ]# w5 Y; T1 }1 s6 @* G4 M - RCC_OscInitStruct.HSIState = RCC_HSI_OFF;) a% f% }, q+ W1 J c
- RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
5 D0 M4 X( z3 ]: \5 ?. D - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;! K/ e$ w- L( \# b# n% u4 `* g
- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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* G$ a+ A. B* S, ?2 e2 w- RCC_OscInitStruct.PLL.PLLM = PLL_M;! z6 ?8 H2 L2 `" u1 m
- RCC_OscInitStruct.PLL.PLLN = PLL_N;
0 b7 z5 Z$ Q0 H3 l. ] - RCC_OscInitStruct.PLL.PLLFRACN = 0;- w5 C1 e$ R& y6 E" u) D) O$ v
- RCC_OscInitStruct.PLL.PLLP = PLL_P;
; C% z8 _. h! T8 g7 u% ~ - RCC_OscInitStruct.PLL.PLLR = 2;
9 w4 Y' b- g; R* j" i+ W& m) G$ T - RCC_OscInitStruct.PLL.PLLQ = PLL_Q;3 R8 j* B$ N0 N, o
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- RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
: P# c' Z: ]# I* X3 d- i J" r5 r - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;7 F" T# y: k9 X* }
- ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
' [2 U* g- e+ A( M' u - if(ret != HAL_OK)
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. R! b$ i# e& Z6 S7 C8 u- U" F9 H0 Y - while(1) {};
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- /* Select PLL as system clock source and configure bus clocks dividers */6 g9 {' ^( H, |( \( B
- RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \4 y& \; P- Z( P$ }% N* O0 d7 [
- RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1);
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- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;2 v+ G/ G# ?9 x2 ` X
- RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;+ ]6 m0 o2 m1 D/ u0 }( ~) f
- RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
, |# Q( w6 R/ _3 q - RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;8 Z6 y' T5 ], X& w) V; g6 [% ]5 g
- RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
\' k5 a) c) Z5 B- h0 I0 C5 y% V - RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
9 `" [- j4 L5 n4 a% v - RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;5 r1 G- _! }% k7 w5 }/ Z4 R
- ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
: r4 i4 y1 h( z5 \& L - if(ret != HAL_OK)9 b; D( i8 k" O! t+ X
- {
2 y% W: j+ R! [ ]) {+ c! i3 C - while(1) {};- d% f$ o8 K0 d9 O* f, t) ]
- }
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