【经验分享】STM32 时钟相关函数和类型

STMCU小助手 · 2022-03-31T03:00:00+00:00

01. 概述 4 ~6 t. y1 {3 K' y! Z$ `在 STM32F4 标准固件库里，时钟源的选择以及时钟使能等函数都是在 RCC 相关固件库文件 stm32f4xx_rcc.h 和 stm32f4xx_rcc.c 中声明和定义的。大家打开 stm32f4xx_rcc.h 文件可以看到文件开头有很多宏定义标识符，然后是一系列时钟配置和时钟使能函数申明。这些函数大致可以归结为三类，一类是外设时钟使能函数，一类是时钟源和分频因子配置函数，还有一类是外设复位函数。当然还有几个获取时钟源配置的函数。) U3 o: l' d/ S& x( ~" [ % G6 U3 V, g; }: g' \* u' r, r 02. 相关类型! p( a( ^* ~1 K# h5 C RCC_ClocksTypeDef: Z* O1 a6 Q7 @& @" l7 D 7 p7 w( T/ Z) L% X0 m! j /* Exported types ------------------------------------------------------------*/ 9 `6 d9 \* U$ D8 t1 a* |4 Wtypedef struct1 X/ z6 l }+ Y; B X1 A( x1 Z {5 s0 O6 a) ~ t; H uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ 7 P& I8 z2 u) M" K( ~ uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */8 o. w& b% s, \ uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ 9 H/ Z9 y5 Z. U+ i( C) @2 g uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */6 `7 I, B/ v) T3 \ }RCC_ClocksTypeDef;复制代码1 q6 }! x" u U+ @/ w RCC_HSE_configuration, O/ V, B# F: O$ b& Q a4 N 3 Z3 J: X' h. O5 A9 G" T /** @defgroup RCC_HSE_configuration o/ x7 y$ W2 H% ` * @{) V* S5 ?8 U1 C ^. x: B */ $ E* J8 f! G2 r3 S#define RCC_HSE_OFF ((uint8_t)0x00); p: U0 O. @3 l# V #define RCC_HSE_ON ((uint8_t)0x01) ; g5 u0 _6 u+ `, A) f3 _#define RCC_HSE_Bypass ((uint8_t)0x05)2 m/ W# `: o6 D1 X #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - w3 _5 o2 j$ q/ a! P ((HSE) == RCC_HSE_Bypass))复制代码 ) O( _0 H4 O+ [% g, HRCC_LSE_Dual_Mode_Selection K" q( `6 h0 O) R! H: S7 m n' c6 z6 m) T. @' v+ L /** @defgroup RCC_LSE_Dual_Mode_Selection1 H- x, p/ S0 z" I5 ^/ M9 o' w * @{( s% K4 L1 s. f0 |5 N- I% U */, ?3 T4 j, r8 Z4 T: Q' N #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) 3 I0 r! I4 |- o, y2 H9 ~. S5 Q#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) : w% u: K7 I/ h# D- K2 L( t$ A#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \! ?# h3 r/ y: A6 ]5 O& I: Y9 {, M- q/ y ((MODE) == RCC_LSE_HIGHDRIVE_MODE))复制代码 $ K/ ]9 X5 f1 |$ d3 QRCC_PLLSAIDivR_Factor* u; h' x/ o$ [& ]8 L- g1 Q6 V 9 a$ d ^. M! c/ A9 | /** @defgroup RCC_PLLSAIDivR_Factor 6 l9 |+ O/ W& z) {1 E * @{ ) |" f* r8 S% E* P. D q */ / G% ]9 W! [" n#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)( n! ^! w# f m, Z8 Q6 B7 ~ #define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)* Q- ^: L3 f0 K# `& H #define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)7 G, s% b1 G( j2 [/ x #define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000) 3 t0 ~# |. { m: \1 e! F#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\! T y* n8 T+ x+ w ((VALUE) == RCC_PLLSAIDivR_Div4) ||\ 9 x: `+ Z- d1 X1 ? |( y ((VALUE) == RCC_PLLSAIDivR_Div8) ||\ ; }4 m7 a% h$ r9 F! p3 x7 H9 N ((VALUE) == RCC_PLLSAIDivR_Div16))复制代码; j# l$ K" O0 u, Y& w" ~ RCC_PLL_Clock_Source9 H1 Z- B- p: V: r) d/ W : `1 ]; K# h% Y+ @9 a' Y/** @defgroup RCC_PLL_Clock_Source 2 O. t2 j$ t' ^- d* U q' T4 [ * @{ ; |, Z4 ?6 V% X) t& I3 b# e */% v6 h1 G2 a4 C: b3 U. A/ e #define RCC_PLLSource_HSI ((uint32_t)0x00000000)$ v1 @/ F% I8 L' W2 r' l; e- S" c #define RCC_PLLSource_HSE ((uint32_t)0x00400000)+ m' m' J; C6 z& X# n+ K8 e- b2 k #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \* B% z0 B$ x" i/ _( @; }! Q ((SOURCE) == RCC_PLLSource_HSE)) 8 k; G" e$ P A: f) a! B I2 p#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) / T( |3 l2 R8 V; n, v4 z#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))9 {- \- R; p% ` @ O1 b6 `7 t #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || 3 a6 Q! D& C% s ((VALUE) == 6) || ((VALUE) == 8))5 o6 q J3 R3 e4 \* g4 g #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) ) O# Y; G0 u! C* b0 e% b#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) * k5 o, f- k' |6 _6 f7 q || defined(STM32F446xx) || defined(STM32F469_479xx) . v) j0 Q$ X( [7 p1 h) O#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))# b7 z n0 u; k4 X- w2 Q0 f #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx 4 Z u: G# V& a || STM32F469_479xx */ 2 d* K; F4 X( Q 4 \" _2 o/ R' ]/ }#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))) e3 T) p! W* u6 ?; } #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))) i3 A' z! ^9 [4 W0 ` #define IS_RCC_PLLI2SM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63)) % w4 f- O9 q7 b+ q& E3 J t, U#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))* @+ y4 H* e3 E/ H. {+ E #if defined(STM32F446xx) & A$ o: u8 S) q #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) : b+ |- H3 a9 M; s0 s || ((VALUE) == 6) || ((VALUE) == 8))9 m) J$ x- i5 \5 {' T #define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63) , T2 Y3 t: s+ S9 {6 i#elif defined(STM32F412xG) || defined(STM32F413_423xx) ) B1 [0 y A' W% P; [. c# c#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) 5 x) j* k, O" g* x3 \ || ((VALUE) == 6) || ((VALUE) == 8)) 7 S! V; ]7 K1 m6 J J Z- w#else 6 x+ S0 J% d D* D#endif /* STM32F446xx */( Y0 O d, g0 u& {! T" `* l #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) , t, W' F& C, J0 ~#if defined(STM32F446xx) || defined(STM32F469_479xx) % p( b# R$ H8 R( N! N# h. x#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) % s* B0 ]( H; q || ((VALUE) == 6) || ((VALUE) == 8)); D) s) J% \1 H #endif /* STM32F446xx || STM32F469_479xx */ % N3 R. x& @; L! e1 ~. T#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))% d: {7 P1 t% D, C #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + F c: Y* m) \8 c& O# Z : [3 y! v0 z0 N0 j. c' f#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))' z& U1 w6 Z+ l) ^ #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))( X# C1 y6 q( D7 `' ]1 ~ 3 K* {# d$ V' e #if defined(STM32F413_423xx) ' T, N1 }3 M3 f2 `5 A#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) . ?8 |3 X9 c- |; I0 F' `#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))- g" _; ?% A, V; T) S( N% u6 A8 ] #endif /* STM32F413_423xx */复制代码 4 W% ~& l; f+ c* s2 lRCC_System_Clock_Source 6 p1 U6 P9 N( k3 P8 B* t6 v9 [: x6 E) t$ {) A /** @defgroup RCC_System_Clock_Source 7 Q+ Q& t. Y- r# C' E$ Y * @{ $ _! H2 }1 L- c6 J7 s6 ?0 x d */ % u" b' j* O$ @6 K/ Y' O& g, c( Z8 L/ ]6 e p #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)2 F- o* q! e% h5 H" G5 p #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)+ G3 n! i# j* O #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) / j8 {6 h! x ]/ _3 m) B% k# G: c# u+ f#define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002)' e" f( L c9 O# S2 ~( W7 _# l5 d #define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003) - v6 o* \# M! [% g- F1 U& d#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \+ D6 h9 k: _$ S E ((SOURCE) == RCC_SYSCLKSource_HSE) || \- x7 a& s: V3 q; W3 J ((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \" b/ s3 A5 e+ z6 M ((SOURCE) == RCC_SYSCLKSource_PLLRCLK)) . z2 W( S) x2 M$ p; _4 c/* Add legacy definition */ ) C% }+ s/ F9 ^3 {* ?) ?9 O8 C+ R7 K#define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK ! H$ Q! P: J E. B: m#endif /* STM32F446xx */4 B5 R* o+ o$ ]" u* r5 C ) D* a4 J o' x3 f& x #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) ) E. ^; [2 i) Y9 h& Q% Y|| defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) $ s2 e2 ~* t! T4 W0 D. R% C || defined(STM32F469_479xx)9 _ i/ h' K( _# k( N4 o$ J( ^ #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) - |! F+ T6 W: S( ?#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)+ R3 S+ r4 }4 E3 }/ x #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)) h1 m' o5 r5 ?' Q; ^, [5 L #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ ( E7 k$ G4 ^8 n2 X7 U ((SOURCE) == RCC_SYSCLKSource_HSE) || \2 `9 K% X' T( s+ O ((SOURCE) == RCC_SYSCLKSource_PLLCLK))' o, D* z4 z! w #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx & b8 v0 {3 v# h' ]$ l2 @& U || STM32F410xx || STM32F411xE || STM32F469_479xx */ " I1 X! S0 m( X% r1 ^复制代码 4 t0 z; `# I+ _. T# K0 f7 x7 aRCC_AHB_Clock_Source % r4 F. Z% {6 \ Z0 Q+ }9 i * |# _- V) n! K3 T. G9 t; `/** @defgroup RCC_AHB_Clock_Source1 u8 Y0 P: Y% \) ]8 Z3 p* K W" N0 o * @{ 6 d5 x0 i; O0 d* v& [ */ 5 H9 S/ j. @ R2 K#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) / v, s9 @ V( E4 [- M#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)! a0 n$ {: P/ W) M8 j #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)* B% {1 q' r# {& P6 ] #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) ! r9 a3 P3 f% K- `8 D* s#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)7 B3 G; A# w. S1 M) ?" U #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) 1 i7 C/ Q# R4 [: x3 b% \3 E2 P#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0): ?5 J k1 ? \; j #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)+ Z4 K3 R& k" A' \8 }9 V #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) - e7 L6 P6 u" R; k+ ?" ^) x8 y#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ [- ^6 q8 `# A9 w ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ / n$ O( S# I5 t! b3 B3 ^ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ 6 t$ J5 z6 t; ~4 O" u( u6 j1 e4 E ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \0 `: [6 ]# W$ R* Q4 f, s ((HCLK) == RCC_SYSCLK_Div512))复制代码 / G3 q% n" s, t8 E# V3 `* iRCC_APB1_APB2_Clock_Source 4 g4 f# Q4 M+ U" }9 k& B& q 0 w- E0 Q; u- a& @( p; l/** @defgroup RCC_APB1_APB2_Clock_Source % E' K! p/ B& _3 M * @{% _3 {$ E$ C1 D# U z0 U; R */$ N+ `& ]5 u6 l, [ #define RCC_HCLK_Div1 ((uint32_t)0x00000000)/ J- I1 H7 }8 u( R8 _: z: P: h #define RCC_HCLK_Div2 ((uint32_t)0x00001000) , ]' T I9 N+ f7 p#define RCC_HCLK_Div4 ((uint32_t)0x00001400)/ ?2 b& ^$ j# R #define RCC_HCLK_Div8 ((uint32_t)0x00001800) 8 I6 j3 H1 K. I, h; z2 H: Y; {#define RCC_HCLK_Div16 ((uint32_t)0x00001C00): S2 D9 R) r, \! a; ^7 D #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ * g! X* k* p0 k/ \' Y ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \! g' Z2 W$ B% e( V9 Y9 P ((PCLK) == RCC_HCLK_Div16))* q# E8 J6 U$ ?9 f 复制代码 1 f' f8 e. \# K2 wRCC_Interrupt_Source$ T1 R- [& u* t2 y5 T * p2 d6 I4 W) _/** @defgroup RCC_Interrupt_Source " N5 j1 `1 t, ^: z3 e! @ * @{( {3 |( Q5 b8 M# l3 A) ~9 k */5 f: @& j! M( i# k; w1 f" U1 s #define RCC_IT_LSIRDY ((uint8_t)0x01) 8 H/ `1 d* R8 ], z( f: G#define RCC_IT_LSERDY ((uint8_t)0x02) ' D( g8 X6 M( `, ~! C' u#define RCC_IT_HSIRDY ((uint8_t)0x04); m8 f; Q, |: w" A #define RCC_IT_HSERDY ((uint8_t)0x08) 9 |: b c* H) J#define RCC_IT_PLLRDY ((uint8_t)0x10) & S: }2 d4 }+ o0 D. |3 ^#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) 7 s2 I" C! v( G g3 b& Y#define RCC_IT_PLLSAIRDY ((uint8_t)0x40) 9 }8 D& | e+ L#define RCC_IT_CSS ((uint8_t)0x80)) G6 X {& a$ u. \4 t L% c5 v+ l. X: [( G#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) ) ]; W) t( J, y7 P; v2 _0 z! D#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \7 a+ S+ d1 y; s& T6 @. G8 k8 ? ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ 2 q( T* D a" K0 a6 O9 { ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ & B+ R2 H1 q8 x4 @ ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY)) * E) ^0 M. O) E" d5 ^* b#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)复制代码 & w8 n2 b' n* m1 N% s6 p! SRCC_LSE_Configuration ) `, {, j$ _* f" H2 R 1 p; ], b4 E$ M; n/** @defgroup RCC_LSE_Configuration 8 n3 K# O4 S8 s2 ^ * @{ - i+ T. V* w# E" }: I j */ & {: L R) \, U5 b# W#define RCC_LSE_OFF ((uint8_t)0x00)! f! H: X& w6 ?/ c2 i4 j #define RCC_LSE_ON ((uint8_t)0x01) 9 @: q6 z9 m+ k+ a& N! f0 B#define RCC_LSE_Bypass ((uint8_t)0x04)4 a/ [, d4 G0 y #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \! n# z$ J& _$ V; S7 s2 c ((LSE) == RCC_LSE_Bypass))复制代码8 G* E) P N4 T# i0 _5 W RCC_RTC_Clock_Source 1 r% M* q! l; p: S3 B! @, Q6 [/ n$ z; U/ R9 D o /** @defgroup RCC_RTC_Clock_Source U, a( I# b( h * @{8 u4 c' B1 I; \9 s& F */ 3 q; s/ Y- R {. g, }0 ]" Z% M#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) # {6 E |: c- Z. Y#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)' X; R" z8 t4 O$ b6 F9 X #define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)) l! n4 ?* ]/ C: ]. a8 v #define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) 8 T$ x( L+ G. k) p#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) 9 o6 \ d: p8 V#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)6 w7 }( Y1 e; V #define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) 5 o; |" V! J8 D7 ?; o4 @#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)7 ~" ] e5 ~, z( D# Q4 D #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)( r1 t" s+ r- i- R #define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)7 E5 t" s$ T6 ]9 v+ w& D #define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)) C4 d! R8 z+ \ #define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) % A9 E* j2 a# B! w#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) 8 \+ |" e0 ]7 I" P a3 f#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)4 Q; k1 m& [2 i5 N* F, j7 s #define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) ! ~7 @& X' s: ?/ e! n) c#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) : `* f- b6 |6 Y- u8 g/ F#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) 1 s- V/ ?9 w5 ^/ I#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) ) T0 Z( b6 c5 v1 @6 |4 a, j) M) R; l6 q#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)- t& ]8 \2 O! \+ H% \+ y0 p #define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300). K9 R% B5 Q3 o0 @( O7 y #define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) % h1 H3 E: N+ R! c#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)+ `7 i8 b' Q2 J9 Y5 n, S$ C& \- A, ^ #define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300), O" A) p( z1 c #define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) 0 f' @9 {/ f# E2 ^ {1 H5 ~#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) |' x* @3 G0 R5 g Y& b# a#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) + N9 t- c1 e; g$ {#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) 4 Z g9 }& R3 @#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)8 ], Z, D; y" U) u #define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)) H( F$ ~8 m2 e& b* ], D! b( u #define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)0 [% e- q+ e+ H4 `) \1 B #define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) " [, M" ^1 t- J9 B#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)$ @$ e9 l8 I: M4 x i #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \+ \' l1 M/ w3 z- ~; o6 ?3 T ((SOURCE) == RCC_RTCCLKSource_LSI) || \* Y( d+ f) h; ^7 C ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ : i9 a1 z5 W: A8 M0 h5 a# ~ ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ & w; c9 j6 Z! d1 B9 J7 Z/ N ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ $ j; Q& T* I" d0 b1 w" a ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \6 ^) c4 U" |0 m+ u' A; [ ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ 1 k; R4 X& Y, c. V ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ " D9 Y8 B" P& B x ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \, F3 z+ w0 `9 p* _9 B, G ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ ; @# X# o* q( |& w ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ ! e2 {( h& d- E' t3 r ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ ; U8 U7 x6 }/ g9 U ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \+ }. x$ W3 \% `' f) L' ? P6 X ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ ' n: z5 D0 }: r" F ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ 7 J! {( a9 `, x% L ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ 7 f. P. Z/ h, j* n ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ . @( X4 J7 b& W) F ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \$ `0 ?' u* h: Z ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ 3 b+ @3 @& |1 v. r ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ 5 y# `( v. d0 _( Z+ b" [5 Q ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ 1 q- i7 E. T, x+ |, t& y. S ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \) q4 H8 v& x7 ]' k* s( t, } ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ $ ~) v2 S8 p0 A9 r- G ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ 9 T! l0 o5 m/ y ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ S) y& Q6 v7 W# [) @. |9 D5 u, ]. _ ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ , E) a8 z: e& ?" s1 _( g: g ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ ; o# A: ~$ [9 a& w ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ 0 T* o4 ]% O/ ~, }5 A7 D" p) T ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \) R4 n* ]3 v" ^" A7 \; p* f" p ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \6 i- h7 f" }+ S$ r8 a( V ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ : M# L% J" L4 A8 Q) @ ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))复制代码- N) E7 h4 n2 U( O0 j/ V9 E& H RCC_SAI_BlockA_Clock_Source& r3 b8 `, s" s5 x% j: ]$ j8 E $ h+ {$ ?( H& X' J/** @defgroup RCC_SAI_BlockA_Clock_Source / H- \1 b* D0 _% I5 J * @{/ x5 |8 q4 i& J */6 N' d! h- p) U5 @! ]1 Z6 z #define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000) % M) E, {5 a6 r8 y3 q Q; s#define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000)) @, `5 F9 H% M4 r7 w" o9 T #define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000) & j/ J. P8 O! v% l+ L, G8 c4 i" ^: h( R, S( ^. r* [% E #define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\ ) H9 y& r# z% t4 X3 ?" O' i4 C ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\ P0 a; P( Q( k, B7 k7 k: n4 ~ ((SOURCE) == RCC_SAIACLKSource_Ext))复制代码 7 `' \0 O- c3 b2 x( r9 c7 V1 c# hRCC_SAI_BlockB_Clock_Source; k8 E( U' L- Z" C+ b/ A8 L9 b 2 y: F( I* L9 E9 e* W+ F6 v9 N: I1 `/** @defgroup RCC_SAI_BlockB_Clock_Source ! T; z7 D2 c! Z * @{ 3 T+ Z9 Y6 l( ~# v9 Z; Q */$ A$ I( ]5 t+ [0 G6 p' f/ B #define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000) 7 R$ M* o8 P' z/ Y5 h3 a5 R#define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000)5 A9 v7 N# _: \! @+ ~" u #define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000) * I& r% g/ k6 G& _9 q% B* g + G0 Z0 M0 L7 H5 _5 w) w7 g, q+ H#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\ ; \' s5 x+ M: b& m, u ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\ - Q7 H2 h$ `* p9 f- m ((SOURCE) == RCC_SAIBCLKSource_Ext))复制代码' D" v) _) X5 O' U: a4 S RCC_TIM_PRescaler_Selection 8 m: \3 E. g! U/ s( l, D2 U) ]! A3 L1 u6 z# |" D0 F& Z /** @defgroup RCC_TIM_PRescaler_Selection* a- ?6 c, {# } * @{7 B3 ]3 @; _) t4 z1 V* J */- D$ x$ ^- f% a% j# [ #define RCC_TIMPrescDesactivated ((uint8_t)0x00)& P4 w: g# n7 Q& t3 _ #define RCC_TIMPrescActivated ((uint8_t)0x01) 2 F$ r# x8 G, Q! Z0 G9 @! x 0 C5 d- A! p' T7 H0 [ h#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) 0 C, q. c4 q' C|| ((VALUE) == RCC_TIMPrescActivated))复制代码0 Q @* Y- x) |- x/ F RCC_AHB1_Peripherals 2 p H: `- I6 W% Y6 K0 b p3 n4 N. A- Z5 c& S) m" F5 e# x /** @defgroup RCC_AHB1_Peripherals 6 R1 I9 J' S; @2 h2 b5 l/ y# y9 x * @{ $ ]3 |3 Y5 z8 z* |$ F8 ] */ p ^8 y/ P. Z1 ~& |6 s #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)9 _, k1 \1 f3 c2 L& ^: s' g #define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) 4 ]3 \0 P$ t" Z$ m, q% R& H#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)' V* Q; c7 s* W- @5 K0 w #define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)! b; p$ F9 j5 ? M1 C7 c #define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)* Y R% `. J; F' }2 O #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)8 A& U' f" M+ F #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)( A' F( J, i* W% e #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)$ R+ p7 x: r% G* k3 B( N #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) - c! D9 G, r/ ?( q#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200)1 d/ j2 H% J1 y' B/ h/ l) v #define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400) 9 M- `; Z& y# K I9 u( `#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)3 b: e' A. d) f2 X4 h #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) ; v3 B2 S8 C4 G8 v#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000): w; z, U; i0 Z M8 Q #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000). A8 u% M3 y" p) Q' Q #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)9 W$ v- C, x. D* [( s G9 ^ #define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000) ! s$ D" H; Y [#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)( w; D; H- |; t #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000). ^, ^" t" L: J/ p( x$ ] #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) 6 q8 [% o }( J2 f! H& P2 K3 t. d9 k1 |#define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000) 9 h; U+ `: |7 g#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)* n' \3 q' {4 t, v j' R- S o( e #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) # W# a1 a- y! _! ^) V; X% ~#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) . [5 w8 g$ H0 Q$ |1 t#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) ( a2 f% e& v# P* r& c6 p#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) - t' R8 j4 a9 x, z/ x#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)0 B4 _" k( Z$ u* C# j9 c % N5 @& r2 h: U0 G) ^" s( B$ P #define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) 7 b3 E7 j7 N$ e7 f) ? ((((PERIPH) & 0x010BE800) == 0x00) && ((PERIPH) != 0x00))! ]! t1 l2 U- E* `- m #define IS_RCC_AHB1_RESET_PERIPH(PERIPH) 5 @! F# v5 J5 W3 `* \7 n& U ((((PERIPH) & 0x51FE800) == 0x00) && ((PERIPH) != 0x00)) $ N, c7 ~4 w: o* D#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ( X4 j G3 i3 ~( s+ n5 Q" d: M ((((PERIPH) & 0x01106800) == 0x00) && ((PERIPH) != 0x00)) % N `3 ~! k3 u" j. [复制代码 % R, E" \0 K: T. ~RCC_APB1_Peripherals- _! W& k% b% @1 U) ?4 l0 B $ D: B: N' a. l5 B; e8 b& L/** @defgroup RCC_APB1_Peripherals & f b/ `/ U6 v. M6 @0 A1 {* m. d * @{ s6 O6 y: D* G8 b( H' e8 [ */ 3 }0 U! T- P- L. ? #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) L6 i6 q' b- L% s- |8 y* h #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) . q9 C- j# z# q: ]% [#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) 7 l. w; ]+ \' F7 b# L* Y) c) f#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) 3 U; H; w4 U0 o3 c9 G/ ?; G# v4 t#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) " N: }8 U& B8 c# E! G t$ I0 [2 z, a#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)4 s) A, A. \% I. J #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)2 T( x+ _; y; h: | #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)4 Z* p" n B* V( I0 Z1 J$ p6 J #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) : d" E4 n" C' b' j: t* Y$ d#if defined(STM32F410xx) || defined(STM32F413_423xx) ( A! @ `! N. l3 B. M+ w/ M2 {#define RCC_APB1Periph_LPTIM1 ((uint32_t)0x00000200) . Z" t% w& c; B, k6 w ^; J# {#endif /* STM32F410xx || STM32F413_423xx *// ?1 Q* U$ t4 S; ?& J #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)' y/ s# u/ H4 X7 \& m #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) 5 s2 g4 J' c. A5 v9 h% @9 L#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)# C9 U d. F% b$ x5 _4 E #if defined(STM32F446xx) $ _2 ?: b) D- W c# o( W#define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000) $ ]: r, ~% I5 _: c p9 T#endif /* STM32F446xx */ ( M" t3 p5 a1 n; [$ f' R #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) & b% H. w" m# S6 q8 f% Q1 [2 h#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) / U* j A1 a4 s& F* Q0 r#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)6 I+ j. A* l) F& _ #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)7 h1 v4 {9 e- ]; u( O1 @# q7 `/ c #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)! s2 Y: h( E) v& g #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)7 `9 e6 Y9 [, ~ #define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)/ T" I& O: v! P/ D" {9 t' }0 L! _ #if defined(STM32F410xx) || defined(STM32F412xG) ; ?. [- ^# o* d7 Y/ h || defined(STM32F413_423xx) || defined(STM32F446xx) " S0 V) z( J: _* Y. C) B#define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000) . {* k$ j+ k: W' c0 ?& g( \, b; u#endif /* STM32F410xx || STM32F446xx || STM32F413_423xx*/ 4 K% v' T6 \4 p/ k #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) 5 s4 k" s4 E# _! V2 \( H#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) ' A; ?: x4 Y0 S+ x. g8 I& `% y#if defined(STM32F413_423xx)0 \$ l5 t3 w/ [. a4 R1 X4 l# k& \ #define RCC_APB1Periph_CAN3 ((uint32_t)0x08000000) 5 ~8 g/ n$ h1 E#endif /* STM32F413_423xx */9 x8 N) l8 E) q3 K+ C U* S- f #if defined(STM32F446xx) ) O2 W" z G$ t/ Q! ^$ E$ m#define RCC_APB1Periph_CEC ((uint32_t)0x08000000); Q) a2 _1 K* H4 q/ A% N; u* M #endif /* STM32F446xx */ 2 y% K3 @, W) r- _" v: d$ y#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) a0 l% O6 N& s #define RCC_APB1Periph_DAC ((uint32_t)0x20000000)) C8 e3 o% T/ f1 k" {" h #define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)- M. }8 R4 H, W5 B& q #define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)2 j3 L6 P/ ^. j) p #define IS_RCC_APB1_PERIPH(PERIPH) / _* b( l `2 J( I1 i ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00))复制代码/ s( k! p& v( x* @, Y d RCC_APB2_Peripherals ( ^4 Y+ H, v5 c* C0 u0 q. }8 s7 _+ N N8 v2 K% e2 x1 f2 x /** @defgroup RCC_APB2_Peripherals $ r( L: R, ], S) o( R4 ? * @{7 |" j& l* d" _ */ & T6 |9 K2 U; g: V' D. \ #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) 1 q* ?+ J8 ~+ p! `. g) L% B#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) 6 R4 l/ | ^, x# [7 Y. ?#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) ! k5 w9 X+ }* [#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)7 S& i* b( k# f9 E; d8 T #define RCC_APB2Periph_ADC ((uint32_t)0x00000100) 1 g+ e7 ~ b3 T: i#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) $ g3 V/ X: M+ g) \6 c3 I9 F#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)7 q# z$ H1 E7 z1 Y: L #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400), O) Q. `* k7 g #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) 2 d+ n4 v* i( A& h6 h! n3 d- Z#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)8 Z! p, H+ s! K( K2 s4 E #define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000)( u! P. B, ]1 }& v* b! y #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) 7 }* | c7 b- p* U: x+ N#define RCC_APB2Periph_EXTIT ((uint32_t)0x00008000)1 O6 {1 t3 b- P #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) % T8 T* t- t3 n9 i o#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)7 V# x, O a- G #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) ! I s9 b, [" v: `2 I4 M1 Y4 R( D#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000) ! _, [0 I$ [" C) v! J# _) ?#define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000), B V" ^0 ~3 g6 w; E- s #define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000)3 N2 M' u5 e6 L3 j #if defined(STM32F446xx) || defined(STM32F469_479xx) $ k/ U4 b& ~% E- e4 T#define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000); q) I; {. q( h- m, Q' N/ ~* _) ^ #endif /* STM32F446xx || STM32F469_479xx */* w& M2 }* Q) k: S) S" \ #define RCC_APB2Periph_LTDC ((uint32_t)0x04000000)0 e8 K7 k) ^8 x8 m7 ]! L" Y$ K #if defined(STM32F469_479xx) t0 s5 \9 ~/ {, Q #define RCC_APB2Periph_DSI ((uint32_t)0x08000000) , m2 |6 o" F. |) J2 k( Q6 N#endif /* STM32F469_479xx */% g- M9 Q Q& x+ q o #if defined(STM32F412xG) || defined(STM32F413_423xx) ' s& m! \8 L5 v) L! H#define RCC_APB2Periph_DFSDM1 ((uint32_t)0x01000000) 2 v# i9 N; Z) J! D+ }9 G#endif /* STM32F412xG || STM32F413_423xx */& s- Z7 k( q3 t #if defined(STM32F413_423xx) 4 N) Q: E2 C; q* x#define RCC_APB2Periph_DFSDM2 ((uint32_t)0x02000000)$ d1 V5 `0 r5 q #define RCC_APB2Periph_UART9 ((uint32_t)0x02000040)' B0 S+ T+ p7 Q7 x/ ~! l #define RCC_APB2Periph_UART10 ((uint32_t)0x00000080)% m M% i4 I/ s0 H #endif /* STM32F413_423xx */- K' J' T% Z* A/ l# N* q 8 \- ^4 ~1 P7 p3 i' N /* Legacy Defines *// Q0 I- n$ l1 C x' s7 Q #define RCC_APB2Periph_DFSDM RCC_APB2Periph_DFSDM13 n/ |. k; p% X9 w- V# C( H c Y/ x! Y+ U( q #define IS_RCC_APB2_PERIPH(PERIPH) + Z$ I: b8 x- j) H7 r ((((PERIPH) & 0xF008000C) == 0x00) && ((PERIPH) != 0x00)) 2 R4 W \& b n3 B) H7 m; }#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ' s+ s) [9 K+ q8 J7 V ((((PERIPH) & 0xF208860C) == 0x00) && ((PERIPH) != 0x00))复制代码 - U, N2 f5 o% Y: Q+ G$ A1 V# I9 M* nRCC_MCO1_Clock_Source_Prescaler # p8 E! W% ^, |& e6 X8 F1 X( y! K8 a$ Q3 h8 k" A+ V3 I9 v /** @defgroup RCC_MCO1_Clock_Source_Prescaler3 F% E. u. ?: m& I1 N! c * @{9 {* L9 L# p4 k5 p! V/ F7 X3 Q */* g& s" K! l$ |7 f* j: p( G, \ #define RCC_MCO1Source_HSI ((uint32_t)0x00000000)0 O( Q) H# y7 N2 Q, f #define RCC_MCO1Source_LSE ((uint32_t)0x00200000)0 i) a; v( A) ?* } #define RCC_MCO1Source_HSE ((uint32_t)0x00400000) 4 e- _+ j. L; e$ y#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) $ u# ~: D. c9 v- [4 g/ |#define RCC_MCO1Div_1 ((uint32_t)0x00000000) 1 z, [8 N+ r* g#define RCC_MCO1Div_2 ((uint32_t)0x04000000) $ L# k0 u o6 J' C6 c0 j#define RCC_MCO1Div_3 ((uint32_t)0x05000000)7 u4 v& N D! a) M+ h- D* O #define RCC_MCO1Div_4 ((uint32_t)0x06000000) 3 D/ U5 k2 p- g3 r' T5 [#define RCC_MCO1Div_5 ((uint32_t)0x07000000)& C/ A2 f& k$ }: p; U. H6 Z #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) 0 q6 U8 C6 R9 O) P; }7 C3 N5 O |. [|| ((SOURCE) == RCC_MCO1Source_LSE) || \ - Y9 I5 E8 H, x' v0 m ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))( E4 D. M0 q+ |: c& e0 q U5 y4 F ~( k0 W- p2 } #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \/ g4 F. j4 j/ j4 }. F c ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ / ~* C/ ^5 E, Z ((DIV) == RCC_MCO1Div_5)) 复制代码, v! l. V: z! | RCC_MCO2_Clock_Source_Prescaler 0 K! P" c+ u0 s3 ?! I: ^ i , N/ s) Y( j5 M, [- |/** @defgroup RCC_MCO2_Clock_Source_Prescaler5 i0 @" C8 ?0 ~! O3 A * @{/ J% b6 l: C1 O) v [- X */0 v2 H1 m: M0 J8 y. h, m #define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) 2 I2 q. k$ z) Y4 `: I( X- w#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000). Y. n/ C4 O7 J( M #define RCC_MCO2Source_HSE ((uint32_t)0x80000000)& z6 C! _9 K- w/ k) N- \ #define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)8 q9 [/ M( ?, d7 f #define RCC_MCO2Div_1 ((uint32_t)0x00000000)2 X5 j7 z- v. z( @. a+ ?" g& F #define RCC_MCO2Div_2 ((uint32_t)0x20000000), l' o; @$ q% d: l) r' h) `8 X #define RCC_MCO2Div_3 ((uint32_t)0x28000000) ) ?9 m$ v4 t" T6 A5 h* O#define RCC_MCO2Div_4 ((uint32_t)0x30000000) - J2 _, F( E* j6 Q$ B7 i0 Q% K#define RCC_MCO2Div_5 ((uint32_t)0x38000000) 9 Y$ \& F5 d- M#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) + K E* c9 L$ S|| ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ ' p r2 x/ h, n7 I1 O ((SOURCE) == RCC_MCO2Source_HSE) , t/ ?; ?+ S. ^3 ~ || ((SOURCE) == RCC_MCO2Source_PLLCLK)) ; G6 X5 Q u! s9 l; m* G0 r, m5 w #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \& M& ~, }) }9 Q; ~+ z+ N# Q ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \% Z' @# C' T; U# b W% O' Q ((DIV) == RCC_MCO2Div_5)) 复制代码( i1 ^- k; B' @7 I RCC_Flag/ `" w, \ d. e7 J( W4 _ 0 F+ p- F- H3 t6 r /** @defgroup RCC_Flag % u+ C; Z% y. ~1 P' V * @{ ; A2 W. Q( p) } */ 6 f( a% {0 W0 z& z; y7 E+ {, C#define RCC_FLAG_HSIRDY ((uint8_t)0x21)0 g" C) }, b$ \) j, I0 d7 c #define RCC_FLAG_HSERDY ((uint8_t)0x31)0 y2 z' B+ v4 T6 t4 I; K# \2 [ #define RCC_FLAG_PLLRDY ((uint8_t)0x39) , [. {6 k9 w! ?! c#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) 6 O* u- e7 o+ E5 q4 l" ]#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D) ( q1 p1 f- {3 q- h#define RCC_FLAG_LSERDY ((uint8_t)0x41) 9 q* O: ^4 Q2 S( b# s#define RCC_FLAG_LSIRDY ((uint8_t)0x61)* S6 m7 f8 v6 w1 V1 j #define RCC_FLAG_BORRST ((uint8_t)0x79) & s6 u) A K7 {: Q, f# v! {8 E#define RCC_FLAG_PINRST ((uint8_t)0x7A)" h0 E2 J z, P2 n" T #define RCC_FLAG_PORRST ((uint8_t)0x7B)* R* ~* a! k* A) F `- W8 U) V5 U1 l #define RCC_FLAG_SFTRST ((uint8_t)0x7C) 3 ?" B/ p$ K" {0 o+ ?. n#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) 5 P8 K. @- K; ]+ V' M3 N#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)( L7 z6 s/ f6 D7 G0 J #define RCC_FLAG_LPWRRST ((uint8_t)0x7F); x, A3 r6 a7 n; Y' B6 J3 C ! q; Y( r. M6 \; W( U) V6 G( ~ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ ) R' j7 S+ U7 ~4 n) l- f2 y/ o ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 1 q, r/ L0 f! N4 z) \# x2 r ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \$ B5 i% k' b* D3 V5 U% ` ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ - t# ]' b! O- Z. T ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ 9 J% [# W9 v# u ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \2 Q5 v+ p8 K% |& F ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY)) , h4 W( O H) @3 f' p8 W5 C8 p5 I3 g! }$ M" V: e2 ` #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)复制代码5 C5 Q3 a, M- @# { ]- M2 o 03. 相关函数 + U" \% _& ^6 d5 Y2 y6 Z/* Function used to set the RCC clock configuration to the default reset state */- y1 t: N4 L" Q. o/ m g( E8 ^ void RCC_DeInit(void); 7 X- c0 f+ }; [, E/ q2 Z0 k% P- ^7 } /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ " `( n4 c' p' ~1 \1 b) T/ p1 nvoid RCC_HSEConfig(uint8_t RCC_HSE);! b5 H0 |9 E) ]% {% P$ y+ _ ErrorStatus RCC_WaitForHSEStartUp(void); 1 H3 C& n6 Y# f, G% P0 x% [% v @void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);2 ^ m# s1 |- E% y1 M. Y void RCC_HSICmd(FunctionalState NewState); 5 v, H+ T5 b) x* F+ `9 C$ s5 U fvoid RCC_LSEConfig(uint8_t RCC_LSE);: `. Q3 z$ W' \1 ^7 ^ void RCC_LSICmd(FunctionalState NewState);' q+ d6 T o7 H: i: g( H * S" J( t6 X; \4 } L2 u2 o& o- R( _ void RCC_PLLCmd(FunctionalState NewState);' ~$ p3 T- R% A3 [& X ( W$ V* U9 x; x& j. e' F# p2 ~ void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, `$ v* h9 h1 o( ?8 q6 m' I uint32_t PLLP, uint32_t PLLQ); ; T4 j8 J. i$ s& W- L / ^: h8 M9 g; s7 g" fvoid RCC_PLLI2SCmd(FunctionalState NewState);( k9 A6 n3 o9 `5 Q3 n4 ^( _, z - Q/ l' [3 s' E8 d1 q9 l; j( r' ivoid RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); 1 o. O, s3 r6 l7 G! a% g8 Z# L6 L- V& t5 M0 H$ U* k : t- r8 x# b `7 tvoid RCC_PLLSAICmd(FunctionalState NewState);) Z) z) n+ G0 U# o9 C# d * \! I' Y0 B, f: M# j void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);5 y& H0 E$ d! t" \4 Q" j, e void RCC_ClockSecuritySystemCmd(FunctionalState NewState); T: Q4 `( }, Qvoid RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); 5 P+ x# m' A' N) I$ dvoid RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);& t* f) G \; q# k $ X/ i& [# [, i0 T* u: b - Y* C' Y+ v; R) \. X/ a/ F /* System, AHB and APB busses clocks configuration functions ******************/& u/ V5 R2 M6 u, X9 c" ]3 X* ^; ~ void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); & y+ G s& E' `6 f# C/ P7 n! Muint8_t RCC_GetSYSCLKSource(void);9 P g$ y- t. ?& F9 l void RCC_HCLKConfig(uint32_t RCC_SYSCLK);8 Q. P2 q$ Z: G' u7 W8 I; J$ N void RCC_PCLK1Config(uint32_t RCC_HCLK);* J2 E* b% h7 v* n/ W0 m void RCC_PCLK2Config(uint32_t RCC_HCLK); ' B+ X U5 P, v- J2 _$ ~. Evoid RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); 2 _- e+ X) B {: L" t , o* x* I: ^/ h1 T, n/ ?' s* y* e/* Peripheral clocks configuration functions **********************************/. i+ Q$ R1 s, ], y) B void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); 5 I+ \( h0 F4 j( Y# ^void RCC_RTCCLKCmd(FunctionalState NewState);9 |1 J8 @! t9 n5 a. m6 x4 W void RCC_BackupResetCmd(FunctionalState NewState); 4 v; s8 W/ ~ l, w0 N. Y( I& e% K" i% N9 U' @0 Q# s) g- U3 A # ^9 r$ {( }3 u+ s1 ~void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); ' ?& [+ p# u! S' B8 _" Z* m/ I8 l! D, t D ) ^6 M1 n% ?" O! x2 N4 k1 k6 W void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource); " i1 f6 D+ U s0 S' d+ {void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource); / M; D, B0 ]7 n 9 M8 a$ |; `9 @+ @& ?5 k ( p G1 H& S/ uvoid RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ); & V0 g9 Z9 s8 X9 F9 H. {1 v/ Tvoid RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ); 1 I& S8 I' r! {* ]" i+ t$ \0 T 7 I! F& `5 f! J3 M0 F; ?2 e9 [7 f, H. q5 o& S( n void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR); . E/ r/ L' z- Kvoid RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);" n4 O. n* p( O$ b6 Q" T5 f; y : ]6 U' J1 f% R: p2 l- Y! y void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);; ?& h" Z/ C# x void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);+ ^) H# |7 ?1 G void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); ; _- I8 f1 ^$ S. t6 {: Svoid RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 4 ^" B) b; e7 b8 Z; avoid RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); ) I# T& {' R1 l3 O/ {3 P) h2 { * x- t* l$ u- q* c6 K' D* Kvoid RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); 4 }9 ~, c4 R! T0 R( ivoid RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); / q: d- K8 h/ m+ X2 Zvoid RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); 8 Y. w% \' U9 |' r" ?' N" yvoid RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); . G. r' T: ]- S3 T- \void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 3 k# t- N6 z1 r) o* m $ @$ R5 v8 t# d! D2 z; Bvoid RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); & z4 e0 `' c( [4 i0 {) o( gvoid RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);4 v0 \+ H& F7 w$ B$ q- k void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);: k/ V+ s7 k/ K1 `9 |" o. H- B void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 7 E5 j" O- `" o( L) `$ |& dvoid RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);1 H# a2 ]" d2 t8 M) ^7 f / N( k$ Q( v. a4 O & x& l R7 R0 a% M+ l1 j, [& x/* Interrupts and flags management functions **********************************/ : ` [2 h) x9 d8 ^ ivoid RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); . b$ E+ t0 R' O+ n& Y) vFlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);6 n* a6 b7 h) B* ]1 u/ E& I void RCC_ClearFlag(void);- M+ E o2 i. N1 C0 F$ p0 M1 I% D( N4 { ITStatus RCC_GetITStatus(uint8_t RCC_IT);% o9 p6 h. ?, {2 M" F void RCC_ClearITPendingBit(uint8_t RCC_IT);复制代码3 ]* k2 E" Y: v6 ]+ R 04. 结构体封装 5 l# G9 b. f! H" h/** % a7 Q, k- [4 q% w/ } * @brief Reset and Clock Control . @" z" `! j4 }# V: M9 Y */) ~0 `3 l$ c2 _2 n l / P7 B& k, W" s* X9 { typedef struct ( N! q. N" p: j{ 3 F5 ~/ M0 x9 } __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ # w6 g* D3 `9 V5 m9 g __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */7 P& G5 N# R0 G; ?7 j) V( F __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */# a: c/ c" D: R) C: E __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */, |: H0 Z! a# D6 l __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */; h; H$ H, z; f8 _. Z* b __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ 0 k: t- ~+ m# A- j; b1 R __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ ; f' K: b0 M8 G, h; ] uint32_t RESERVED0; /*!< Reserved, 0x1C */ 1 z% N, E4 y7 A __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ ; Q" y+ s" e0 F v6 X% Y; U __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */& O# K) R4 W& W uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ 0 e# J$ v/ X- \: j) u __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ 6 q5 @- D' s' n) w __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ 5 s5 J+ E6 r7 d- l4 p: x) W __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ 6 [, M% L8 C; k# o9 ~$ J7 j uint32_t RESERVED2; /*!< Reserved, 0x3C */ 4 q' Y0 {$ P/ a; p6 B __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ - e- i2 H1 u3 j9 m" T9 i. `( Q __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */6 D/ t0 v7 }1 d7 X uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ " z7 ~7 ~( A8 W* g$ }2 Z3 k8 O __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */: N o1 L( d1 @+ a' g9 u) l# c __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */' T! \1 x' W6 f g __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ 5 l* i9 z4 O, L8 e/ i X' S uint32_t RESERVED4; /*!< Reserved, 0x5C */) {7 Z& f' S/ W+ T __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ ) _2 |8 M. v% }4 t$ z __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */, s4 Q. f1 \* t7 o" ] uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */) m, }# W3 A$ [6 m1 k1 \. T __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ 3 N) g/ g. P7 J1 p$ Q3 ^ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ - c, i& A8 U% T: V* O uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */; n: J5 S4 i8 H __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */- R- o; G; ^2 e __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ B! w/ Y& M2 C2 w v0 p __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ 2 ?# r/ T8 k3 ]; r# I5 G3 F __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ B' ]7 _6 p! g __IO uint32_t CKGATENR; /*!< RCC Clocks Gated Enable Register, Address offset: 0x90 */ /* Only for STM32F412xG, STM32413_423xx and STM32F446xx devices */ * F$ I# @: ?# P! i* f. r m0 F) Q __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */ /* Only for STM32F410xx, STM32F412xG, STM32413_423xx and STM32F446xx devices */ ) O: V A* e- h- Z7 D- U/ e- o l6 F / G- }$ O$ l2 N- d9 Z4 f1 g. n5 U} RCC_TypeDef;3 w6 I9 B, U# C% I! ]* [ 复制代码9 g5 F( q8 R4 Q9 R0 k+ c 05. 其它- C, n# w/ t# e+ H /******************************************************************************/ ; f& r7 i; _; W7 j" S6 ]+ |/* */ 5 w( C: O3 J3 o% J$ r" H& N/* Reset and Clock Control */5 A: s' w7 t8 m+ q /* */& S8 s/ D; x; q) e8 } /******************************************************************************/ . c1 M) K) o# Q c& ]9 T ]1 L/******************** Bit definition for RCC_CR register ********************/- t3 ^2 \5 v1 O #define RCC_CR_HSION ((uint32_t)0x00000001) . L. i+ C- K& H+ r/ Y#define RCC_CR_HSIRDY ((uint32_t)0x00000002)* h# q! Z E$ o3 R$ t% H + i" B' W8 Z( W) ]# [% _7 X#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)- Z* o" d1 r3 M. S/ d1 b #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */ ; z5 w8 H& W% {% [#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */ # G$ g5 ~ e# B- }' {#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 *// ]! V7 r5 x% K- j #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */ ! H- m, c7 K- b4 j& L#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */ Q/ c9 G/ I* C; |4 E $ w3 M/ _0 m' I2 k/ U9 L% E#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) : g1 x& m+ N6 g' _2 s. j: T#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */ 6 c+ h+ V+ S3 J* _#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */" S3 N/ T" F+ H+ M" Y #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */ 8 U* k, I. O: ~6 ]: `4 Q#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */ " c& U& ]& g! O) V9 u+ h2 l, \& }#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */- n- W0 F* f; a: ~ #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */ 2 Z0 F" w* }) k0 y#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */ 6 ?, A9 _3 ?# N+ t d+ F( A#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */ 0 U" a" [6 o2 I1 ]/ S7 Y7 m- m$ G/ a; z' f b: Q2 L" m" d #define RCC_CR_HSEON ((uint32_t)0x00010000) ' y- y* ^0 x9 O2 S% M% |, K2 L# F' E#define RCC_CR_HSERDY ((uint32_t)0x00020000)( Q$ K$ k+ g# ^6 i3 i #define RCC_CR_HSEBYP ((uint32_t)0x00040000)8 q( Z% Q: n, H# f& Q( K #define RCC_CR_CSSON ((uint32_t)0x00080000) 1 e$ \6 g8 v4 D$ W) b- w: T. O% z. x#define RCC_CR_PLLON ((uint32_t)0x01000000)+ L* w" s4 a- d2 ~$ I) r1 t #define RCC_CR_PLLRDY ((uint32_t)0x02000000)! G2 m* w5 M* V9 }$ s7 O4 e #define RCC_CR_PLLI2SON ((uint32_t)0x04000000) 4 ~! F* U' ]; y- T#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000) 0 o7 ?" ?& X+ V#define RCC_CR_PLLSAION ((uint32_t)0x10000000). z& K! f; D/ h9 F #define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)' V+ ^ V* y# C8 Z 1 q7 R2 h! m2 r /******************** Bit definition for RCC_PLLCFGR register ***************/- q# D% r, H0 x+ } #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F) & c# a/ Y7 ]( {& v#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)4 R8 x5 g( e' n1 R+ H8 H #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)! s& Z# L2 P; C/ f6 h1 `! X0 }6 x #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)) d4 [! B- f! } #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008) ! t. r* B4 O+ m. ]2 G#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)8 ?4 [1 m. ^ f3 R! o #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020) 6 g; J1 t' \+ ?$ N6 Q3 g: i, D7 S4 ?6 y+ Q0 Q. n #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0) * v' Q" m2 Z6 \# y+ h3 K- _1 Y! a#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040) $ z$ a& ?! q2 \9 R) D$ X#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080) / v/ t M7 L. c- l9 s, ?#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)" H4 I1 v0 D- F/ H, V #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200) 0 R9 }* e& L( n" V8 e#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400) ( Q$ h7 S" o$ I2 d+ c' A#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800) S4 ^, Y+ G9 @, @' f+ N6 l6 Q #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000) 3 J0 g1 n( l U: H. o3 p7 J# C0 ~#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000) 9 z D6 B; o8 F3 f: X9 a) h0 c#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000) : F- r$ n% c/ r # E' U# T, R! w$ f#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)1 ^- G6 ?. u- T$ O( z #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)8 ^: W$ j: l7 |( O# u- S: y- o #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000) m& Z8 {- g2 @0 C 8 m. c* D) J& R/ X% \( A$ p' \ #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000): Z# s1 M: H. L' g8 L% C #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)9 X# V" W* } Z* Q) I #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)8 @/ z7 l: G: N5 p) ~2 v 7 H8 L+ X5 l) ]- d- g9 H# A9 ]& Q#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000) ' L* _) c7 |# s#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)+ D) a5 ?6 {2 U1 S! f #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000) 5 Z0 F- ^8 W3 c4 h; z0 x#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)6 x" R+ `: V6 N' T' A/ {: t #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)) y5 o( |/ z1 s2 D 1 }9 z) f1 D% l8 L5 y4 d#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) 9 H+ ~/ x+ D; W0 [; G0 T#define RCC_PLLCFGR_PLLR ((uint32_t)0x70000000)& {; J0 x: A( Z- |# l* t #define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x10000000) : u# o& j: l9 e4 o6 x, a7 O: l9 U#define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x20000000)9 r% H2 J. H m) u& Q #define RCC_PLLCFGR_PLLR_2 ((uint32_t)0x40000000)) ^8 V: t0 g8 U0 m" S, O #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ 7 I3 I6 b6 v3 d7 J* G a# p J7 P1 O3 V( i/******************** Bit definition for RCC_CFGR register ******************/* _4 ~9 o, R0 p" G; F3 k /*!< SW configuration */7 R( u" K4 K3 @ #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ 5 T* T) W5 f6 k#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ & g/ s, |1 c% H0 U% l#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */9 j$ z! G7 @6 e # L9 H* r: d2 {# s. Z3 Q#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */- I2 D& B3 ~ C: V6 S #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */0 `! ~# P- c3 O; W$ s- F #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL/PLLP selected as system clock */ / e) \8 L2 W# g" o4 A$ @9 t#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)7 c4 s E6 y4 p8 Q3 C; o1 { #define RCC_CFGR_SW_PLLR ((uint32_t)0x00000003) /*!< PLL/PLLR selected as system clock */2 s1 S; z" F/ K% C, h #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */# I$ _: r: Z) A* g1 q6 O) j, e d- P8 }6 ^3 |. e+ q/*!< SWS configuration */ 3 T" ?, w% Q1 ]9 A* u/ J+ f( k. K#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ " H" [0 K) R1 {, E% C6 E9 g#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */5 _: y# t5 A8 Z* [! f/ l" Z #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */- @ W+ M7 [$ f: ^" G) T8 K ( B9 y7 \5 G6 d: R. F#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */+ b" _& L2 x/ g8 w #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ o/ K9 }. ~& b3 C' d% @ #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL/PLLP used as system clock */ 4 ]6 s+ v/ Q& Q R) d; _4 V#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F469_479xx) || defined(STM32F446xx) 5 f! n% o3 L) ^#define RCC_CFGR_SWS_PLLR ((uint32_t)0x0000000C) /*!< PLL/PLLR used as system clock */ 6 x! |% F7 s6 ]$ X6 s+ g- j, ?" |#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */% R; X$ D7 {) V# |3 h3 h 5 H% Y* ^" \! N [, z: q$ U/*!< HPRE configuration */8 N; S( M' C9 g7 ]2 N" U8 n #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ ' ~7 G9 s/ C6 R! P#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ $ | v7 A+ p# y; Z#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ $ I; u) `, |5 B8 b( |9 A#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ % A9 n; @& S! Q: L! S/ I#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ % B- o3 o9 |2 R/ T, Y3 M) Y0 @* D. `9 `" h2 X #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ 5 g% Y' b5 V( z# c, X5 Q0 o8 g#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */5 ]# r. M _' T/ L. c( P# M/ I( m2 T #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */8 f4 d8 i( t. r& F8 M9 l #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ 9 M+ d4 e! n7 Z+ y" O% S+ I" p#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ 7 r8 Q S. r l" w* k; G2 N z#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ / j$ l, p$ ?0 ?4 u4 U* A#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ s- h5 V v! j #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */0 c, K& y6 Z( X/ s- j, E0 R1 @ #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ # \; A# f' ]3 i. R% k* u6 x$ d2 E# j #if defined(STM32F410xx) ( ^# N9 o, h/ C$ d. c/*!< MCO1EN configuration *// H7 g1 ^ ~7 M4 T4 M; {3 t4 T #define RCC_CFGR_MCO1EN ((uint32_t)0x00000100) /*!< MCO1EN bit */ $ A% d& Q+ n% m3 ?6 u/*!< MCO1EN configuration */' |, h1 ]# p+ p% R' s% S0 U3 G #define RCC_CFGR_MCO2EN ((uint32_t)0x00000200) /*!< MCO2EN bit */ $ v; \5 I, _ e/ _7 Y5 i3 [1 s#endif /* STM32F410xx */9 I$ r3 ~$ X$ h /*!< PPRE1 configuration */ 8 W- |3 h* e6 Z) h Q) X#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */# r. _6 n9 o9 y #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */" ~6 u. a/ H8 A #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */ * `0 l1 p1 s J7 t#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */ 3 f1 r. l, @+ R5 d! ?# c) P ( b. I7 \# z; a1 H. T* D#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */' r* W; V2 e- K #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */' o+ U0 O4 K) } ~5 Q! y7 a# S #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */9 Y5 y) t8 B5 w& \0 l) e6 f/ B #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */4 f4 E! x* I5 i" G! ?: { #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */ 4 x; A9 B3 c( a* ]$ U: Z5 a7 @ , Z- A# Z2 d! E/*!< PPRE2 configuration */6 ~. a/ q5 U! r8 ] #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */ " z) A1 e( J G#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */. W8 i- ]6 i* W1 j# V0 n6 Z #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */ 8 o9 P4 D% N& D0 e. R7 I#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */ - c1 X' m: a4 u7 $ Y1 ^/ N7 Q 2 m: {+ e* {# j3 $ \5 D#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ ( ^# H3 H" p3 A1 ?0 a#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */! I+ P* T# F3 b* g8 B% u( z1 o #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */9 j$ ^/ k* e$ \5 P #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */ + c) |) K, D, F$ t* W#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */+ d# t0 p! a2 R4 N5 [ 3 Z c) a8 Y. s3 c: z5 F$ T/*!< RTCPRE configuration */ 9 u) y6 J5 S- j#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000) 3 J% s. W$ z E#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000); L1 O% G: w& q7 N$ \$ b( I! g #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)) \) h9 b. \/ o: o) ^0 E& e #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)$ | d% d3 h8 B2 P4 | #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000) + H: H _! F# ^ r#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)5 v& H6 u0 d# p1 M% K9 o- C / ]! S' J4 S, g( ^( s /*!< MCO1 configuration */ F0 Z4 _# v1 \! f8 [ N4 ?2 B #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)( r, Z1 {$ v/ r1 t4 C7 J #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)5 b5 o1 E& x: |+ D2 u n #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)) p% D7 V# [) d) [ ( S* p1 d( @' X; ?6 Y#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) 5 u8 w! y/ M( v- { ) ~( Q3 q. C. K# X6 K8 x* a: t#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)& |/ P8 }. L( u. i; Y% x( q #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000) / {& z# Q! {8 d q#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)6 C& u. ^8 M9 i1 I5 {" m! J% } #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000), M% [0 T6 L. G 5 e9 T+ u. c" Z7 v% n) u& J #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000): Q' d# ~" k0 f* a* N# B #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)5 c2 f2 ?0 u8 I1 R* E #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000) ( i8 J( T( d8 ^9 l( {. _( |#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000); z- w. z, Q4 n l5 E2 o( I4 w! P6 l% n 4 E; T0 A) A' r8 X8 | #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)7 l; z" J7 d, _0 e! _4 Q #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000) ( `. O* |" s5 K9 Z- Y: F7 ~) Z#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000) 7 L+ {$ [2 y9 O1 p. y2 V/ X1 T& `6 V. f- Q4 j /******************** Bit definition for RCC_CIR register *******************/( R$ t/ Y2 J% m. \3 A" h' q7 j #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)/ U: A0 v( {! @2 d; |1 P v #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)6 F' H+ t8 U( w" x #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) - C# Q/ [, ^" ?. w#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) " @6 U6 q6 ]* h8 U1 z8 B! t#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) 1 b3 S7 [" ?: t9 D% U* ]* h#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020) * E2 l+ Y! ^' B' r) }/ o. n! }#define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)4 |5 }4 J1 U$ ^* p1 W% a #define RCC_CIR_CSSF ((uint32_t)0x00000080) , N, G' m# S. u# r# \#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)$ u, J$ I; h& @( | #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) A) i, A2 c, F1 `8 g9 h6 u#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400): @7 n# g* z& E5 | #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)" N: \) I- e9 }% @! g- B #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)# ~# Z0 `; t) Q9 A( o5 Q" O. k #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)$ Z: _1 L) U' Y/ ]) N0 z" A5 H& r #define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)- t6 `, l8 f2 H$ K #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)+ o% T9 Y4 V" R) s; z3 ^ #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) 0 l8 Q# S* ?- e& R; l- r8 I#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) ; c1 P0 L( E- y#define RCC_CIR_HSERDYC ((uint32_t)0x00080000), t0 S, n: |- \' k9 l% m# |! o3 C #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000), }% H( D' Y2 \0 s #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)8 x' w, W3 G; H1 u* q #define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000) 8 z+ U: M X$ H) u! A7 j#define RCC_CIR_CSSC ((uint32_t)0x00800000)" c3 P! W7 P7 j1 C9 ^ 6 K+ C2 A7 P" p5 I L2 O/******************** Bit definition for RCC_AHB1RSTR register **************/+ k! J+ j# S, Q7 ?. \$ S #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)" [5 W# y- q2 z. g$ U #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002) ; {4 R, W. ^7 }/ R1 u) _#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004) 5 _6 ^ U- e; ~1 K' c2 \1 i& K5 p#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008) / R: [! |, e5 c+ u( W, ~#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010) : W/ N* ^ `* y; U#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020) * K8 T8 s2 D; |2 [* ~#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)# b" d0 i: N# |0 f #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080) " z# t3 x6 c1 u/ Q/ m" S0 t#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100) u) u/ D2 ~, {#define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200) & y0 V$ g* M- t" M8 t( k0 h; e#define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)0 x% @7 Y( F2 E4 Q6 a' A #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)6 v3 \2 ?, E5 Z, }; j( ]; J, M. `* X! P #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)$ h0 `* W+ S* N8 K1 V3 x #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000) 1 Z5 h6 L7 ^; N" C#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000) ; d/ K$ u& x8 T- o9 V- G#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000) ) A' r: e# N1 m8 h3 H6 [8 C! {#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)" [7 H: z7 F* x7 W3 t* j. K , J" P4 N( v) N3 S% T% m /******************** Bit definition for RCC_AHB2RSTR register **************/ : U8 B( t* @# l# L2 z#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001) 0 G E* d4 U' x5 E- E' D#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010) 2 l2 L9 R/ c6 ~5 N' `#define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)1 t ~1 m- w6 k8 @/ k /* maintained for legacy purpose */' h) O3 i; U& J #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST) Z8 f3 j( h5 ^9 E! k. n [ #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040) - n$ d' y& \% ~4 v+ u#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080) 5 J+ T: U9 d( W1 z* b) f T r: C1 V $ n3 U1 v7 P* f3 ?/******************** Bit definition for RCC_AHB3RSTR register **************/ , `! w0 y* i9 F, x; d#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx); E2 A3 M. Y. O$ y #define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001). B4 q% A# R: A% m #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ 5 K8 O# }+ L8 `2 T9 v! h + ?9 S1 T) Y4 |( l7 Q; g#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)/ h2 B* J; E9 D# |( c+ B9 N8 Q6 \ #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001) . W9 s" }9 j0 g; P+ [#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ ; s* U D2 v0 P) {. _3 S+ R#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)6 J4 i# @. E1 Y% e$ |6 g #define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002) 3 a5 l) v) p: c) L0 Q2 o9 c1 C& t#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */- U4 U9 L0 p- H$ ?/ H9 S6 ^: P; X ' i4 O1 X2 K' _4 s/******************** Bit definition for RCC_APB1RSTR register **************/: P1 z$ V. u, O #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) # Z& O. ]; c' z$ s. L#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) : R7 M% v9 f# N#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)0 E- f& |6 K5 L& t! \) M #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) A% m$ K( [4 w3 z #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) 8 b% l8 u# W( I! I' r#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) $ X1 M3 M4 n9 w& m6 V#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) # q/ K; K0 h8 b5 c) i8 Y7 Y#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)6 k3 u8 f" a* |& A #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)- P$ o/ X F4 h* d! r/ k) J #if defined(STM32F410xx) || defined(STM32F413_423xx)& `8 Q1 u/ u0 M: E$ z$ ^7 ] #define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x00000200) ' ~9 |2 j5 d/ A5 b' E. i7 @ d#endif /* STM32F410xx || STM32F413_423xx */4 W n. u9 [$ x3 q, t #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) : k5 B; C3 Q) h$ N" a5 [#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)7 s" j2 ?+ Q! j #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)9 i) G9 U* R7 `% a! @/ ?5 w #if defined(STM32F446xx)& \; ]4 Y" O# C: i- M5 j #define RCC_APB1RSTR_SPDIFRXRST ((uint32_t)0x00010000) 2 G& s2 T2 K' c#endif /* STM32F446xx */ 3 d* L6 w3 C$ \* {#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) 9 N# G( _6 e( m) p$ \, Y#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)* W, G! B$ y( z( W& `4 j #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) 6 n1 E; f3 _( P9 q# S p#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) ) `6 o( \+ D3 S+ `+ L) [1 a#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000). u) Q1 g" e1 t$ P, G, q$ g #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) 5 X* b. A# n& H; ^# _#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)0 M: J% m! c6 \+ K #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) / n/ z2 ] z6 |3 Z/ x#define RCC_APB1RSTR_FMPI2C1RST ((uint32_t)0x01000000)% o8 K+ F+ t- F5 Q/ `" B1 J #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */ , |3 L& D+ L; i6 }#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) : S% e" M }2 p, R/ ]! d7 N8 ^#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)( s1 v* K0 h. S2 ~2 Z2 s #if defined(STM32F446xx) ; i) t1 |9 g1 H/ r+ k0 ?#define RCC_APB1RSTR_CECRST ((uint32_t)0x08000000) 5 `1 S% v+ r D#endif /* STM32F446xx */ # r! N/ S$ f+ b- _$ B( J#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) ; N% ?0 T- D3 D2 K& ?# U#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) . i3 O( G2 z$ F- P9 B, }#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000) " O. j3 [" o" n( Z! B#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000): O) y$ W$ o* Y/ V8 s 7 ^( C6 v8 r k3 e /******************** Bit definition for RCC_APB2RSTR register **************/ 8 c9 U5 C, `# K, ~% m N#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)2 d, A! i9 j* w# @8 Q5 r% l #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)4 @- J' ~6 S) L5 r3 b- J$ J #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010) 0 J5 i( N: o/ p' F! ^& B6 A#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020) C# r2 F" ]1 _9 y! @9 L# _% W#define RCC_APB2RSTR_UART9RST ((uint32_t)0x00000040); T9 P% E8 r* u# H #define RCC_APB2RSTR_UART10RST ((uint32_t)0x00000080)0 s& D, g8 N; Y" I$ P( x0 w #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100) 8 y- k. x8 u1 B: Q6 \#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800). R/ ]$ x; C* s T; |. Z #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) " {9 Y c& i! e' K- ~#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)7 ]* D6 R% W+ P' Z+ U g% e( N #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000) + U2 l( a9 E: e+ e6 u#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000) 3 [, O/ `( M2 w4 h. c9 W/ ?#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000) 8 L5 g: b8 G1 u5 z" F/ [#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000) # U0 Q9 x# _$ }# a#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)5 U7 q( }' k* [4 t5 {/ j #define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000) 7 u( x1 g" s4 P, E#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)$ ~+ j5 W/ W8 ^$ \' z. v: p+ R- v$ ^$ l #if defined(STM32F446xx)$ H* g r0 t8 j( p) h& ] #define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00800000) |4 q, H. A N( a/ r4 }% R3 b #endif /* STM32F446xx */0 W, o0 w' G+ h1 t" ` #define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000) - A* O! B' y% \" U z" W% ~- B# _9 W#if defined(STM32F469_479xx) + y" X% u8 v0 T- F1 ^#define RCC_APB2RSTR_DSIRST ((uint32_t)0x08000000), |) |# v( C2 I% A2 X% d* t #endif /* STM32F469_479xx */ ) @5 C$ V' Z1 d% z h8 y#if defined(STM32F412xG) || defined(STM32F413_423xx) 6 V) U/ O8 B8 H2 s$ p#define RCC_APB2RSTR_DFSDM1RST ((uint32_t)0x01000000) 2 Q: b, d5 z; v2 k. I0 q9 n#endif /* STM32F412xG || STM32F413_423xx */. R; h' V; g0 Y' |1 F7 G0 M 6 t" {! }& [0 s; u6 r( | #if defined(STM32F413_423xx)4 I3 F. W: [& w% I# B7 C #define RCC_APB2RSTR_DFSDM2RST ((uint32_t)0x02000000)& k% e% m9 ` I: f" r l8 B9 P% |9 J #endif /* STM32F413_423xx */9 I3 e# `3 M8 K% l( z' R ^2 S /* Old definitions, maintained for legacy purpose */2 ]0 z- Q9 N, [( C0 N) d #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST # {/ m* e0 z( V#define RCC_APB2RSTR_DFSDMRST RCC_APB2RSTR_DFSDM1RST 6 {$ a4 j8 ]; p4 t: j/ b3 \6 [ O5 k /******************** Bit definition for RCC_AHB1ENR register ***************/ ! g$ ?0 w3 F* K! \+ D2 }" D#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001) 8 E. r A S7 I1 a1 C( a% A/ m#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002) 4 p6 a$ J0 p3 F% n) f#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004) 0 Y# W( b+ I, _* T( ^#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008); b1 U) X0 O/ v9 h #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010) $ J5 a `. B5 I) M#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)1 T- {' j ]" z/ v1 [+ E* { #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040) 6 j- U. V# E: \2 J( ]6 a#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080): b' g g; [2 o$ w8 V #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100) 5 A) k: n( f' o# Y$ U: s#define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200) ' Z O% p% b+ y4 S n: Y#define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400) . K R- t; e- D, Z# p% G#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)' d' H. q3 u6 ^/ D( f6 R! I- K #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)9 O7 H9 p, [' q6 v1 c #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000) K; V" q Z# b2 `9 g#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000) ( G: D8 N( M/ M+ {/ c#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)/ e9 l# {% M& S& o# \3 Q #define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)! r6 x. p. a K/ J% D% ?) \! b5 M #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000) 7 M$ l2 c8 n, M" N5 ]' I#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000) 3 d* a1 q+ u: }2 [#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000) 9 T& @/ o' T2 R9 k% d6 u/ p#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000) 4 j6 G0 J i) a#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000) 6 t- k2 ] }) P7 O, \1 y {#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000) " Y/ s8 e' M) d2 G3 Y0 B$ B n# _6 ~/ N7 n) W% j /******************** Bit definition for RCC_AHB2ENR register ***************/ 2 \) `8 [. A) z _' e& m" R1 P#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001) 6 B+ _' n) M/ ]; S- |#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010) 7 m; m1 j( K7 j% P1 U2 a- W#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020) 1 m8 R& Y3 [7 ?$ L& u2 i6 L#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040). S* C" Y! c6 H. M2 p; ~ V/ S #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080) / S; l, x' R% B7 `. N1 \1 k" O+ s3 b8 u2 V# O- ` /******************** Bit definition for RCC_AHB3ENR register ***************/3 V' H9 f& {* c1 R8 I* i- O1 G ; K0 Y+ d/ f# h #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) - f" y4 C: W" s' s2 k#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)1 i5 m7 J4 J" S, R #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ + R) r1 d1 W! [0 E- @0 h9 r: P% h3 u4 ~& `& ? #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)2 g# x5 O4 W: N$ ]7 B, [2 d0 E #define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001) : W. m( m2 y3 |! H: Z#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ 6 Z+ e/ q r+ G* a, K0 q1 F! l% m- y3 ^+ q- |0 H #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) 6 @" w( w( y" o$ E- I0 y#define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002) 1 H2 f# l( i5 n3 ~2 K#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ ! V# O& |- m' U' y) W+ X6 x% Z) B1 I7 o- H, e /******************** Bit definition for RCC_APB1ENR register ***************/3 R$ A6 s( R |( R$ R+ Z$ N3 k/ e #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) 1 M. ^8 {# q8 \5 l+ K#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)7 a6 C1 G: w- o6 l' h #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004); E }& u X2 B" N& B; @* ]7 z #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) |0 s1 R- S/ p9 d7 ]#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) T7 }! O3 V& d% H/ B #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)2 q( E9 L; }' u* ]3 ~) N$ s #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)( ^7 l/ r) R7 M2 n #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080): e; V3 L. u8 k! @% h9 t$ X; Q8 C #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)5 s7 Y* x6 R+ f4 q #if defined(STM32F410xx) || defined(STM32F413_423xx) " v7 Y' P1 o& W) U% l#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x00000200) , h. P; ]4 N' D' X6 s* ~#endif /* STM32F410xx || STM32F413_423xx */. L" o1 R/ s: X( ?' e/ b #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) " E0 }! |0 c! r5 O1 ]- ?, Z#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) , a7 a1 [+ `5 b#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)- W) T: n1 p$ k+ a #if defined(STM32F446xx) 4 v" A$ M2 N3 R: G#define RCC_APB1ENR_SPDIFRXEN ((uint32_t)0x00010000)6 I, O6 E2 I$ N( l- J( L #endif /* STM32F446xx */4 X" A( H) ]3 ~4 ~5 w1 W, [3 w& C: w #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) * I& a/ \, S0 A' S#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) ! m) ~4 i/ d+ U. _- b#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) P! g! z2 B( t) A$ p- S& D3 d #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)& s9 q& U# X [ #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)! n. c: @& p: z #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) @, x% Z- g. x( d#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)7 X v# F; _; R( t4 f* p #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) 6 t/ M+ Q5 ~0 I+ G#define RCC_APB1ENR_FMPI2C1EN ((uint32_t)0x01000000)0 k9 u$ q& c1 `) B) l5 @9 ?* A( p #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */ " ^& B/ f9 |$ i) m& D% Z7 r* ?/ |! o#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) 3 m) z/ V& z- e, A7 e' t#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)- W7 f; u) I4 d5 R! D3 h' j #if defined(STM32F446xx) . Q" L) _, X: e' D9 ]) O% g#define RCC_APB1ENR_CECEN ((uint32_t)0x08000000) 4 g' }! A: S& I) i8 X#endif /* STM32F446xx */% I( ?6 S8 \! D #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)$ J. z4 t5 G6 g: |7 H #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) 4 Y% C) D7 ]# F#define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000): J! s, n3 y; D" E, |8 G' p #define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000) / T9 g8 i4 h. Z' p. ]. `" ^/ ], j& z$ B( s* f: F /******************** Bit definition for RCC_APB2ENR register ***************/7 z' R2 L$ B9 a4 S. ^: o8 C4 l #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)# o0 |9 [5 R, O: D- H, q #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002) 6 b* x O. Y/ s, U; U#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010) ( X. _! z, ~' I, g1 l5 F+ q#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)( m6 k/ k* y/ G# \) Y$ u #define RCC_APB2ENR_UART9EN ((uint32_t)0x00000040) / H9 e, I1 R- j- ]/ u& f#define RCC_APB2ENR_UART10EN ((uint32_t)0x00000080)% z) W! F' q+ w( g1 }# T+ u( G6 C$ Y( M #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)# W6 \& z* o1 R9 | #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)" J9 d1 {; S$ j #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400) & [" g; k- {, x! `, W" W#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)- D% L/ @! }) }! v$ ^# X9 _ #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000): l* Q. o' f. O #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000) 1 J0 v- ]0 R. R) U; Q#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000) 5 F+ g. _& K! l& D: `* z#define RCC_APB2ENR_EXTIEN ((uint32_t)0x00008000) # Z, g+ v! {2 F#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000) ! b7 t# P0 d: k3 g, o& U7 Y#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000) ( r2 [8 u* k; j8 J: [#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000) ; ^" ~, z+ y6 P% h/ Q0 X) Y1 M#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000) - ?' R) R2 g7 m, ?#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)' R" ]3 v: F* h8 Y #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)6 c! D4 A0 [( W' | #if defined(STM32F446xx)' _9 G- |2 T! f3 c$ E1 n" u #define RCC_APB2ENR_SAI2EN ((uint32_t)0x00800000) 7 V0 { s4 n6 z" v' O; ]3 K#endif /* STM32F446xx */. H0 B6 B0 P0 i$ u+ N# X #define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000) ! n# A! L; Z# B* ?: I" ?, i4 j9 c#if defined(STM32F469_479xx) ( ]3 i( m) O3 n0 r#define RCC_APB2ENR_DSIEN ((uint32_t)0x08000000) + Q- U; e1 w/ R; i, B% M#endif /* STM32F469_479xx */2 q: P- H0 j# {1 Z7 A' h4 D( Z #if defined(STM32F412xG) || defined(STM32F413_423xx) & G) {$ W( q2 M) b: B4 i$ i#define RCC_APB2ENR_DFSDM1EN ((uint32_t)0x01000000) + p. x1 }# [. p) N; {+ @6 B' G5 V#endif /* STM32F412xG || STM32F413_423xx */ 0 N5 W3 r. q% p7 @#if defined(STM32F413_423xx) 1 L( ~# X1 y" \#define RCC_APB2ENR_DFSDM2EN ((uint32_t)0x02000000) K' O) m- P n #endif /* STM32F413_423xx */ : V2 L( o8 ~3 V+ r% I0 a; @/******************** Bit definition for RCC_AHB1LPENR register *************/ , E5 W. q3 V' m9 i" {! j a% t D#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001) - {* c* j8 A' A: o7 G& J#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002); ~; A4 k( e5 ?# G A/ S. I #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)) O$ ]4 e0 a$ C# Q! R7 i% c #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)# P6 v) Y: p- e7 \( f1 {" C2 N) Y9 G #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)' y/ v, s7 e, ? #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)8 z# A. x9 G) T- S8 H #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040). g ^. @0 K9 O2 a9 b _ #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080) ; l# o4 M5 ~8 i$ j) S# ~* i. e#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)" v8 I) b3 u3 m& |. r6 g* F #define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200) 4 Q" F( Z/ c: D. p/ F#define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)/ X5 s& B" K1 u2 T( F #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)' \7 e; b1 J f7 w) ~ #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)6 d* D% G2 Z9 |$ w #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)% `0 k& U+ K1 p$ ^ #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000) 6 n; c; O$ Q! `, D#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)8 \! S* _- u$ B* ] B: A" m: a8 Z #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000) ) }3 V5 I5 }1 `5 K1 o6 J1 r#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000) 1 d) T* R. n# Z#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000) * F( G/ s) i3 Y. I) n$ I; J#define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)! A+ o1 i+ Y! x6 u( }6 |; s #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000) 7 D1 Z) X; a% v p) y#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000) 4 K$ W6 e/ c% T5 U6 A; ]#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)1 W6 y! K% Z: y- [ #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)* D( V+ j0 t8 s0 a! z #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000). {: H; \$ L& [ #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000) # z9 v+ R7 [2 d" k6 k# d# W# ~1 h: Y% f. A! h /******************** Bit definition for RCC_AHB2LPENR register *************/% l* k# x0 H1 q9 o9 ^ #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001). l' j. n# I0 O$ `5 X1 P4 B #define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010) . S4 t6 B( b$ K, N0 W#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020) 9 c4 k& b5 I, v+ `# Y: h( Q#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040) ( K3 t4 m0 l, e7 U. K#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080) I; v& C0 w' [9 S4 w' i! p0 M* @! j6 f /******************** Bit definition for RCC_AHB3LPENR register *************/) K- f0 P1 a& _2 R. q #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)2 d3 k9 f |4 Q0 f# S* p O #define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001) 1 @6 t7 z' d0 P N3 w6 A#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ ; _( F% V5 A+ |$ p 5 h2 t- `0 g; [' L#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx): [9 N. |% }0 g# l s. k) z #define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)9 r# w' H" R) m3 o #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */3 s+ P- o8 K! ~& T3 F0 C, K& o% u #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)$ H* m# Q! P4 M, P: g+ X* { #define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002) g0 W) u4 I o5 Y% c5 Z4 [#endif /* STM32F412xG || STM32F413_423xx || STM32F469_479xx || STM32F446xx */ t/ w) l6 L9 c) f 1 I5 S) T0 W* }% G" @ T0 {/******************** Bit definition for RCC_APB1LPENR register *************/' G/ ^: j! M: |' s# y! K& W #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)$ I1 e/ `/ |" p: j! u" h9 V #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)" n) I" ]4 V9 E4 a #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)- L1 M' h! t" f6 C; N+ S" r #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) 4 z) x7 t- B. F! y! C) V' }( b#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)+ B& |! P8 s5 K2 E+ g% k2 Y5 @7 I #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) : _5 G1 p% R. O2 d#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)8 D, K4 C, s: S #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080) * `! g! G: V0 p! i# v; K. |#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100), @. m- W; u3 ~' t. P$ \ #if defined(STM32F410xx) || defined(STM32F413_423xx)% ~) f$ P' Y5 t5 I5 w/ q #define RCC_APB1LPENR_LPTIM1LPEN ((uint32_t)0x00000200)8 u, D6 `, n v! B8 X7 T #endif /* STM32F410xx || STM32F413_423xx */ 4 G( Z& s# w+ \! Y" P6 r9 Y#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)0 I8 ~' o( f* M! S #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) 8 p, F) Z+ u) S8 _; ~0 h#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) + y( H# m: h! i" ^& W7 W#if defined(STM32F446xx) 5 m: i' e) h$ a#define RCC_APB1LPENR_SPDIFRXLPEN ((uint32_t)0x00010000)+ U9 k/ Y+ F+ D! e, a: ]* L. i #endif /* STM32F446xx */ J; ^' ` K: F5 L: z" x7 R #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)4 {5 {' c/ n+ |# Y( h6 g #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)! j1 s# p2 W6 l" h9 E #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)2 e1 r6 F) X) C0 b #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)5 W1 Y: ?/ K; P3 @0 o$ _ x9 t #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)% Q# A6 X8 T3 _ #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) ! e. ^ `: m% C4 j3 n' _; I& u#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000) & c' ]0 s& C+ ^2 [2 Q' b) F#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) ) I- e" m1 c2 q5 Z5 i#define RCC_APB1LPENR_FMPI2C1LPEN ((uint32_t)0x01000000) ' `# y! _7 o& y#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx *// r# `, a/ U8 i) V, Y #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)& F1 {. N% ~" k; J7 O3 j #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)" B9 m8 {( x3 A+ }( L' {5 d #if defined(STM32F446xx)5 d7 ?. S1 ^3 K# ^% M #define RCC_APB1LPENR_CECLPEN ((uint32_t)0x08000000) 6 T; |+ P+ x! q5 u* M2 r#endif /* STM32F446xx */$ j- W& ?% k' C #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000). S$ V! c7 O. g& ^, O- y #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) : @' h; u* ]0 H5 M8 a( G#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000): H5 D/ A! M0 a8 Q #define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000) b( q2 y4 ^6 o' X, g8 V / Z! d2 ?2 f2 a0 }; g/******************** Bit definition for RCC_APB2LPENR register *************/ - l; q5 }1 B- c% j3 r L5 f7 S. F#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001) ! R7 Z! N( {7 @4 G' |. ?#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002) 7 }8 v# n$ q6 l. G+ V#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)2 X/ I2 V2 Y$ a X #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)) I( p( m; n. y/ Z6 H #define RCC_APB2LPENR_UART9LPEN ((uint32_t)0x00000040)' u# V7 I1 T& G/ M. m: r #define RCC_APB2LPENR_UART10LPEN ((uint32_t)0x00000080), ~8 j, b; G/ C+ y# E5 _. s #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100) 9 ?2 @( G& ]- v#define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)( a7 t' p$ f: g B6 l6 x #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400) 4 c. v0 G8 b$ l( {# @! o0 q. ~#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)9 W2 C7 c0 o- o/ z% z+ j! Q8 { #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) # ]! D( X: @& p% |# `, z#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)9 @$ h1 ?9 c3 H t" J1 e2 ? #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000): `1 Z7 C' K( w2 b8 O' ^% j #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)& N. [" o8 F5 a- Q8 ^6 X* o0 F #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000) 3 f# z6 A) ?# q, r, j6 _2 c#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000) ) F& x8 U$ R. x#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000) # ~) u8 W% R6 ?' a#define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000) ; `5 Y8 s' F+ V$ R#define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)/ H: e# ? d4 M' P% }% ` #if defined(STM32F446xx)# u2 F: h0 P: n t% E #define RCC_APB2LPENR_SAI2LPEN ((uint32_t)0x00800000)3 n. v0 f6 Q7 K- R6 X, ^4 h% ^6 b #endif /* STM32F446xx */ : g0 j9 y1 v0 A" q0 `#define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000) . v/ j9 N1 j3 W9 s/ n#if defined(STM32F469_479xx)* u# r, u: Y- \+ I" Z0 x #define RCC_APB2LPENR_DSILPEN ((uint32_t)0x08000000)/ w/ {4 Q* }6 J. v5 \8 q. e m #endif /* STM32F469_479xx */ + ^) }9 z4 c1 \% u, e9 [#if defined(STM32F412xG) || defined(STM32F413_423xx)# o& t' o8 |* j+ x* G% @9 Q9 D9 A #define RCC_APB2LPENR_DFSDM1LPEN ((uint32_t)0x01000000)- K3 c7 v5 O& T8 h. Q6 u; ` #endif /* STM32F412xG || STM32F413_423xx */ 0 j9 |( c" o( k" r( F2 r n#if defined(STM32F413_423xx) + F% e' h( ~( R) i( Z#define RCC_APB2LPENR_DFSDM2LPEN ((uint32_t)0x02000000) ' i' R) N `* w6 O#endif /* STM32F413_423xx */ G5 c# f h9 w$ A9 G) ^$ A2 I& B! X3 d& {2 B/ s /******************** Bit definition for RCC_BDCR register ******************/ 5 T# a6 P, ]/ X! y( X( N9 Q#define RCC_BDCR_LSEON ((uint32_t)0x00000001)0 y) T* |$ X* A8 m9 q! j #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) ( A% e9 i% N; y#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)- w# W+ s' B9 M( F5 Y, e; g #define RCC_BDCR_LSEMOD ((uint32_t)0x00000008) H0 w( O/ r" s6 w; K$ m' q* k, G& `; Y) t #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) . q- I. h; M6 L" g% h/ T#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) 4 S* b, @6 f0 a# P7 I* ^#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)9 h5 k5 o2 w$ H" { 4 F& [8 G# W5 s$ z3 D1 N4 w#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)" G1 n& ~. f4 z7 s* l #define RCC_BDCR_BDRST ((uint32_t)0x00010000)( W, \5 s l( U4 K8 i 4 a1 o6 q7 I& H( Q6 F5 C$ _/******************** Bit definition for RCC_CSR register *******************/2 o$ D v$ J# o' B) s( } #define RCC_CSR_LSION ((uint32_t)0x00000001), f7 M4 k2 |# `& N8 x) R! Z #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)* X8 B1 V: L. b, ` #define RCC_CSR_RMVF ((uint32_t)0x01000000)6 }9 J, M5 |! T3 x% D" n, Q) l #define RCC_CSR_BORRSTF ((uint32_t)0x02000000) ' E9 O1 M* n. F7 w- H% C6 i+ r#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)) a) L+ [" V8 Y0 s L$ C #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) - ^+ W6 {* {. _: W8 l: V6 S#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) r8 k2 W, i N3 {- i) X#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000) " V- F- d) e* F! E#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000). C- I/ L, z% b' ~# A" h #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) , d/ B% B3 z5 N7 ` t8 J& C8 j4 ]( X6 z$ J2 n- R4 y6 R- W; u /******************** Bit definition for RCC_SSCGR register *****************/* @, o0 O+ Q& y+ x' | #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF) 5 @6 L k* M/ Z) Z& q9 i! p( ^4 B#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000) 1 _9 o* ?4 n) ]: @& t#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)# b3 @1 r$ c/ C #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000) . [ m' q: [+ L " j/ J8 K- P8 V/******************** Bit definition for RCC_PLLI2SCFGR register ************/ * M- s# l2 |7 Y8 O' N+ Q#define RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F), N* o- n8 f5 U" r #define RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001) % z! a' S1 K) A- z& u#define RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002) ' E6 G+ q, ^% m) Y$ Y3 w#define RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004) ~) v. D4 ~: h( b: I0 P3 t' U2 K #define RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008)3 L( R: Q3 o$ m$ b4 \3 k" c #define RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010)- S% {% J8 {1 J3 J0 K+ U& E #define RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020) 0 `" @* S1 h6 X8 a+ [ * v+ k i5 m1 M" s, L#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)2 S1 L T9 d8 N7 i4 i* _. o! M #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040) " G) a' Y# Q9 `) i A3 r#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)* j: j& p& l& }$ U3 @) Q4 H #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)' V: c b+ D4 w& M, y #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)- B+ Y0 ~2 v, N7 ]) w #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400) " I0 t3 X4 @) b# K- E#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)# e0 ~& _3 M5 t3 t2 M' r, a #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)3 X9 w5 [' h( t% x. F #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)8 O# v4 B$ u/ E |. t* v #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)2 w0 t# v8 \ R0 `5 O+ m % \. ^ I {- K9 o4 x8 S5 j& E#if defined(STM32F412xG) || defined(STM32F413_423xx) ! v; x+ n1 ~$ ^% H _+ P+ v#define RCC_PLLI2SCFGR_PLLI2SSRC ((uint32_t)0x00400000) " i; N' k' `6 e |' i/ ^#endif /* STM32F412xG || STM32F413_423xx */ 5 P' m% w' u7 C- S5 Q3 F' E, W ( i+ t, z9 O6 c#if defined(STM32F446xx)$ O9 Z. j; r" e7 Q3 g #define RCC_PLLI2SCFGR_PLLI2SP ((uint32_t)0x00030000) / N$ ?3 A( J" J% v; Q7 n#define RCC_PLLI2SCFGR_PLLI2SP_0 ((uint32_t)0x00010000). l! @8 a: }1 @( R% \ #define RCC_PLLI2SCFGR_PLLI2SP_1 ((uint32_t)0x00020000)2 T/ T% T5 D0 x" I8 [# B% i7 r2 W #endif /* STM32F446xx */9 q- ^; y5 U$ C7 b$ e. J 0 `3 Q9 b/ A+ a#define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000) " L7 t& d6 @+ E5 D#define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000) " a2 x4 u" G5 ?" @% s#define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)6 p( @9 f0 g1 L$ c+ y #define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000) 4 Y" O* I4 D2 {0 f#define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000) 1 x; M' L U1 h# d7 V; j: i( \6 b. r1 M #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000) 2 S3 V& n3 |$ i; o0 U4 s#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000) ' C( T* S9 m( A: y7 e#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)5 ~9 y0 ~# z4 n9 F+ G #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)% {( q: ]. x3 m. J: w. Y . P0 D1 u: I; {5 u( }8 f /******************** Bit definition for RCC_PLLSAICFGR register ************/. [* r( ?) ~- W' i7 u2 i #if defined(STM32F446xx) 8 w: d6 b8 ]4 n9 s) j+ ~7 K; K) O6 z8 a#define RCC_PLLSAICFGR_PLLSAIM ((uint32_t)0x0000003F)3 J' s' N2 G5 x, N2 I #define RCC_PLLSAICFGR_PLLSAIM_0 ((uint32_t)0x00000001) 6 Y- H4 f/ k2 `7 K7 p0 F- L#define RCC_PLLSAICFGR_PLLSAIM_1 ((uint32_t)0x00000002)0 O3 h: p5 Z( q1 W2 z# i #define RCC_PLLSAICFGR_PLLSAIM_2 ((uint32_t)0x00000004)" ?5 F g3 m0 T" [0 b- u" { #define RCC_PLLSAICFGR_PLLSAIM_3 ((uint32_t)0x00000008)' v% H0 o ?- G1 ]2 |0 b* {5 r #define RCC_PLLSAICFGR_PLLSAIM_4 ((uint32_t)0x00000010) , {3 b4 }* R; n* Z) h6 j _- e#define RCC_PLLSAICFGR_PLLSAIM_5 ((uint32_t)0x00000020) : O$ }+ b- Y9 J- u1 Q9 t, r#endif /* STM32F446xx */ 5 }% d2 O2 c7 {5 t) c9 l1 m; t0 ^9 C6 o. H #define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0) 8 x9 N" N4 X) C6 g# a4 N#define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040) 3 w+ ?# v- ~5 M! y% V" I& {#define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)( n$ L- o* l# f8 t #define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)2 i( W+ H$ V7 y. n9 p #define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)- U; Q9 t$ R( P0 B% [( U7 Q$ e9 i #define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400) 6 M0 K \3 g$ K6 d7 [) t#define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)' e6 g9 U( p4 M1 k. S( [ #define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000) . ?8 q5 ^5 ~. V( s, {7 [8 L#define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000) 4 n! c7 \' v1 F/ q! }- O W#define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)/ v, C9 P9 m K 9 g4 K. L4 F( W, J9 P #if defined(STM32F446xx) || defined(STM32F469_479xx) 1 p5 E' ]' X; v1 S #define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)# L7 B% Q% C# q #define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)/ S3 k% R8 Z( ]) e- E) h9 |4 ? #define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000) 8 Y0 Y8 \" \ J# V#endif /* STM32F446xx || STM32F469_479xx */- Q; \5 }, N& d % _7 L" ?( F" o# j: q#define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)5 [) S" P: \7 s( [7 t #define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)% f' y( L3 { ^/ v; W #define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)9 W! ?7 w1 f' s* G #define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000). `3 v# i4 E% W% i0 H #define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)4 o7 m3 U. X4 a- ?! e( c% z 7 S: T8 t* f( M8 i. J/ h2 |#define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)4 G4 O7 V8 c) `2 F #define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)) _, h$ \/ I, h( c8 N1 {. Z #define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)" E3 g& q; O% W* e #define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000) H% H; s4 P: V0 u" l! } X. K, s# m, \* U) x/ H! f /******************** Bit definition for RCC_DCKCFGR register ***************/+ v4 W* \% v+ U+ f9 a- a0 N( R #define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F) x! {6 K* u! ]) t: h0 {#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00) ) D3 X. }$ b/ o/ k#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)" V! p+ Q, d8 j: U# ~2 P3 V 9 F3 H3 B) O# U, B4 Z+ X/ m#if defined(STM32F412xG) || defined(STM32F413_423xx)$ W; j: X9 m8 o+ V- `9 q2 p+ G #define RCC_DCKCFGR_CKDFSDM1SEL ((uint32_t)0x80000000) 8 Q. M3 s! |6 I#define RCC_DCKCFGR_CKDFSDM1ASEL ((uint32_t)0x00008000): B1 [; [: P* { #endif /* STM32F412xG || STM32F413_423xx */# M1 F( f* [( h- r' ?6 z' ~5 X( O 4 T$ c! h3 S. n O/ }) ]#if defined(STM32F413_423xx) 6 ^: s3 w6 ~; ~" W( }#define RCC_DCKCFGR_PLLI2SDIVR ((uint32_t)0x0000001F) : @; A' v: b4 }1 m9 O* g& Z#define RCC_DCKCFGR_PLLI2SDIVR_0 ((uint32_t)0x00000001)* [( ] U) d' a #define RCC_DCKCFGR_PLLI2SDIVR_1 ((uint32_t)0x00000002) * ` M, {7 Q2 j; [#define RCC_DCKCFGR_PLLI2SDIVR_2 ((uint32_t)0x00000004)/ D" ?/ D: V; k6 d$ N+ N3 o0 t #define RCC_DCKCFGR_PLLI2SDIVR_3 ((uint32_t)0x00000008)- ]' I! T4 i$ @ l #define RCC_DCKCFGR_PLLI2SDIVR_4 ((uint32_t)0x00000010). q. _( h5 R8 a - b- ]% T# I+ n+ c8 |2 k% @+ E#define RCC_DCKCFGR_PLLDIVR ((uint32_t)0x00001F00)3 \# N8 v" g$ t. j s" x #define RCC_DCKCFGR_PLLDIVR_0 ((uint32_t)0x00000100) ! _, p6 q* g$ Q% D, H0 _+ f#define RCC_DCKCFGR_PLLDIVR_1 ((uint32_t)0x00000200)- R* K( H# [. c- I6 B# i( z# ?7 s #define RCC_DCKCFGR_PLLDIVR_2 ((uint32_t)0x00000400)3 D4 g. i$ J q! M; ^; J* F2 O #define RCC_DCKCFGR_PLLDIVR_3 ((uint32_t)0x00000800) 9 z% C# H; d; G% f7 Y% ?#define RCC_DCKCFGR_PLLDIVR_4 ((uint32_t)0x00001000) " c; _: E: S, {, U! r#define RCC_DCKCFGR_CKDFSDM2ASEL ((uint32_t)0x00004000)* z: y. Z1 K1 d! H1 W #endif /* STM32F413_423xx */ $ n( r0 b2 N( m* S& I i. Y- P8 W' c/ `! v% K; d+ l! u0 l #define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)0 ~& x( _0 l5 g7 D: W* d #define RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000)5 p# m5 |3 |! R' ^. s #define RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000)- e u" B3 [0 j. C& |2 c #if defined(STM32F446xx)" q1 w% O5 Q& x% [0 \ #define RCC_DCKCFGR_SAI1SRC ((uint32_t)0x00300000)1 n. l D5 `' l6 D #define RCC_DCKCFGR_SAI1SRC_0 ((uint32_t)0x00100000) ) W' T/ K: Y4 N0 P#define RCC_DCKCFGR_SAI1SRC_1 ((uint32_t)0x00200000)+ R4 V& t: W$ _# K+ @. ? #endif /* STM32F446xx */; ?+ C* D5 ^' W# S7 u* |: J / U! U+ O" i& w #define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)9 h- ^) x, b9 E+ ^3 q9 a4 l% L #define RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000)/ b6 r5 u$ q) s #define RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000)! b3 A* i5 J4 Q6 X! r- i: f! ^6 @. U #if defined(STM32F446xx)% k6 m( A! M: S! R$ Y4 q #define RCC_DCKCFGR_SAI2SRC ((uint32_t)0x00C00000) , q$ `! J9 \6 Y$ ]; c. r/ P& u#define RCC_DCKCFGR_SAI2SRC_0 ((uint32_t)0x00400000) / \$ ?5 i0 Q0 I3 T: u5 c' a. S#define RCC_DCKCFGR_SAI2SRC_1 ((uint32_t)0x00800000) - S3 N# C D2 m3 i( S' w#endif /* STM32F446xx */- R$ R0 u$ I, S* |' O1 Q, e ( \4 n! X2 m' m* G+ \ #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)/ {7 E0 I% R% k( { #if defined(STM32F469_479xx) 3 W0 Y( W v4 E! e9 _+ c#define RCC_DCKCFGR_CK48MSEL ((uint32_t)0x08000000) # t0 F0 N& ?" C+ h9 D: G, f. i#define RCC_DCKCFGR_SDIOSEL ((uint32_t)0x10000000); r' A3 j3 ]+ [) \# T0 A #define RCC_DCKCFGR_DSISEL ((uint32_t)0x20000000) ( }$ W6 a) g3 M6 u#endif /* STM32F469_479xx */ ( s" `' V# P& Q. F& J' ~) B' g/ i% ~ #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) ' N" R+ c9 i9 ^+ X5 k, Q' b# F#define RCC_DCKCFGR_I2S1SRC ((uint32_t)0x06000000) : \5 ~; S5 Q2 R0 V5 Q* I9 P- x3 O#define RCC_DCKCFGR_I2S1SRC_0 ((uint32_t)0x02000000) 6 R# m, W2 E2 _; q I9 I O S& S#define RCC_DCKCFGR_I2S1SRC_1 ((uint32_t)0x04000000)) ]! J3 E1 w N# U8 U, _ #define RCC_DCKCFGR_I2S2SRC ((uint32_t)0x18000000) " `3 ^# ]0 P) f# s#define RCC_DCKCFGR_I2S2SRC_0 ((uint32_t)0x08000000)) Q2 J9 A! e( V. F, c3 ] #define RCC_DCKCFGR_I2S2SRC_1 ((uint32_t)0x10000000) # \) l- p, V8 _# h% b) j8 ` 8 B/ i- S+ h/ K) ~+ g9 X9 j/******************** Bit definition for RCC_CKGATENR register ***************/6 W. P/ p9 r4 L9 Q6 _' | #define RCC_CKGATENR_AHB2APB1_CKEN ((uint32_t)0x00000001) 0 M0 H" [7 X& ~, m#define RCC_CKGATENR_AHB2APB2_CKEN ((uint32_t)0x00000002) ; f9 d' S* E3 z! B. O. O. e#define RCC_CKGATENR_CM4DBG_CKEN ((uint32_t)0x00000004)9 I. Q, U" i7 | p #define RCC_CKGATENR_SPARE_CKEN ((uint32_t)0x00000008) . I3 Z0 k0 c% m# V; ~9 \+ W#define RCC_CKGATENR_SRAM_CKEN ((uint32_t)0x00000010)& R" h+ }: D1 Q. Y #define RCC_CKGATENR_FLITF_CKEN ((uint32_t)0x00000020); F( ^- x# [( a+ D8 F( q6 Z q6 K #define RCC_CKGATENR_RCC_CKEN ((uint32_t)0x00000040)# n$ O6 E. h( H #if defined(STM32F412xG) || defined(STM32F413_423xx) : v$ L" i r, A) U$ ^. I0 F#define RCC_CKGATENR_RCC_EVTCTL ((uint32_t)0x00000080) ( S- h3 ^2 F; Z9 }; X! Z8 s$ k#endif /* STM32F412xG || STM32F413_423xx */ ( m* J! H7 X. L. D 1 O0 y2 p" X- k, @* H/ `# q/******************** Bit definition for RCC_DCKCFGR2 register ***************/$ a# h: g) S5 { #define RCC_DCKCFGR2_FMPI2C1SEL ((uint32_t)0x00C00000)2 L, }" @$ n" @. @ `- s #define RCC_DCKCFGR2_FMPI2C1SEL_0 ((uint32_t)0x00400000)1 Y5 u& V0 l: ^" t #define RCC_DCKCFGR2_FMPI2C1SEL_1 ((uint32_t)0x00800000) ) h- ]& L- g5 T' a3 X#define RCC_DCKCFGR2_CECSEL ((uint32_t)0x04000000) + F o/ |: m" o4 K6 {% k! s#define RCC_DCKCFGR2_CK48MSEL ((uint32_t)0x08000000): a5 ]+ T4 z6 r) [* J #define RCC_DCKCFGR2_SDIOSEL ((uint32_t)0x10000000) # z( \4 ], e- V3 v# }#if defined(STM32F446xx) o: l: N1 o9 u a#define RCC_DCKCFGR2_SPDIFRXSEL ((uint32_t)0x20000000) * O% U) q: K Q4 s6 t5 }8 v#endif /* STM32F446xx */: X& \5 V* X8 a' y* x( @ #if defined(STM32F413_423xx)- f, S f4 y( | V2 f- p) ? #define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0xC0000000) * C; R- H8 l) i9 j1 T5 r2 Q#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x40000000)& j8 E0 r9 M1 {( X/ C" y #define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x80000000) ( R: [8 C9 p$ j. @: O#endif /* STM32F413_423xx */ % k, {7 y8 m# @5 U( T. s3 s#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */* B: c+ ?0 {# b7 N( I/ V! k3 i$ B 0 ~8 l0 Q7 d/ ]/ [5 y8 w8 O#if defined(STM32F410xx)- y E t) f6 D; U" k; p h #define RCC_DCKCFGR_I2SSRC ((uint32_t)0x06000000) / q* p# ? c# P o8 ?7 O- N' G1 r7 G2 L#define RCC_DCKCFGR_I2SSRC_0 ((uint32_t)0x02000000) $ p, a/ r; X [% ]* d#define RCC_DCKCFGR_I2SSRC_1 ((uint32_t)0x04000000)7 a+ k8 w e2 _- p! O7 A+ x) V #endif /* STM32F410xx */: f3 }, M' M$ n0 L : Z+ g6 p. w7 B- S6 y* A #if defined(STM32F410xx) $ z# l: H# ^+ i0 q9 Z) x1 D6 x/******************** Bit definition for RCC_DCKCFGR2 register **************/ " m! J" p! S0 ?8 ]+ v: d# H#define RCC_DCKCFGR2_FMPI2C1SEL ((uint32_t)0x00C00000)0 E6 C' P4 s( w& c! c9 G3 |2 ` #define RCC_DCKCFGR2_FMPI2C1SEL_0 ((uint32_t)0x00400000) / { s4 a" J+ {. O9 G& p( P& t#define RCC_DCKCFGR2_FMPI2C1SEL_1 ((uint32_t)0x00800000) 5 x+ l: I+ D) J#define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0xC0000000) ! b. M/ }: w3 I9 v/ f1 O4 D* X3 G#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x40000000)" u) E% S0 e2 z0 @/ c2 z. x #define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x80000000) 3 j% M0 J' P8 N#endif /* STM32F410xx */4 \3 e/ x4 A! d- ~ 复制代码. Q5 R. Z# C/ m% W# w0 d

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STMCU小助手发布时间：2022-3-31 11:00

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文章简介:	STM32 时钟相关函数和类型

01. 概述
在 STM32F4 标准固件库里，时钟源的选择以及时钟使能等函数都是在 RCC 相关固件库文件 stm32f4xx_rcc.h 和 stm32f4xx_rcc.c 中声明和定义的。大家打开 stm32f4xx_rcc.h 文件可以看到文件开头有很多宏定义标识符，然后是一系列时钟配置和时钟使能函数申明。这些函数大致可以归结为三类，一类是外设时钟使能函数，一类是时钟源和分频因子配置函数，还有一类是外设复位函数。当然还有几个获取时钟源配置的函数。

02. 相关类型
RCC_ClocksTypeDef

/* Exported types ------------------------------------------------------------*/
9 `6 d9 \* U$ D8 t1 a* |4 W
typedef struct1 X/ z6 l }+ Y; B X1 A( x1 Z
{5 s0 O6 a) ~ t; H
uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
7 P& I8 z2 u) M" K( ~
uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */8 o. w& b% s, \
uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
9 H/ Z9 y5 Z. U+ i( C) @2 g
uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */6 `7 I, B/ v) T3 \
}RCC_ClocksTypeDef;

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RCC_HSE_configuration

/** @defgroup RCC_HSE_configuration
o/ x7 y$ W2 H% `
* @{) V* S5 ?8 U1 C ^. x: B
*/
$ E* J8 f! G2 r3 S
#define RCC_HSE_OFF ((uint8_t)0x00); p: U0 O. @3 l# V
#define RCC_HSE_ON ((uint8_t)0x01)
; g5 u0 _6 u+ `, A) f3 _
#define RCC_HSE_Bypass ((uint8_t)0x05)2 m/ W# `: o6 D1 X
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
- w3 _5 o2 j$ q/ a! P
((HSE) == RCC_HSE_Bypass))

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RCC_LSE_Dual_Mode_Selection

/** @defgroup RCC_LSE_Dual_Mode_Selection1 H- x, p/ S0 z" I5 ^/ M9 o' w
* @{( s% K4 L1 s. f0 |5 N- I% U
*/, ?3 T4 j, r8 Z4 T: Q' N
#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
3 I0 r! I4 |- o, y2 H9 ~. S5 Q
#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
: w% u: K7 I/ h# D- K2 L( t$ A
#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \! ?# h3 r/ y: A6 ]5 O& I: Y9 {, M- q/ y
((MODE) == RCC_LSE_HIGHDRIVE_MODE))

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RCC_PLLSAIDivR_Factor

/** @defgroup RCC_PLLSAIDivR_Factor
6 l9 |+ O/ W& z) {1 E
* @{
) |" f* r8 S% E* P. D q
*/
/ G% ]9 W! [" n
#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)( n! ^! w# f m, Z8 Q6 B7 ~
#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)* Q- ^: L3 f0 K# `& H
#define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)7 G, s% b1 G( j2 [/ x
#define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)
3 t0 ~# |. { m: \1 e! F
#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\! T y* n8 T+ x+ w
((VALUE) == RCC_PLLSAIDivR_Div4) ||\
9 x: `+ Z- d1 X1 ? |( y
((VALUE) == RCC_PLLSAIDivR_Div8) ||\
; }4 m7 a% h$ r9 F! p3 x7 H9 N
((VALUE) == RCC_PLLSAIDivR_Div16))

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RCC_PLL_Clock_Source

/** @defgroup RCC_PLL_Clock_Source
2 O. t2 j$ t' ^- d* U q' T4 [
* @{
; |, Z4 ?6 V% X) t& I3 b# e
*/% v6 h1 G2 a4 C: b3 U. A/ e
#define RCC_PLLSource_HSI ((uint32_t)0x00000000)$ v1 @/ F% I8 L' W2 r' l; e- S" c
#define RCC_PLLSource_HSE ((uint32_t)0x00400000)+ m' m' J; C6 z& X# n+ K8 e- b2 k
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \* B% z0 B$ x" i/ _( @; }! Q
((SOURCE) == RCC_PLLSource_HSE))
8 k; G" e$ P A: f) a! B I2 p
#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
/ T( |3 l2 R8 V; n, v4 z
#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))9 {- \- R; p% ` @ O1 b6 `7 t
#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || 3 a6 Q! D& C% s
((VALUE) == 6) || ((VALUE) == 8))5 o6 q J3 R3 e4 \* g4 g
#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
) O# Y; G0 u! C* b0 e% b
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) * k5 o, f- k' |6 _6 f7 q
|| defined(STM32F446xx) || defined(STM32F469_479xx)
. v) j0 Q$ X( [7 p1 h) O
#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))# b7 z n0 u; k4 X- w2 Q0 f
#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx 4 Z u: G# V& a
|| STM32F469_479xx */
2 d* K; F4 X( Q
4 \" _2 o/ R' ]/ }
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))) e3 T) p! W* u6 ?; }
#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))) i3 A' z! ^9 [4 W0 `
#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
% w4 f- O9 q7 b+ q& E3 J t, U
#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))* @+ y4 H* e3 E/ H. {+ E
#if defined(STM32F446xx) & A$ o: u8 S) q
#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4)
: b+ |- H3 a9 M; s0 s
|| ((VALUE) == 6) || ((VALUE) == 8))9 m) J$ x- i5 \5 {' T
#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
, T2 Y3 t: s+ S9 {6 i
#elif defined(STM32F412xG) || defined(STM32F413_423xx)
) B1 [0 y A' W% P; [. c# c
#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) 5 x) j* k, O" g* x3 \
|| ((VALUE) == 6) || ((VALUE) == 8))
7 S! V; ]7 K1 m6 J J Z- w
#else
6 x+ S0 J% d D* D
#endif /* STM32F446xx */( Y0 O d, g0 u& {! T" `* l
#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
, t, W' F& C, J0 ~
#if defined(STM32F446xx) || defined(STM32F469_479xx)
% p( b# R$ H8 R( N! N# h. x
#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) % s* B0 ]( H; q
|| ((VALUE) == 6) || ((VALUE) == 8)); D) s) J% \1 H
#endif /* STM32F446xx || STM32F469_479xx */
% N3 R. x& @; L! e1 ~. T
#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))% d: {7 P1 t% D, C
#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + F c: Y* m) \8 c& O# Z
: [3 y! v0 z0 N0 j. c' f
#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))' z& U1 w6 Z+ l) ^
#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))( X# C1 y6 q( D7 `' ]1 ~
3 K* {# d$ V' e
#if defined(STM32F413_423xx)
' T, N1 }3 M3 f2 `5 A
#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
. ?8 |3 X9 c- |; I0 F' `
#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))- g" _; ?% A, V; T) S( N% u6 A8 ]
#endif /* STM32F413_423xx */

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RCC_System_Clock_Source

/** @defgroup RCC_System_Clock_Source 7 Q+ Q& t. Y- r# C' E$ Y
* @{
$ _! H2 }1 L- c6 J7 s6 ?0 x d
*/
% u" b' j* O$ @6 K/ Y' O
& g, c( Z8 L/ ]6 e p
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)2 F- o* q! e% h5 H" G5 p
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)+ G3 n! i# j* O
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
#define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002)' e" f( L c9 O# S2 ~( W7 _# l5 d
#define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003)
- v6 o* \# M! [% g- F1 U& d
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \+ D6 h9 k: _$ S E
((SOURCE) == RCC_SYSCLKSource_HSE) || \- x7 a& s: V3 q; W3 J
((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \" b/ s3 A5 e+ z6 M
((SOURCE) == RCC_SYSCLKSource_PLLRCLK))
. z2 W( S) x2 M$ p; _4 c
/* Add legacy definition */
) C% }+ s/ F9 ^3 {* ?) ?9 O8 C+ R7 K
#define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK
! H$ Q! P: J E. B: m
#endif /* STM32F446xx */4 B5 R* o+ o$ ]" u* r5 C
) D* a4 J o' x3 f& x
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx)
) E. ^; [2 i) Y9 h& Q% Y
|| defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE)
$ s2 e2 ~* t! T4 W0 D. R% C
|| defined(STM32F469_479xx)9 _ i/ h' K( _# k( N4 o$ J( ^
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
- |! F+ T6 W: S( ?
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)+ R3 S+ r4 }4 E3 }/ x
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)) h1 m' o5 r5 ?' Q; ^, [5 L
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
( E7 k$ G4 ^8 n2 X7 U
((SOURCE) == RCC_SYSCLKSource_HSE) || \2 `9 K% X' T( s+ O
((SOURCE) == RCC_SYSCLKSource_PLLCLK))' o, D* z4 z! w
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx & b8 v0 {3 v# h' ]$ l2 @& U
|| STM32F410xx || STM32F411xE || STM32F469_479xx */
" I1 X! S0 m( X% r1 ^

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RCC_AHB_Clock_Source

/** @defgroup RCC_AHB_Clock_Source1 u8 Y0 P: Y% \) ]8 Z3 p* K W" N0 o
* @{
6 d5 x0 i; O0 d* v& [
*/
5 H9 S/ j. @ R2 K
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
/ v, s9 @ V( E4 [- M
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)! a0 n$ {: P/ W) M8 j
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)* B% {1 q' r# {& P6 ]
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
! r9 a3 P3 f% K- `8 D* s
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)7 B3 G; A# w. S1 M) ?" U
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
1 i7 C/ Q# R4 [: x3 b% \3 E2 P
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0): ?5 J k1 ? \; j
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)+ Z4 K3 R& k" A' \8 }9 V
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
- e7 L6 P6 u" R; k+ ?" ^) x8 y
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
[- ^6 q8 `# A9 w
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
/ n$ O( S# I5 t! b3 B3 ^
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
6 t$ J5 z6 t; ~4 O" u( u6 j1 e4 E
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \0 `: [6 ]# W$ R* Q4 f, s
((HCLK) == RCC_SYSCLK_Div512))

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RCC_APB1_APB2_Clock_Source

/** @defgroup RCC_APB1_APB2_Clock_Source
% E' K! p/ B& _3 M
* @{% _3 {$ E$ C1 D# U z0 U; R
*/$ N+ `& ]5 u6 l, [
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)/ J- I1 H7 }8 u( R8 _: z: P: h
#define RCC_HCLK_Div2 ((uint32_t)0x00001000)
, ]' T I9 N+ f7 p
#define RCC_HCLK_Div4 ((uint32_t)0x00001400)/ ?2 b& ^$ j# R
#define RCC_HCLK_Div8 ((uint32_t)0x00001800)
8 I6 j3 H1 K. I, h; z2 H: Y; {
#define RCC_HCLK_Div16 ((uint32_t)0x00001C00): S2 D9 R) r, \! a; ^7 D
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
* g! X* k* p0 k/ \' Y
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \! g' Z2 W$ B% e( V9 Y9 P
((PCLK) == RCC_HCLK_Div16))* q# E8 J6 U$ ?9 f

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RCC_Interrupt_Source

/** @defgroup RCC_Interrupt_Source
" N5 j1 `1 t, ^: z3 e! @
* @{( {3 |( Q5 b8 M# l3 A) ~9 k
*/5 f: @& j! M( i# k; w1 f" U1 s
#define RCC_IT_LSIRDY ((uint8_t)0x01)
8 H/ `1 d* R8 ], z( f: G
#define RCC_IT_LSERDY ((uint8_t)0x02)
' D( g8 X6 M( `, ~! C' u
#define RCC_IT_HSIRDY ((uint8_t)0x04); m8 f; Q, |: w" A
#define RCC_IT_HSERDY ((uint8_t)0x08)
9 |: b c* H) J
#define RCC_IT_PLLRDY ((uint8_t)0x10)
& S: }2 d4 }+ o0 D. |3 ^
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
7 s2 I" C! v( G g3 b& Y
#define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
9 }8 D& | e+ L
#define RCC_IT_CSS ((uint8_t)0x80)) G6 X {& a$ u. \4 t
L% c5 v+ l. X: [( G
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
) ]; W) t( J, y7 P; v2 _0 z! D
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \7 a+ S+ d1 y; s& T6 @. G8 k8 ?
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
2 q( T* D a" K0 a6 O9 {
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
& B+ R2 H1 q8 x4 @
((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
* E) ^0 M. O) E" d5 ^* b
#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)

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RCC_LSE_Configuration

/** @defgroup RCC_LSE_Configuration
8 n3 K# O4 S8 s2 ^
* @{
- i+ T. V* w# E" }: I j
*/
& {: L R) \, U5 b# W
#define RCC_LSE_OFF ((uint8_t)0x00)! f! H: X& w6 ?/ c2 i4 j
#define RCC_LSE_ON ((uint8_t)0x01)
9 @: q6 z9 m+ k+ a& N! f0 B
#define RCC_LSE_Bypass ((uint8_t)0x04)4 a/ [, d4 G0 y
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \! n# z$ J& _$ V; S7 s2 c
((LSE) == RCC_LSE_Bypass))

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RCC_RTC_Clock_Source
1 r% M* q! l; p: S3 B! @

/** @defgroup RCC_RTC_Clock_Source U, a( I# b( h
* @{8 u4 c' B1 I; \9 s& F
*/
3 q; s/ Y- R {. g, }0 ]" Z% M
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
# {6 E |: c- Z. Y
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)' X; R" z8 t4 O$ b6 F9 X
#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)) l! n4 ?* ]/ C: ]. a8 v
#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)
8 T$ x( L+ G. k) p
#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
9 o6 \ d: p8 V
#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)6 w7 }( Y1 e; V
#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
5 o; |" V! J8 D7 ?; o4 @
#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)7 ~" ] e5 ~, z( D# Q4 D
#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)( r1 t" s+ r- i- R
#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)7 E5 t" s$ T6 ]9 v+ w& D
#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)) C4 d! R8 z+ \
#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
% A9 E* j2 a# B! w
#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
8 \+ |" e0 ]7 I" P a3 f
#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)4 Q; k1 m& [2 i5 N* F, j7 s
#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
! ~7 @& X' s: ?/ e! n) c
#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)
: `* f- b6 |6 Y- u8 g/ F
#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
1 s- V/ ?9 w5 ^/ I
#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
) T0 Z( b6 c5 v1 @6 |4 a, j) M) R; l6 q
#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)- t& ]8 \2 O! \+ H% \+ y0 p
#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300). K9 R% B5 Q3 o0 @( O7 y
#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
% h1 H3 E: N+ R! c
#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)+ `7 i8 b' Q2 J9 Y5 n, S$ C& \- A, ^
#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300), O" A) p( z1 c
#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)
0 f' @9 {/ f# E2 ^ {1 H5 ~
#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
|' x* @3 G0 R5 g Y& b# a
#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
+ N9 t- c1 e; g$ {
#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
4 Z g9 }& R3 @
#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)8 ], Z, D; y" U) u
#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)) H( F$ ~8 m2 e& b* ], D! b( u
#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)0 [% e- q+ e+ H4 `) \1 B
#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
" [, M" ^1 t- J9 B
#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)$ @$ e9 l8 I: M4 x i
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \+ \' l1 M/ w3 z- ~; o6 ?3 T
((SOURCE) == RCC_RTCCLKSource_LSI) || \* Y( d+ f) h; ^7 C
((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
: i9 a1 z5 W: A8 M0 h5 a# ~
((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
& w; c9 j6 Z! d1 B9 J7 Z/ N
((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
$ j; Q& T* I" d0 b1 w" a
((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \6 ^) c4 U" |0 m+ u' A; [
((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
1 k; R4 X& Y, c. V
((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
" D9 Y8 B" P& B x
((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \, F3 z+ w0 `9 p* _9 B, G
((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
; @# X# o* q( |& w
((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
! e2 {( h& d- E' t3 r
((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
; U8 U7 x6 }/ g9 U
((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \+ }. x$ W3 \% `' f) L' ? P6 X
((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
' n: z5 D0 }: r" F
((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
7 J! {( a9 `, x% L
((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
7 f. P. Z/ h, j* n
((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
. @( X4 J7 b& W) F
((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \$ `0 ?' u* h: Z
((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
3 b+ @3 @& |1 v. r
((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
5 y# `( v. d0 _( Z+ b" [5 Q
((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
1 q- i7 E. T, x+ |, t& y. S
((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \) q4 H8 v& x7 ]' k* s( t, }
((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
$ ~) v2 S8 p0 A9 r- G
((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
9 T! l0 o5 m/ y
((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
S) y& Q6 v7 W# [) @. |9 D5 u, ]. _
((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
, E) a8 z: e& ?" s1 _( g: g
((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
; o# A: ~$ [9 a& w
((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
0 T* o4 ]% O/ ~, }5 A7 D" p) T
((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \) R4 n* ]3 v" ^" A7 \; p* f" p
((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \6 i- h7 f" }+ S$ r8 a( V
((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
: M# L% J" L4 A8 Q) @
((SOURCE) == RCC_RTCCLKSource_HSE_Div31))

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RCC_SAI_BlockA_Clock_Source

/** @defgroup RCC_SAI_BlockA_Clock_Source
/ H- \1 b* D0 _% I5 J
* @{/ x5 |8 q4 i& J
*/6 N' d! h- p) U5 @! ]1 Z6 z
#define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000)
% M) E, {5 a6 r8 y3 q Q; s
#define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000)) @, `5 F9 H% M4 r7 w" o9 T
#define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000)
& j/ J. P8 O! v% l+ L, G8 c
4 i" ^: h( R, S( ^. r* [% E
#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\
) H9 y& r# z% t4 X3 ?" O' i4 C
((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\ P0 a; P( Q( k, B7 k7 k: n4 ~
((SOURCE) == RCC_SAIACLKSource_Ext))

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RCC_SAI_BlockB_Clock_Source

/** @defgroup RCC_SAI_BlockB_Clock_Source
! T; z7 D2 c! Z
* @{
3 T+ Z9 Y6 l( ~# v9 Z; Q
*/$ A$ I( ]5 t+ [0 G6 p' f/ B
#define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000)
7 R$ M* o8 P' z/ Y5 h3 a5 R
#define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000)5 A9 v7 N# _: \! @+ ~" u
#define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000)
* I& r% g/ k6 G& _9 q% B* g
+ G0 Z0 M0 L7 H5 _5 w) w7 g, q+ H
#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\
; \' s5 x+ M: b& m, u
((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\
- Q7 H2 h$ `* p9 f- m
((SOURCE) == RCC_SAIBCLKSource_Ext))

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RCC_TIM_PRescaler_Selection

/** @defgroup RCC_TIM_PRescaler_Selection* a- ?6 c, {# }
* @{7 B3 ]3 @; _) t4 z1 V* J
*/- D$ x$ ^- f% a% j# [
#define RCC_TIMPrescDesactivated ((uint8_t)0x00)& P4 w: g# n7 Q& t3 _
#define RCC_TIMPrescActivated ((uint8_t)0x01)
2 F$ r# x8 G, Q! Z0 G9 @! x
0 C5 d- A! p' T7 H0 [ h
#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated)
0 C, q. c4 q' C
|| ((VALUE) == RCC_TIMPrescActivated))

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RCC_AHB1_Peripherals

/** @defgroup RCC_AHB1_Peripherals
6 R1 I9 J' S; @2 h2 b5 l/ y# y9 x
* @{
$ ]3 |3 Y5 z8 z* |$ F8 ]
*/ p ^8 y/ P. Z1 ~& |6 s
#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)9 _, k1 \1 f3 c2 L& ^: s' g
#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)
4 ]3 \0 P$ t" Z$ m, q% R& H
#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)' V* Q; c7 s* W- @5 K0 w
#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)! b; p$ F9 j5 ? M1 C7 c
#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)* Y R% `. J; F' }2 O
#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)8 A& U' f" M+ F
#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)( A' F( J, i* W% e
#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)$ R+ p7 x: r% G* k3 B( N
#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
- c! D9 G, r/ ?( q
#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200)1 d/ j2 H% J1 y' B/ h/ l) v
#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400)
9 M- `; Z& y# K I9 u( `
#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)3 b: e' A. d) f2 X4 h
#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
; v3 B2 S8 C4 G8 v
#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000): w; z, U; i0 Z M8 Q
#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000). A8 u% M3 y" p) Q' Q
#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)9 W$ v- C, x. D* [( s G9 ^
#define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000)
! s$ D" H; Y [
#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)( w; D; H- |; t
#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000). ^, ^" t" L: J/ p( x$ ]
#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
#define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000)
9 h; U+ `: |7 g
#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)* n' \3 q' {4 t, v j' R- S o( e
#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
# W# a1 a- y! _! ^) V; X% ~
#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
. [5 w8 g$ H0 Q$ |1 t
#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
( a2 f% e& v# P* r& c6 p
#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
- t' R8 j4 a9 x, z/ x
#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)0 B4 _" k( Z$ u* C# j9 c
% N5 @& r2 h: U0 G) ^" s( B$ P
#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) 7 b3 E7 j7 N$ e7 f) ?
((((PERIPH) & 0x010BE800) == 0x00) && ((PERIPH) != 0x00))! ]! t1 l2 U- E* `- m
#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) 5 @! F# v5 J5 W3 `* \7 n& U
((((PERIPH) & 0x51FE800) == 0x00) && ((PERIPH) != 0x00))
$ N, c7 ~4 w: o* D
#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ( X4 j G3 i3 ~( s+ n5 Q" d: M
((((PERIPH) & 0x01106800) == 0x00) && ((PERIPH) != 0x00))
% N `3 ~! k3 u" j. [

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RCC_APB1_Peripherals

/** @defgroup RCC_APB1_Peripherals
& f b/ `/ U6 v. M6 @0 A1 {* m. d
* @{
s6 O6 y: D* G8 b( H' e8 [
*/ 3 }0 U! T- P- L. ?
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) L6 i6 q' b- L% s- |8 y* h
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
. q9 C- j# z# q: ]% [
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
7 l. w; ]+ \' F7 b# L* Y) c) f
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
3 U; H; w4 U0 o3 c9 G/ ?; G# v4 t
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
" N: }8 U& B8 c# E! G t$ I0 [2 z, a
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)4 s) A, A. \% I. J
#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)2 T( x+ _; y; h: |
#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)4 Z* p" n B* V( I0 Z1 J$ p6 J
#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
: d" E4 n" C' b' j: t* Y$ d
#if defined(STM32F410xx) || defined(STM32F413_423xx)
( A! @ `! N. l3 B. M+ w/ M2 {
#define RCC_APB1Periph_LPTIM1 ((uint32_t)0x00000200)
. Z" t% w& c; B, k6 w ^; J# {
#endif /* STM32F410xx || STM32F413_423xx *// ?1 Q* U$ t4 S; ?& J
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)' y/ s# u/ H4 X7 \& m
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
5 s2 g4 J' c. A5 v9 h% @9 L
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)# C9 U d. F% b$ x5 _4 E
#if defined(STM32F446xx)
$ _2 ?: b) D- W c# o( W
#define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000)
$ ]: r, ~% I5 _: c p9 T
#endif /* STM32F446xx */ ( M" t3 p5 a1 n; [$ f' R
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
& b% H. w" m# S6 q8 f% Q1 [2 h
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
/ U* j A1 a4 s& F* Q0 r
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)6 I+ j. A* l) F& _
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)7 h1 v4 {9 e- ]; u( O1 @# q7 `/ c
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)! s2 Y: h( E) v& g
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)7 `9 e6 Y9 [, ~
#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)/ T" I& O: v! P/ D" {9 t' }0 L! _
#if defined(STM32F410xx) || defined(STM32F412xG) ; ?. [- ^# o* d7 Y/ h
|| defined(STM32F413_423xx) || defined(STM32F446xx)
" S0 V) z( J: _* Y. C) B
#define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000)
. {* k$ j+ k: W' c0 ?& g( \, b; u
#endif /* STM32F410xx || STM32F446xx || STM32F413_423xx*/ 4 K% v' T6 \4 p/ k
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
5 s4 k" s4 E# _! V2 \( H
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
' A; ?: x4 Y0 S+ x. g8 I& `% y
#if defined(STM32F413_423xx)0 \$ l5 t3 w/ [. a4 R1 X4 l# k& \
#define RCC_APB1Periph_CAN3 ((uint32_t)0x08000000)
5 ~8 g/ n$ h1 E
#endif /* STM32F413_423xx */9 x8 N) l8 E) q3 K+ C U* S- f
#if defined(STM32F446xx)
) O2 W" z G$ t/ Q! ^$ E$ m
#define RCC_APB1Periph_CEC ((uint32_t)0x08000000); Q) a2 _1 K* H4 q/ A% N; u* M
#endif /* STM32F446xx */
2 y% K3 @, W) r- _" v: d$ y
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) a0 l% O6 N& s
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)) C8 e3 o% T/ f1 k" {" h
#define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)- M. }8 R4 H, W5 B& q
#define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)2 j3 L6 P/ ^. j) p
#define IS_RCC_APB1_PERIPH(PERIPH)
/ _* b( l `2 J( I1 i
((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00))

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RCC_APB2_Peripherals

/** @defgroup RCC_APB2_Peripherals
$ r( L: R, ], S) o( R4 ?
* @{7 |" j& l* d" _
*/ & T6 |9 K2 U; g: V' D. \
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
1 q* ?+ J8 ~+ p! `. g) L% B
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
6 R4 l/ | ^, x# [7 Y. ?
#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
! k5 w9 X+ }* [
#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)7 S& i* b( k# f9 E; d8 T
#define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
1 g+ e7 ~ b3 T: i
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)
$ g3 V/ X: M+ g) \6 c3 I9 F
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)7 q# z$ H1 E7 z1 Y: L
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400), O) Q. `* k7 g
#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
2 d+ n4 v* i( A& h6 h! n3 d- Z
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)8 Z! p, H+ s! K( K2 s4 E
#define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000)( u! P. B, ]1 }& v* b! y
#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
7 }* | c7 b- p* U: x+ N
#define RCC_APB2Periph_EXTIT ((uint32_t)0x00008000)1 O6 {1 t3 b- P
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
% T8 T* t- t3 n9 i o
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)7 V# x, O a- G
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
! I s9 b, [" v: `2 I4 M1 Y4 R( D
#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)
! _, [0 I$ [" C) v! J# _) ?
#define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000), B V" ^0 ~3 g6 w; E- s
#define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000)3 N2 M' u5 e6 L3 j
#if defined(STM32F446xx) || defined(STM32F469_479xx)
$ k/ U4 b& ~% E- e4 T
#define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000); q) I; {. q( h- m, Q' N/ ~* _) ^
#endif /* STM32F446xx || STM32F469_479xx */* w& M2 }* Q) k: S) S" \
#define RCC_APB2Periph_LTDC ((uint32_t)0x04000000)0 e8 K7 k) ^8 x8 m7 ]! L" Y$ K
#if defined(STM32F469_479xx) t0 s5 \9 ~/ {, Q
#define RCC_APB2Periph_DSI ((uint32_t)0x08000000)
, m2 |6 o" F. |) J2 k( Q6 N
#endif /* STM32F469_479xx */% g- M9 Q Q& x+ q o
#if defined(STM32F412xG) || defined(STM32F413_423xx)
' s& m! \8 L5 v) L! H
#define RCC_APB2Periph_DFSDM1 ((uint32_t)0x01000000)
2 v# i9 N; Z) J! D+ }9 G
#endif /* STM32F412xG || STM32F413_423xx */& s- Z7 k( q3 t
#if defined(STM32F413_423xx)
4 N) Q: E2 C; q* x
#define RCC_APB2Periph_DFSDM2 ((uint32_t)0x02000000)$ d1 V5 `0 r5 q
#define RCC_APB2Periph_UART9 ((uint32_t)0x02000040)' B0 S+ T+ p7 Q7 x/ ~! l
#define RCC_APB2Periph_UART10 ((uint32_t)0x00000080)% m M% i4 I/ s0 H
#endif /* STM32F413_423xx */- K' J' T% Z* A/ l# N* q
8 \- ^4 ~1 P7 p3 i' N
/* Legacy Defines *// Q0 I- n$ l1 C x' s7 Q
#define RCC_APB2Periph_DFSDM RCC_APB2Periph_DFSDM13 n/ |. k; p% X9 w- V# C( H
c Y/ x! Y+ U( q
#define IS_RCC_APB2_PERIPH(PERIPH)
+ Z$ I: b8 x- j) H7 r
((((PERIPH) & 0xF008000C) == 0x00) && ((PERIPH) != 0x00))
2 R4 W \& b n3 B) H7 m; }
#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ' s+ s) [9 K+ q8 J7 V
((((PERIPH) & 0xF208860C) == 0x00) && ((PERIPH) != 0x00))

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- U, N2 f5 o% Y: Q+ G$ A1 V# I9 M* nRCC_MCO1_Clock_Source_Prescaler

/** @defgroup RCC_MCO1_Clock_Source_Prescaler3 F% E. u. ?: m& I1 N! c
* @{9 {* L9 L# p4 k5 p! V/ F7 X3 Q
*/* g& s" K! l$ |7 f* j: p( G, \
#define RCC_MCO1Source_HSI ((uint32_t)0x00000000)0 O( Q) H# y7 N2 Q, f
#define RCC_MCO1Source_LSE ((uint32_t)0x00200000)0 i) a; v( A) ?* }
#define RCC_MCO1Source_HSE ((uint32_t)0x00400000)
4 e- _+ j. L; e$ y
#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
$ u# ~: D. c9 v- [4 g/ |
#define RCC_MCO1Div_1 ((uint32_t)0x00000000)
1 z, [8 N+ r* g
#define RCC_MCO1Div_2 ((uint32_t)0x04000000)
$ L# k0 u o6 J' C6 c0 j
#define RCC_MCO1Div_3 ((uint32_t)0x05000000)7 u4 v& N D! a) M+ h- D* O
#define RCC_MCO1Div_4 ((uint32_t)0x06000000)
3 D/ U5 k2 p- g3 r' T5 [
#define RCC_MCO1Div_5 ((uint32_t)0x07000000)& C/ A2 f& k$ }: p; U. H6 Z
#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI)
0 q6 U8 C6 R9 O) P; }7 C3 N5 O |. [
|| ((SOURCE) == RCC_MCO1Source_LSE) || \
- Y9 I5 E8 H, x' v0 m
((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))( E4 D. M0 q+ |: c& e0 q
U5 y4 F ~( k0 W- p2 }
#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \/ g4 F. j4 j/ j4 }. F c
((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
/ ~* C/ ^5 E, Z
((DIV) == RCC_MCO1Div_5))

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RCC_MCO2_Clock_Source_Prescaler

/** @defgroup RCC_MCO2_Clock_Source_Prescaler5 i0 @" C8 ?0 ~! O3 A
* @{/ J% b6 l: C1 O) v [- X
*/0 v2 H1 m: M0 J8 y. h, m
#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
2 I2 q. k$ z) Y4 `: I( X- w
#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000). Y. n/ C4 O7 J( M
#define RCC_MCO2Source_HSE ((uint32_t)0x80000000)& z6 C! _9 K- w/ k) N- \
#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)8 q9 [/ M( ?, d7 f
#define RCC_MCO2Div_1 ((uint32_t)0x00000000)2 X5 j7 z- v. z( @. a+ ?" g& F
#define RCC_MCO2Div_2 ((uint32_t)0x20000000), l' o; @$ q% d: l) r' h) `8 X
#define RCC_MCO2Div_3 ((uint32_t)0x28000000)
) ?9 m$ v4 t" T6 A5 h* O
#define RCC_MCO2Div_4 ((uint32_t)0x30000000)
- J2 _, F( E* j6 Q$ B7 i0 Q% K
#define RCC_MCO2Div_5 ((uint32_t)0x38000000)
9 Y$ \& F5 d- M
#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK)
+ K E* c9 L$ S
|| ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
' p r2 x/ h, n7 I1 O
((SOURCE) == RCC_MCO2Source_HSE) , t/ ?; ?+ S. ^3 ~
|| ((SOURCE) == RCC_MCO2Source_PLLCLK))
; G6 X5 Q u! s
9 l; m* G0 r, m5 w
#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \& M& ~, }) }9 Q; ~+ z+ N# Q
((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \% Z' @# C' T; U# b W% O' Q
((DIV) == RCC_MCO2Div_5))

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RCC_Flag

/** @defgroup RCC_Flag
% u+ C; Z% y. ~1 P' V
* @{
; A2 W. Q( p) }
*/
6 f( a% {0 W0 z& z; y7 E+ {, C
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)0 g" C) }, b$ \) j, I0 d7 c
#define RCC_FLAG_HSERDY ((uint8_t)0x31)0 y2 z' B+ v4 T6 t4 I; K# \2 [
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
, [. {6 k9 w! ?! c
#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
6 O* u- e7 o+ E5 q4 l" ]
#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D)
( q1 p1 f- {3 q- h
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
9 q* O: ^4 Q2 S( b# s
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)* S6 m7 f8 v6 w1 V1 j
#define RCC_FLAG_BORRST ((uint8_t)0x79)
& s6 u) A K7 {: Q, f# v! {8 E
#define RCC_FLAG_PINRST ((uint8_t)0x7A)" h0 E2 J z, P2 n" T
#define RCC_FLAG_PORRST ((uint8_t)0x7B)* R* ~* a! k* A) F `- W8 U) V5 U1 l
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
3 ?" B/ p$ K" {0 o+ ?. n
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
5 P8 K. @- K; ]+ V' M3 N
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)( L7 z6 s/ f6 D7 G0 J
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F); x, A3 r6 a7 n; Y' B6 J3 C
! q; Y( r. M6 \; W( U) V6 G( ~
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
) R' j7 S+ U7 ~4 n) l- f2 y/ o
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
1 q, r/ L0 f! N4 z) \# x2 r
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \$ B5 i% k' b* D3 V5 U% `
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
- t# ]' b! O- Z. T
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
9 J% [# W9 v# u
((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \2 Q5 v+ p8 K% |& F
((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
, h4 W( O H) @3 f' p8 W5 C8 p
5 I3 g! }$ M" V: e2 `
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)

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03. 相关函数

/* Function used to set the RCC clock configuration to the default reset state */- y1 t: N4 L" Q. o/ m g( E8 ^
void RCC_DeInit(void);
7 X- c0 f+ }; [, E
/ q2 Z0 k% P- ^7 }
/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
" `( n4 c' p' ~1 \1 b) T/ p1 n
void RCC_HSEConfig(uint8_t RCC_HSE);! b5 H0 |9 E) ]% {% P$ y+ _
ErrorStatus RCC_WaitForHSEStartUp(void);
1 H3 C& n6 Y# f, G% P0 x% [% v @
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);2 ^ m# s1 |- E% y1 M. Y
void RCC_HSICmd(FunctionalState NewState);
5 v, H+ T5 b) x* F+ `9 C$ s5 U f
void RCC_LSEConfig(uint8_t RCC_LSE);: `. Q3 z$ W' \1 ^7 ^
void RCC_LSICmd(FunctionalState NewState);' q+ d6 T o7 H: i: g( H
* S" J( t6 X; \4 } L2 u2 o& o- R( _
void RCC_PLLCmd(FunctionalState NewState);' ~$ p3 T- R% A3 [& X
( W$ V* U9 x; x& j. e' F# p2 ~
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN,
`$ v* h9 h1 o( ?8 q6 m' I
uint32_t PLLP, uint32_t PLLQ);
; T4 j8 J. i$ s& W- L
/ ^: h8 M9 g; s7 g" f
void RCC_PLLI2SCmd(FunctionalState NewState);( k9 A6 n3 o9 `5 Q3 n4 ^( _, z
- Q/ l' [3 s' E8 d1 q9 l; j( r' i
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
1 o. O, s3 r6 l7 G! a
% g8 Z# L6 L- V& t5 M0 H$ U* k
: t- r8 x# b `7 t
void RCC_PLLSAICmd(FunctionalState NewState);) Z) z) n+ G0 U# o9 C# d
* \! I' Y0 B, f: M# j
void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);5 y& H0 E$ d! t" \4 Q" j, e
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
T: Q4 `( }, Q
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
5 P+ x# m' A' N) I$ d
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);& t* f) G \; q# k
$ X/ i& [# [, i0 T* u: b
- Y* C' Y+ v; R) \. X/ a/ F
/* System, AHB and APB busses clocks configuration functions ******************/& u/ V5 R2 M6 u, X9 c" ]3 X* ^; ~
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
& y+ G s& E' `6 f# C/ P7 n! M
uint8_t RCC_GetSYSCLKSource(void);9 P g$ y- t. ?& F9 l
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);8 Q. P2 q$ Z: G' u7 W8 I; J$ N
void RCC_PCLK1Config(uint32_t RCC_HCLK);* J2 E* b% h7 v* n/ W0 m
void RCC_PCLK2Config(uint32_t RCC_HCLK);
' B+ X U5 P, v- J2 _$ ~. E
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
2 _- e+ X) B {: L" t
, o* x* I: ^/ h1 T, n/ ?' s* y* e
/* Peripheral clocks configuration functions **********************************/. i+ Q$ R1 s, ], y) B
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
5 I+ \( h0 F4 j( Y# ^
void RCC_RTCCLKCmd(FunctionalState NewState);9 |1 J8 @! t9 n5 a. m6 x4 W
void RCC_BackupResetCmd(FunctionalState NewState);
4 v; s8 W/ ~ l, w0 N. Y( I& e
% K" i% N9 U' @0 Q# s) g- U3 A
# ^9 r$ {( }3 u+ s1 ~
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
' ?& [+ p# u! S' B8 _
" Z* m/ I8 l! D, t D
) ^6 M1 n% ?" O! x2 N4 k1 k6 W
void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
" i1 f6 D+ U s0 S' d+ {
void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
/ M; D, B0 ]7 n
9 M8 a$ |; `9 @+ @& ?5 k
( p G1 H& S/ u
void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);
& V0 g9 Z9 s8 X9 F9 H. {1 v/ T
void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);
1 I& S8 I' r! {* ]" i+ t$ \0 T
7 I! F& `5 f! J3 M
0 F; ?2 e9 [7 f, H. q5 o& S( n
void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);
. E/ r/ L' z- K
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);" n4 O. n* p( O$ b6 Q" T5 f; y
: ]6 U' J1 f% R: p2 l- Y! y
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);; ?& h" Z/ C# x
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);+ ^) H# |7 ?1 G
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
; _- I8 f1 ^$ S. t6 {: S
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
4 ^" B) b; e7 b8 Z; a
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
) I# T& {' R1 l3 O/ {3 P) h2 {
* x- t* l$ u- q* c6 K' D* K
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
4 }9 ~, c4 R! T0 R( i
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
/ q: d- K8 h/ m+ X2 Z
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
8 Y. w% \' U9 |' r" ?' N" y
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
. G. r' T: ]- S3 T- \
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
3 k# t- N6 z1 r) o* m
$ @$ R5 v8 t# d! D2 z; B
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
& z4 e0 `' c( [4 i0 {) o( g
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);4 v0 \+ H& F7 w$ B$ q- k
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);: k/ V+ s7 k/ K1 `9 |" o. H- B
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
7 E5 j" O- `" o( L) `$ |& d
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);1 H# a2 ]" d2 t8 M) ^7 f
/ N( k$ Q( v. a4 O
& x& l R7 R0 a% M+ l1 j, [& x
/* Interrupts and flags management functions **********************************/
: ` [2 h) x9 d8 ^ i
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
. b$ E+ t0 R' O+ n& Y) v
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);6 n* a6 b7 h) B* ]1 u/ E& I
void RCC_ClearFlag(void);- M+ E o2 i. N1 C0 F$ p0 M1 I% D( N4 {
ITStatus RCC_GetITStatus(uint8_t RCC_IT);% o9 p6 h. ?, {2 M" F
void RCC_ClearITPendingBit(uint8_t RCC_IT);

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04. 结构体封装

/** % a7 Q, k- [4 q% w/ }
* @brief Reset and Clock Control
. @" z" `! j4 }# V: M9 Y
*/) ~0 `3 l$ c2 _2 n l
/ P7 B& k, W" s* X9 {
typedef struct
( N! q. N" p: j
{
3 F5 ~/ M0 x9 }
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
# w6 g* D3 `9 V5 m9 g
__IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */7 P& G5 N# R0 G; ?7 j) V( F
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */# a: c/ c" D: R) C: E
__IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */, |: H0 Z! a# D6 l
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */; h; H$ H, z; f8 _. Z* b
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
0 k: t- ~+ m# A- j; b1 R
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
; f' K: b0 M8 G, h; ]
uint32_t RESERVED0; /*!< Reserved, 0x1C */
1 z% N, E4 y7 A
__IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
; Q" y+ s" e0 F v6 X% Y; U
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */& O# K) R4 W& W
uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
0 e# J$ v/ X- \: j) u
__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
6 q5 @- D' s' n) w
__IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
5 s5 J+ E6 r7 d- l4 p: x) W
__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
6 [, M% L8 C; k# o9 ~$ J7 j
uint32_t RESERVED2; /*!< Reserved, 0x3C */
4 q' Y0 {$ P/ a; p6 B
__IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
- e- i2 H1 u3 j9 m" T9 i. `( Q
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */6 D/ t0 v7 }1 d7 X
uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
" z7 ~7 ~( A8 W* g$ }2 Z3 k8 O
__IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */: N o1 L( d1 @+ a' g9 u) l# c
__IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */' T! \1 x' W6 f g
__IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
5 l* i9 z4 O, L8 e/ i X' S
uint32_t RESERVED4; /*!< Reserved, 0x5C */) {7 Z& f' S/ W+ T
__IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
) _2 |8 M. v% }4 t$ z
__IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */, s4 Q. f1 \* t7 o" ]
uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */) m, }# W3 A$ [6 m1 k1 \. T
__IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
3 N) g/ g. P7 J1 p$ Q3 ^
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
- c, i& A8 U% T: V* O
uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */; n: J5 S4 i8 H
__IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */- R- o; G; ^2 e
__IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
B! w/ Y& M2 C2 w v0 p
__IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
2 ?# r/ T8 k3 ]; r# I5 G3 F
__IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ B' ]7 _6 p! g
__IO uint32_t CKGATENR; /*!< RCC Clocks Gated Enable Register, Address offset: 0x90 */ /* Only for STM32F412xG, STM32413_423xx and STM32F446xx devices */
* F$ I# @: ?# P! i* f. r m0 F) Q
__IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */ /* Only for STM32F410xx, STM32F412xG, STM32413_423xx and STM32F446xx devices */
/ G- }$ O$ l2 N- d9 Z4 f1 g. n5 U
} RCC_TypeDef;3 w6 I9 B, U# C% I! ]* [

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05. 其它

/******************************************************************************/
; f& r7 i; _; W7 j" S6 ]+ |
/* */
5 w( C: O3 J3 o% J$ r" H& N
/* Reset and Clock Control */5 A: s' w7 t8 m+ q
/* */& S8 s/ D; x; q) e8 }
/******************************************************************************/
. c1 M) K) o# Q c& ]9 T ]1 L
/******************** Bit definition for RCC_CR register ********************/- t3 ^2 \5 v1 O
#define RCC_CR_HSION ((uint32_t)0x00000001)
. L. i+ C- K& H+ r/ Y
#define RCC_CR_HSIRDY ((uint32_t)0x00000002)* h# q! Z E$ o3 R$ t% H
+ i" B' W8 Z( W) ]# [% _7 X
#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)- Z* o" d1 r3 M. S/ d1 b
#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
; z5 w8 H& W% {% [
#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
# G$ g5 ~ e# B- }' {
#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 *// ]! V7 r5 x% K- j
#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
! H- m, c7 K- b4 j& L
#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
Q/ c9 G/ I* C; |4 E
$ w3 M/ _0 m' I2 k/ U9 L% E
#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
: g1 x& m+ N6 g' _2 s. j: T
#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
6 c+ h+ V+ S3 J* _
#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */" S3 N/ T" F+ H+ M" Y
#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
8 U* k, I. O: ~6 ]: `4 Q
#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
" c& U& ]& g! O) V9 u+ h2 l, \& }
#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */- n- W0 F* f; a: ~
#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
2 Z0 F" w* }) k0 y
#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
6 ?, A9 _3 ?# N+ t d+ F( A
#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
0 U" a" [6 o2 I1 ]/ S7 Y7 m- m$ G/ a; z
' f b: Q2 L" m" d
#define RCC_CR_HSEON ((uint32_t)0x00010000)
' y- y* ^0 x9 O2 S% M% |, K2 L# F' E
#define RCC_CR_HSERDY ((uint32_t)0x00020000)( Q$ K$ k+ g# ^6 i3 i
#define RCC_CR_HSEBYP ((uint32_t)0x00040000)8 q( Z% Q: n, H# f& Q( K
#define RCC_CR_CSSON ((uint32_t)0x00080000)
1 e$ \6 g8 v4 D$ W) b- w: T. O% z. x
#define RCC_CR_PLLON ((uint32_t)0x01000000)+ L* w" s4 a- d2 ~$ I) r1 t
#define RCC_CR_PLLRDY ((uint32_t)0x02000000)! G2 m* w5 M* V9 }$ s7 O4 e
#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
4 ~! F* U' ]; y- T
#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
0 o7 ?" ?& X+ V
#define RCC_CR_PLLSAION ((uint32_t)0x10000000). z& K! f; D/ h9 F
#define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)' V+ ^ V* y# C8 Z
1 q7 R2 h! m2 r
/******************** Bit definition for RCC_PLLCFGR register ***************/- q# D% r, H0 x+ }
#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
& c# a/ Y7 ]( {& v
#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)4 R8 x5 g( e' n1 R+ H8 H
#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)! s& Z# L2 P; C/ f6 h1 `! X0 }6 x
#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)) d4 [! B- f! }
#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
! t. r* B4 O+ m. ]2 G
#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)8 ?4 [1 m. ^ f3 R! o
#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
6 g; J1 t' \+ ?$ N6 Q3 g: i
, D7 S4 ?6 y+ Q0 Q. n
#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
* v' Q" m2 Z6 \# y+ h3 K- _1 Y! a
#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
$ z$ a& ?! q2 \9 R) D$ X
#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
/ v/ t M7 L. c- l9 s, ?
#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)" H4 I1 v0 D- F/ H, V
#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
0 R9 }* e& L( n" V8 e
#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
( Q$ h7 S" o$ I2 d+ c' A
#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800) S4 ^, Y+ G9 @, @' f+ N6 l6 Q
#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
3 J0 g1 n( l U: H. o3 p7 J# C0 ~
#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
9 z D6 B; o8 F3 f: X9 a) h0 c
#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
: F- r$ n% c/ r
# E' U# T, R! w$ f
#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)1 ^- G6 ?. u- T$ O( z
#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)8 ^: W$ j: l7 |( O# u- S: y- o
#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000) m& Z8 {- g2 @0 C
8 m. c* D) J& R/ X% \( A$ p' \
#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000): Z# s1 M: H. L' g8 L% C
#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)9 X# V" W* } Z* Q) I
#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)8 @/ z7 l: G: N5 p) ~2 v
7 H8 L+ X5 l) ]- d- g9 H# A9 ]& Q
#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
' L* _) c7 |# s
#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)+ D) a5 ?6 {2 U1 S! f
#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
5 Z0 F- ^8 W3 c4 h; z0 x
#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)6 x" R+ `: V6 N' T' A/ {: t
#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)) y5 o( |/ z1 s2 D
1 }9 z) f1 D% l8 L5 y4 d
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
9 H+ ~/ x+ D; W0 [; G0 T
#define RCC_PLLCFGR_PLLR ((uint32_t)0x70000000)& {; J0 x: A( Z- |# l* t
#define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x10000000)
: u# o& j: l9 e4 o6 x, a7 O: l9 U
#define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x20000000)9 r% H2 J. H m) u& Q
#define RCC_PLLCFGR_PLLR_2 ((uint32_t)0x40000000)) ^8 V: t0 g8 U0 m" S, O
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
7 I3 I6 b6 v3 d7 J* G
a# p J7 P1 O3 V( i
/******************** Bit definition for RCC_CFGR register ******************/* _4 ~9 o, R0 p" G; F3 k
/*!< SW configuration */7 R( u" K4 K3 @
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
5 T* T) W5 f6 k
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
& g/ s, |1 c% H0 U% l
#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */9 j$ z! G7 @6 e
# L9 H* r: d2 {# s. Z3 Q
#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */- I2 D& B3 ~ C: V6 S
#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */0 `! ~# P- c3 O; W$ s- F
#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL/PLLP selected as system clock */
/ e) \8 L2 W# g" o4 A$ @9 t
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)7 c4 s E6 y4 p8 Q3 C; o1 {
#define RCC_CFGR_SW_PLLR ((uint32_t)0x00000003) /*!< PLL/PLLR selected as system clock */2 s1 S; z" F/ K% C, h
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */# I$ _: r: Z) A* g1 q6 O) j, e
d- P8 }6 ^3 |. e+ q
/*!< SWS configuration */
3 T" ?, w% Q1 ]9 A* u/ J+ f( k. K
#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
" H" [0 K) R1 {, E% C6 E9 g
#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */5 _: y# t5 A8 Z* [! f/ l" Z
#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */- @ W+ M7 [$ f: ^" G) T8 K
( B9 y7 \5 G6 d: R. F
#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */+ b" _& L2 x/ g8 w
#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ o/ K9 }. ~& b3 C' d% @
#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL/PLLP used as system clock */
4 ]6 s+ v/ Q& Q R) d; _4 V
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F469_479xx) || defined(STM32F446xx)
5 f! n% o3 L) ^
#define RCC_CFGR_SWS_PLLR ((uint32_t)0x0000000C) /*!< PLL/PLLR used as system clock */
6 x! |% F7 s6 ]$ X6 s+ g- j, ?" |
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */% R; X$ D7 {) V# |3 h3 h
5 H% Y* ^" \! N [, z: q$ U
/*!< HPRE configuration */8 N; S( M' C9 g7 ]2 N" U8 n
#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
' ~7 G9 s/ C6 R! P
#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
$ | v7 A+ p# y; Z
#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
$ I; u) `, |5 B8 b( |9 A
#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
% A9 n; @& S! Q: L! S/ I
#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
% B- o3 o9 |2 R/ T, Y3 M
) Y0 @* D. `9 `" h2 X
#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
5 g% Y' b5 V( z# c, X5 Q0 o8 g
#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */5 ]# r. M _' T/ L. c( P# M/ I( m2 T
#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */8 f4 d8 i( t. r& F8 M9 l
#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
9 M+ d4 e! n7 Z+ y" O% S+ I" p
#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
7 r8 Q S. r l" w* k; G2 N z
#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
/ j$ l, p$ ?0 ?4 u4 U* A
#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ s- h5 V v! j
#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */0 c, K& y6 Z( X/ s- j, E0 R1 @
#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
# \; A# f' ]3 i. R
% k* u6 x$ d2 E# j
#if defined(STM32F410xx)
( ^# N9 o, h/ C$ d. c
/*!< MCO1EN configuration *// H7 g1 ^ ~7 M4 T4 M; {3 t4 T
#define RCC_CFGR_MCO1EN ((uint32_t)0x00000100) /*!< MCO1EN bit */
$ A% d& Q+ n% m3 ?6 u
/*!< MCO1EN configuration */' |, h1 ]# p+ p% R' s% S0 U3 G
#define RCC_CFGR_MCO2EN ((uint32_t)0x00000200) /*!< MCO2EN bit */
$ v; \5 I, _ e/ _7 Y5 i3 [1 s
#endif /* STM32F410xx */9 I$ r3 ~$ X$ h
/*!< PPRE1 configuration */
8 W- |3 h* e6 Z) h Q) X
#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */# r. _6 n9 o9 y
#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */" ~6 u. a/ H8 A
#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
* `0 l1 p1 s J7 t
#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
3 f1 r. l, @+ R5 d! ?# c) P
( b. I7 \# z; a1 H. T* D
#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */' r* W; V2 e- K
#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */' o+ U0 O4 K) } ~5 Q! y7 a# S
#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */9 Y5 y) t8 B5 w& \0 l) e6 f/ B
#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */4 f4 E! x* I5 i" G! ?: {
#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
4 x; A9 B3 c( a* ]$ U: Z5 a7 @
, Z- A# Z2 d! E
/*!< PPRE2 configuration */6 ~. a/ q5 U! r8 ]
#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
" z) A1 e( J G
#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */. W8 i- ]6 i* W1 j# V0 n6 Z
#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
8 o9 P4 D% N& D0 e. R7 I
#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
- c1 X' m: a4 u7 \( Y1 ^/ N7 Q
2 m: {+ e* {# j3 \) \5 D
#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
( ^# H3 H" p3 A1 ?0 a
#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */! I+ P* T# F3 b* g8 B% u( z1 o
#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */9 j$ ^/ k* e$ \5 P
#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
+ c) |) K, D, F$ t* W
#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */+ d# t0 p! a2 R4 N5 [
3 Z c) a8 Y. s3 c: z5 F$ T
/*!< RTCPRE configuration */
9 u) y6 J5 S- j
#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
3 J% s. W$ z E
#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000); L1 O% G: w& q7 N$ \$ b( I! g
#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)) \) h9 b. \/ o: o) ^0 E& e
#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)$ | d% d3 h8 B2 P4 |
#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
+ H: H _! F# ^ r
#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)5 v& H6 u0 d# p1 M% K9 o- C
/ ]! S' J4 S, g( ^( s
/*!< MCO1 configuration */ F0 Z4 _# v1 \! f8 [ N4 ?2 B
#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)( r, Z1 {$ v/ r1 t4 C7 J
#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)5 b5 o1 E& x: |+ D2 u n
#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)) p% D7 V# [) d) [
( S* p1 d( @' X; ?6 Y
#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
5 u8 w! y/ M( v- {
) ~( Q3 q. C. K# X6 K8 x* a: t
#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)& |/ P8 }. L( u. i; Y% x( q
#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
/ {& z# Q! {8 d q
#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)6 C& u. ^8 M9 i1 I5 {" m! J% }
#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000), M% [0 T6 L. G
5 e9 T+ u. c" Z7 v% n) u& J
#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000): Q' d# ~" k0 f* a* N# B
#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)5 c2 f2 ?0 u8 I1 R* E
#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
( i8 J( T( d8 ^9 l( {. _( |
#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000); z- w. z, Q4 n l5 E2 o( I4 w! P6 l% n
4 E; T0 A) A' r8 X8 |
#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)7 l; z" J7 d, _0 e! _4 Q
#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
( `. O* |" s5 K9 Z- Y: F7 ~) Z
#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
7 L+ {$ [2 y9 O1 p. y2 V
/ X1 T& `6 V. f- Q4 j
/******************** Bit definition for RCC_CIR register *******************/( R$ t/ Y2 J% m. \3 A" h' q7 j
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)/ U: A0 v( {! @2 d; |1 P v
#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)6 F' H+ t8 U( w" x
#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
- C# Q/ [, ^" ?. w
#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
" @6 U6 q6 ]* h8 U1 z8 B! t
#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
1 b3 S7 [" ?: t9 D% U* ]* h
#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
* E2 l+ Y! ^' B' r) }/ o. n! }
#define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)4 |5 }4 J1 U$ ^* p1 W% a
#define RCC_CIR_CSSF ((uint32_t)0x00000080)
, N, G' m# S. u# r# \
#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)$ u, J$ I; h& @( |
#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
A) i, A2 c, F1 `8 g9 h6 u
#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400): @7 n# g* z& E5 |
#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)" N: \) I- e9 }% @! g- B
#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)# ~# Z0 `; t) Q9 A( o5 Q" O. k
#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)$ Z: _1 L) U' Y/ ]) N0 z" A5 H& r
#define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)- t6 `, l8 f2 H$ K
#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)+ o% T9 Y4 V" R) s; z3 ^
#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
0 l8 Q# S* ?- e& R; l- r8 I
#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
; c1 P0 L( E- y
#define RCC_CIR_HSERDYC ((uint32_t)0x00080000), t0 S, n: |- \' k9 l% m# |! o3 C
#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000), }% H( D' Y2 \0 s
#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)8 x' w, W3 G; H1 u* q
#define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
8 z+ U: M X$ H) u! A7 j
#define RCC_CIR_CSSC ((uint32_t)0x00800000)" c3 P! W7 P7 j1 C9 ^
6 K+ C2 A7 P" p5 I L2 O
/******************** Bit definition for RCC_AHB1RSTR register **************/+ k! J+ j# S, Q7 ?. \$ S
#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)" [5 W# y- q2 z. g$ U
#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
; {4 R, W. ^7 }/ R1 u) _
#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
5 _6 ^ U- e; ~1 K' c2 \1 i& K5 p
#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
/ R: [! |, e5 c+ u( W, ~
#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
: W/ N* ^ `* y; U
#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
* K8 T8 s2 D; |2 [* ~
#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)# b" d0 i: N# |0 f
#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
" z# t3 x6 c1 u/ Q/ m" S0 t
#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
u) u/ D2 ~, {
#define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
& y0 V$ g* M- t" M8 t( k0 h; e
#define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)0 x% @7 Y( F2 E4 Q6 a' A
#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)6 v3 \2 ?, E5 Z, }; j( ]; J, M. `* X! P
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)$ h0 `* W+ S* N8 K1 V3 x
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
1 Z5 h6 L7 ^; N" C
#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
; d/ K$ u& x8 T- o9 V- G
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
) A' r: e# N1 m8 h3 H6 [8 C! {
#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)" [7 H: z7 F* x7 W3 t* j. K
, J" P4 N( v) N3 S% T% m
/******************** Bit definition for RCC_AHB2RSTR register **************/
: U8 B( t* @# l# L2 z
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
0 G E* d4 U' x5 E- E' D
#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
2 l2 L9 R/ c6 ~5 N' `
#define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)1 t ~1 m- w6 k8 @/ k
/* maintained for legacy purpose */' h) O3 i; U& J
#define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST) Z8 f3 j( h5 ^9 E! k. n [
#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
- n$ d' y& \% ~4 v+ u
#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
$ n3 U1 v7 P* f3 ?
/******************** Bit definition for RCC_AHB3RSTR register **************/
, `! w0 y* i9 F, x; d
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx); E2 A3 M. Y. O$ y
#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001). B4 q% A# R: A% m
#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
5 K8 O# }+ L8 `2 T9 v! h
+ ?9 S1 T) Y4 |( l7 Q; g
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)/ h2 B* J; E9 D# |( c+ B9 N8 Q6 \
#define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
. W9 s" }9 j0 g; P+ [
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
; s* U D2 v0 P) {. _3 S+ R
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)6 J4 i# @. E1 Y% e$ |6 g
#define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)
3 a5 l) v) p: c) L0 Q2 o9 c1 C& t
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */- U4 U9 L0 p- H$ ?/ H9 S6 ^: P; X
' i4 O1 X2 K' _4 s
/******************** Bit definition for RCC_APB1RSTR register **************/: P1 z$ V. u, O
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
# Z& O. ]; c' z$ s. L
#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
: R7 M% v9 f# N
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)0 E- f& |6 K5 L& t! \) M
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) A% m$ K( [4 w3 z
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
8 b% l8 u# W( I! I' r
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
$ X1 M3 M4 n9 w& m6 V
#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
# q/ K; K0 h8 b5 c) i8 Y7 Y
#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)6 k3 u8 f" a* |& A
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)- P$ o/ X F4 h* d! r/ k) J
#if defined(STM32F410xx) || defined(STM32F413_423xx)& `8 Q1 u/ u0 M: E$ z$ ^7 ]
#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x00000200)
' ~9 |2 j5 d/ A5 b' E. i7 @ d
#endif /* STM32F410xx || STM32F413_423xx */4 W n. u9 [$ x3 q, t
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
: k5 B; C3 Q) h$ N" a5 [
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)7 s" j2 ?+ Q! j
#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)9 i) G9 U* R7 `% a! @/ ?5 w
#if defined(STM32F446xx)& \; ]4 Y" O# C: i- M5 j
#define RCC_APB1RSTR_SPDIFRXRST ((uint32_t)0x00010000)
2 G& s2 T2 K' c
#endif /* STM32F446xx */
3 d* L6 w3 C$ \* {
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
9 N# G( _6 e( m) p$ \, Y
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)* W, G! B$ y( z( W& `4 j
#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
6 n1 E; f3 _( P9 q# S p
#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
) `6 o( \+ D3 S+ `+ L) [1 a
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000). u) Q1 g" e1 t$ P, G, q$ g
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
5 X* b. A# n& H; ^# _
#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)0 M: J% m! c6 \+ K
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
/ n/ z2 ] z6 |3 Z/ x
#define RCC_APB1RSTR_FMPI2C1RST ((uint32_t)0x01000000)% o8 K+ F+ t- F5 Q/ `" B1 J
#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
, |3 L& D+ L; i6 }
#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
: S% e" M }2 p, R/ ]! d7 N8 ^
#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)( s1 v* K0 h. S2 ~2 Z2 s
#if defined(STM32F446xx)
; i) t1 |9 g1 H/ r+ k0 ?
#define RCC_APB1RSTR_CECRST ((uint32_t)0x08000000)
5 `1 S% v+ r D
#endif /* STM32F446xx */
# r! N/ S$ f+ b- _$ B( J
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
; N% ?0 T- D3 D2 K& ?# U
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
. i3 O( G2 z$ F- P9 B, }
#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
" O. j3 [" o" n( Z! B
#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000): O) y$ W$ o* Y/ V8 s
7 ^( C6 v8 r k3 e
/******************** Bit definition for RCC_APB2RSTR register **************/
8 c9 U5 C, `# K, ~% m N
#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)2 d, A! i9 j* w# @8 Q5 r% l
#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)4 @- J' ~6 S) L5 r3 b- J$ J
#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
0 J5 i( N: o/ p' F! ^& B6 A
#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
C# r2 F" ]1 _9 y! @9 L# _% W
#define RCC_APB2RSTR_UART9RST ((uint32_t)0x00000040); T9 P% E8 r* u# H
#define RCC_APB2RSTR_UART10RST ((uint32_t)0x00000080)0 s& D, g8 N; Y" I$ P( x0 w
#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
8 y- k. x8 u1 B: Q6 \
#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800). R/ ]$ x; C* s T; |. Z
#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
" {9 Y c& i! e' K- ~
#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)7 ]* D6 R% W+ P' Z+ U g% e( N
#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
+ U2 l( a9 E: e+ e6 u
#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
3 [, O/ `( M2 w4 h. c9 W/ ?
#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
8 L5 g: b8 G1 u5 z" F/ [
#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
# U0 Q9 x# _$ }# a
#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)5 U7 q( }' k* [4 t5 {/ j
#define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
7 u( x1 g" s4 P, E
#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)$ ~+ j5 W/ W8 ^$ \' z. v: p+ R- v$ ^$ l
#if defined(STM32F446xx)$ H* g r0 t8 j( p) h& ]
#define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00800000) |4 q, H. A N( a/ r4 }% R3 b
#endif /* STM32F446xx */0 W, o0 w' G+ h1 t" `
#define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
- A* O! B' y% \" U z" W% ~- B# _9 W
#if defined(STM32F469_479xx)
+ y" X% u8 v0 T- F1 ^
#define RCC_APB2RSTR_DSIRST ((uint32_t)0x08000000), |) |# v( C2 I% A2 X% d* t
#endif /* STM32F469_479xx */
) @5 C$ V' Z1 d% z h8 y
#if defined(STM32F412xG) || defined(STM32F413_423xx)
6 V) U/ O8 B8 H2 s$ p
#define RCC_APB2RSTR_DFSDM1RST ((uint32_t)0x01000000)
2 Q: b, d5 z; v2 k. I0 q9 n
#endif /* STM32F412xG || STM32F413_423xx */. R; h' V; g0 Y' |1 F7 G0 M
6 t" {! }& [0 s; u6 r( |
#if defined(STM32F413_423xx)4 I3 F. W: [& w% I# B7 C
#define RCC_APB2RSTR_DFSDM2RST ((uint32_t)0x02000000)& k% e% m9 ` I: f" r l8 B9 P% |9 J
#endif /* STM32F413_423xx */9 I3 e# `3 M8 K% l( z' R ^2 S
/* Old definitions, maintained for legacy purpose */2 ]0 z- Q9 N, [( C0 N) d
#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
# {/ m* e0 z( V
#define RCC_APB2RSTR_DFSDMRST RCC_APB2RSTR_DFSDM1RST
6 {$ a4 j8 ]; p4 t
: j/ b3 \6 [ O5 k
/******************** Bit definition for RCC_AHB1ENR register ***************/
! g$ ?0 w3 F* K! \+ D2 }" D
#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
8 E. r A S7 I1 a1 C( a% A/ m
#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
4 p6 a$ J0 p3 F% n) f
#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
0 Y# W( b+ I, _* T( ^
#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008); b1 U) X0 O/ v9 h
#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
$ J5 a `. B5 I) M
#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)1 T- {' j ]" z/ v1 [+ E* {
#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
6 j- U. V# E: \2 J( ]6 a
#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080): b' g g; [2 o$ w8 V
#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
5 A) k: n( f' o# Y$ U: s
#define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
' Z O% p% b+ y4 S n: Y
#define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
. K R- t; e- D, Z# p% G
#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)' d' H. q3 u6 ^/ D( f6 R! I- K
#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)9 O7 H9 p, [' q6 v1 c
#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
K; V" q Z# b2 `9 g
#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
( G: D8 N( M/ M+ {/ c
#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)/ e9 l# {% M& S& o# \3 Q
#define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)! r6 x. p. a K/ J% D% ?) \! b5 M
#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
7 M$ l2 c8 n, M" N5 ]' I
#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
3 d* a1 q+ u: }2 [
#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
9 T& @/ o' T2 R9 k% d6 u/ p
#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
4 j6 G0 J i) a
#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
6 t- k2 ] }) P7 O, \1 y {
#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
" Y/ s8 e' M) d2 G3 Y0 B$ B
n# _6 ~/ N7 n) W% j
/******************** Bit definition for RCC_AHB2ENR register ***************/
2 \) `8 [. A) z _' e& m" R1 P
#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
6 B+ _' n) M/ ]; S- |
#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
7 m; m1 j( K7 j% P1 U2 a- W
#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
1 m8 R& Y3 [7 ?$ L& u2 i6 L
#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040). S* C" Y! c6 H. M2 p; ~ V/ S
#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
/ S; l, x' R% B7 `. N1 \
1 k" O+ s3 b8 u2 V# O- `
/******************** Bit definition for RCC_AHB3ENR register ***************/3 V' H9 f& {* c1 R8 I* i- O1 G
; K0 Y+ d/ f# h
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
- f" y4 C: W" s' s2 k
#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)1 i5 m7 J4 J" S, R
#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
+ R) r1 d1 W! [0 E- @
0 h9 r: P% h3 u4 ~& `& ?
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)2 g# x5 O4 W: N$ ]7 B, [2 d0 E
#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
: W. m( m2 y3 |! H: Z
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
6 Z+ e/ q r+ G* a, K0 q1 F! l
% m- y3 ^+ q- |0 H
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
6 @" w( w( y" o$ E- I0 y
#define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)
1 H2 f# l( i5 n3 ~2 K
#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
! V# O& |- m' U' y) W+ X
6 x% Z) B1 I7 o- H, e
/******************** Bit definition for RCC_APB1ENR register ***************/3 R$ A6 s( R |( R$ R+ Z$ N3 k/ e
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
1 M. ^8 {# q8 \5 l+ K
#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)7 a6 C1 G: w- o6 l' h
#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004); E }& u X2 B" N& B; @* ]7 z
#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
|0 s1 R- S/ p9 d7 ]
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) T7 }! O3 V& d% H/ B
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)2 q( E9 L; }' u* ]3 ~) N$ s
#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)( ^7 l/ r) R7 M2 n
#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080): e; V3 L. u8 k! @% h9 t$ X; Q8 C
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)5 s7 Y* x6 R+ f4 q
#if defined(STM32F410xx) || defined(STM32F413_423xx)
" v7 Y' P1 o& W) U% l
#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x00000200)
, h. P; ]4 N' D' X6 s* ~
#endif /* STM32F410xx || STM32F413_423xx */. L" o1 R/ s: X( ?' e/ b
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
" E0 }! |0 c! r5 O1 ]- ?, Z
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
, a7 a1 [+ `5 b
#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)- W) T: n1 p$ k+ a
#if defined(STM32F446xx)
4 v" A$ M2 N3 R: G
#define RCC_APB1ENR_SPDIFRXEN ((uint32_t)0x00010000)6 I, O6 E2 I$ N( l- J( L
#endif /* STM32F446xx */4 X" A( H) ]3 ~4 ~5 w1 W, [3 w& C: w
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
* I& a/ \, S0 A' S
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
! m) ~4 i/ d+ U. _- b
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) P! g! z2 B( t) A$ p- S& D3 d
#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)& s9 q& U# X [
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)! n. c: @& p: z
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
@, x% Z- g. x( d
#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)7 X v# F; _; R( t4 f* p
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
6 t/ M+ Q5 ~0 I+ G
#define RCC_APB1ENR_FMPI2C1EN ((uint32_t)0x01000000)0 k9 u$ q& c1 `) B) l5 @9 ?* A( p
#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
" ^& B/ f9 |$ i) m& D% Z7 r* ?/ |! o
#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
3 m) z/ V& z- e, A7 e' t
#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)- W7 f; u) I4 d5 R! D3 h' j
#if defined(STM32F446xx)
. Q" L) _, X: e' D9 ]) O% g
#define RCC_APB1ENR_CECEN ((uint32_t)0x08000000)
4 g' }! A: S& I) i8 X
#endif /* STM32F446xx */% I( ?6 S8 \! D
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)$ J. z4 t5 G6 g: |7 H
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
4 Y% C) D7 ]# F
#define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000): J! s, n3 y; D" E, |8 G' p
#define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
/ T9 g8 i4 h. Z' p. ]. `" ^/ ], j
& z$ B( s* f: F
/******************** Bit definition for RCC_APB2ENR register ***************/7 z' R2 L$ B9 a4 S. ^: o8 C4 l
#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)# o0 |9 [5 R, O: D- H, q
#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
6 b* x O. Y/ s, U; U
#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
( X. _! z, ~' I, g1 l5 F+ q
#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)( m6 k/ k* y/ G# \) Y$ u
#define RCC_APB2ENR_UART9EN ((uint32_t)0x00000040)
/ H9 e, I1 R- j- ]/ u& f
#define RCC_APB2ENR_UART10EN ((uint32_t)0x00000080)% z) W! F' q+ w( g1 }# T+ u( G6 C$ Y( M
#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)# W6 \& z* o1 R9 |
#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)" J9 d1 {; S$ j
#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
& [" g; k- {, x! `, W" W
#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)- D% L/ @! }) }! v$ ^# X9 _
#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000): l* Q. o' f. O
#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
1 J0 v- ]0 R. R) U; Q
#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
5 F+ g. _& K! l& D: `* z
#define RCC_APB2ENR_EXTIEN ((uint32_t)0x00008000)
# Z, g+ v! {2 F
#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
! b7 t# P0 d: k3 g, o& U7 Y
#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
( r2 [8 u* k; j8 J: [
#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
; ^" ~, z+ y6 P% h/ Q0 X) Y1 M
#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
- ?' R) R2 g7 m, ?
#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)' R" ]3 v: F* h8 Y
#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)6 c! D4 A0 [( W' |
#if defined(STM32F446xx)' _9 G- |2 T! f3 c$ E1 n" u
#define RCC_APB2ENR_SAI2EN ((uint32_t)0x00800000)
7 V0 { s4 n6 z" v' O; ]3 K
#endif /* STM32F446xx */. H0 B6 B0 P0 i$ u+ N# X
#define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)
! n# A! L; Z# B* ?: I" ?, i4 j9 c
#if defined(STM32F469_479xx)
( ]3 i( m) O3 n0 r
#define RCC_APB2ENR_DSIEN ((uint32_t)0x08000000)
+ Q- U; e1 w/ R; i, B% M
#endif /* STM32F469_479xx */2 q: P- H0 j# {1 Z7 A' h4 D( Z
#if defined(STM32F412xG) || defined(STM32F413_423xx)
& G) {$ W( q2 M) b: B4 i$ i
#define RCC_APB2ENR_DFSDM1EN ((uint32_t)0x01000000)
+ p. x1 }# [. p) N; {+ @6 B' G5 V
#endif /* STM32F412xG || STM32F413_423xx */
0 N5 W3 r. q% p7 @
#if defined(STM32F413_423xx)
1 L( ~# X1 y" \
#define RCC_APB2ENR_DFSDM2EN ((uint32_t)0x02000000) K' O) m- P n
#endif /* STM32F413_423xx */
: V2 L( o8 ~3 V+ r% I0 a; @
/******************** Bit definition for RCC_AHB1LPENR register *************/
, E5 W. q3 V' m9 i" {! j a% t D
#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
- {* c* j8 A' A: o7 G& J
#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002); ~; A4 k( e5 ?# G A/ S. I
#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)) O$ ]4 e0 a$ C# Q! R7 i% c
#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)# P6 v) Y: p- e7 \( f1 {" C2 N) Y9 G
#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)' y/ v, s7 e, ?
#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)8 z# A. x9 G) T- S8 H
#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040). g ^. @0 K9 O2 a9 b _
#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
; l# o4 M5 ~8 i$ j) S# ~* i. e
#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)" v8 I) b3 u3 m& |. r6 g* F
#define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
4 Q" F( Z/ c: D. p/ F
#define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)/ X5 s& B" K1 u2 T( F
#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)' \7 e; b1 J f7 w) ~
#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)6 d* D% G2 Z9 |$ w
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)% `0 k& U+ K1 p$ ^
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
6 n; c; O$ Q! `, D
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)8 \! S* _- u$ B* ] B: A" m: a8 Z
#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
) }3 V5 I5 }1 `5 K1 o6 J1 r
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
1 d) T* R. n# Z
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
* F( G/ s) i3 Y. I) n$ I; J
#define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)! A+ o1 i+ Y! x6 u( }6 |; s
#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
7 D1 Z) X; a% v p) y
#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
4 K$ W6 e/ c% T5 U6 A; ]
#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)1 W6 y! K% Z: y- [
#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)* D( V+ j0 t8 s0 a! z
#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000). {: H; \$ L& [
#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
# z9 v+ R7 [2 d" k6 k# d
# W# ~1 h: Y% f. A! h
/******************** Bit definition for RCC_AHB2LPENR register *************/% l* k# x0 H1 q9 o9 ^
#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001). l' j. n# I0 O$ `5 X1 P4 B
#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
. S4 t6 B( b$ K, N0 W
#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
9 c4 k& b5 I, v+ `# Y: h( Q
#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
( K3 t4 m0 l, e7 U. K
#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
I; v& C0 w' [9 S
4 w' i! p0 M* @! j6 f
/******************** Bit definition for RCC_AHB3LPENR register *************/) K- f0 P1 a& _2 R. q
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)2 d3 k9 f |4 Q0 f# S* p O
#define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
1 @6 t7 z' d0 P N3 w6 A
#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
; _( F% V5 A+ |$ p
5 h2 t- `0 g; [' L
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx): [9 N. |% }0 g# l s. k) z
#define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)9 r# w' H" R) m3 o
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */3 s+ P- o8 K! ~& T3 F0 C, K& o% u
#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)$ H* m# Q! P4 M, P: g+ X* {
#define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002)
g0 W) u4 I o5 Y% c5 Z4 [
#endif /* STM32F412xG || STM32F413_423xx || STM32F469_479xx || STM32F446xx */
t/ w) l6 L9 c) f
1 I5 S) T0 W* }% G" @ T0 {
/******************** Bit definition for RCC_APB1LPENR register *************/' G/ ^: j! M: |' s# y! K& W
#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)$ I1 e/ `/ |" p: j! u" h9 V
#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)" n) I" ]4 V9 E4 a
#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)- L1 M' h! t" f6 C; N+ S" r
#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
4 z) x7 t- B. F! y! C) V' }( b
#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)+ B& |! P8 s5 K2 E+ g% k2 Y5 @7 I
#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
: _5 G1 p% R. O2 d
#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)8 D, K4 C, s: S
#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
* `! g! G: V0 p! i# v; K. |
#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100), @. m- W; u3 ~' t. P$ \
#if defined(STM32F410xx) || defined(STM32F413_423xx)% ~) f$ P' Y5 t5 I5 w/ q
#define RCC_APB1LPENR_LPTIM1LPEN ((uint32_t)0x00000200)8 u, D6 `, n v! B8 X7 T
#endif /* STM32F410xx || STM32F413_423xx */
4 G( Z& s# w+ \! Y" P6 r9 Y
#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)0 I8 ~' o( f* M! S
#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
8 p, F) Z+ u) S8 _; ~0 h
#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
+ y( H# m: h! i" ^& W7 W
#if defined(STM32F446xx)
5 m: i' e) h$ a
#define RCC_APB1LPENR_SPDIFRXLPEN ((uint32_t)0x00010000)+ U9 k/ Y+ F+ D! e, a: ]* L. i
#endif /* STM32F446xx */ J; ^' ` K: F5 L: z" x7 R
#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)4 {5 {' c/ n+ |# Y( h6 g
#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)! j1 s# p2 W6 l" h9 E
#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)2 e1 r6 F) X) C0 b
#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)5 W1 Y: ?/ K; P3 @0 o$ _ x9 t
#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)% Q# A6 X8 T3 _
#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
! e. ^ `: m% C4 j3 n' _; I& u
#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
& c' ]0 s& C+ ^2 [2 Q' b) F
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
) I- e" m1 c2 q5 Z5 i
#define RCC_APB1LPENR_FMPI2C1LPEN ((uint32_t)0x01000000)
' `# y! _7 o& y
#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx *// r# `, a/ U8 i) V, Y
#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)& F1 {. N% ~" k; J7 O3 j
#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)" B9 m8 {( x3 A+ }( L' {5 d
#if defined(STM32F446xx)5 d7 ?. S1 ^3 K# ^% M
#define RCC_APB1LPENR_CECLPEN ((uint32_t)0x08000000)
6 T; |+ P+ x! q5 u* M2 r
#endif /* STM32F446xx */$ j- W& ?% k' C
#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000). S$ V! c7 O. g& ^, O- y
#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
: @' h; u* ]0 H5 M8 a( G
#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000): H5 D/ A! M0 a8 Q
#define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000) b( q2 y4 ^6 o' X, g8 V
/ Z! d2 ?2 f2 a0 }; g
/******************** Bit definition for RCC_APB2LPENR register *************/
- l; q5 }1 B- c% j3 r L5 f7 S. F
#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
! R7 Z! N( {7 @4 G' |. ?
#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
7 }8 v# n$ q6 l. G+ V
#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)2 X/ I2 V2 Y$ a X
#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)) I( p( m; n. y/ Z6 H
#define RCC_APB2LPENR_UART9LPEN ((uint32_t)0x00000040)' u# V7 I1 T& G/ M. m: r
#define RCC_APB2LPENR_UART10LPEN ((uint32_t)0x00000080), ~8 j, b; G/ C+ y# E5 _. s
#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
9 ?2 @( G& ]- v
#define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)( a7 t' p$ f: g B6 l6 x
#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
4 c. v0 G8 b$ l( {# @! o0 q. ~
#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)9 W2 C7 c0 o- o/ z% z+ j! Q8 {
#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
# ]! D( X: @& p% |# `, z
#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)9 @$ h1 ?9 c3 H t" J1 e2 ?
#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000): `1 Z7 C' K( w2 b8 O' ^% j
#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)& N. [" o8 F5 a- Q8 ^6 X* o0 F
#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
3 f# z6 A) ?# q, r, j6 _2 c
#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
) F& x8 U$ R. x
#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
# ~) u8 W% R6 ?' a
#define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
; `5 Y8 s' F+ V$ R
#define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)/ H: e# ? d4 M' P% }% `
#if defined(STM32F446xx)# u2 F: h0 P: n t% E
#define RCC_APB2LPENR_SAI2LPEN ((uint32_t)0x00800000)3 n. v0 f6 Q7 K- R6 X, ^4 h% ^6 b
#endif /* STM32F446xx */
: g0 j9 y1 v0 A" q0 `
#define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)
. v/ j9 N1 j3 W9 s/ n
#if defined(STM32F469_479xx)* u# r, u: Y- \+ I" Z0 x
#define RCC_APB2LPENR_DSILPEN ((uint32_t)0x08000000)/ w/ {4 Q* }6 J. v5 \8 q. e m
#endif /* STM32F469_479xx */
+ ^) }9 z4 c1 \% u, e9 [
#if defined(STM32F412xG) || defined(STM32F413_423xx)# o& t' o8 |* j+ x* G% @9 Q9 D9 A
#define RCC_APB2LPENR_DFSDM1LPEN ((uint32_t)0x01000000)- K3 c7 v5 O& T8 h. Q6 u; `
#endif /* STM32F412xG || STM32F413_423xx */
0 j9 |( c" o( k" r( F2 r n
#if defined(STM32F413_423xx)
+ F% e' h( ~( R) i( Z
#define RCC_APB2LPENR_DFSDM2LPEN ((uint32_t)0x02000000)
' i' R) N `* w6 O
#endif /* STM32F413_423xx */
G5 c# f h9 w$ A9 G) ^$ A2 I
& B! X3 d& {2 B/ s
/******************** Bit definition for RCC_BDCR register ******************/
5 T# a6 P, ]/ X! y( X( N9 Q
#define RCC_BDCR_LSEON ((uint32_t)0x00000001)0 y) T* |$ X* A8 m9 q! j
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
( A% e9 i% N; y
#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)- w# W+ s' B9 M( F5 Y, e; g
#define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
H0 w( O/ r" s6 w; K
$ m' q* k, G& `; Y) t
#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
. q- I. h; M6 L" g% h/ T
#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
4 S* b, @6 f0 a# P7 I* ^
#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)9 h5 k5 o2 w$ H" {
4 F& [8 G# W5 s$ z3 D1 N4 w
#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)" G1 n& ~. f4 z7 s* l
#define RCC_BDCR_BDRST ((uint32_t)0x00010000)( W, \5 s l( U4 K8 i
4 a1 o6 q7 I& H( Q6 F5 C$ _
/******************** Bit definition for RCC_CSR register *******************/2 o$ D v$ J# o' B) s( }
#define RCC_CSR_LSION ((uint32_t)0x00000001), f7 M4 k2 |# `& N8 x) R! Z
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)* X8 B1 V: L. b, `
#define RCC_CSR_RMVF ((uint32_t)0x01000000)6 }9 J, M5 |! T3 x% D" n, Q) l
#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
' E9 O1 M* n. F7 w- H% C6 i+ r
#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)) a) L+ [" V8 Y0 s L$ C
#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
- ^+ W6 {* {. _: W8 l: V6 S
#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
r8 k2 W, i N3 {- i) X
#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
" V- F- d) e* F! E
#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000). C- I/ L, z% b' ~# A" h
#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
, d/ B% B3 z5 N7 ` t8 J& C
8 j4 ]( X6 z$ J2 n- R4 y6 R- W; u
/******************** Bit definition for RCC_SSCGR register *****************/* @, o0 O+ Q& y+ x' |
#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
5 @6 L k* M/ Z) Z& q9 i! p( ^4 B
#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
1 _9 o* ?4 n) ]: @& t
#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)# b3 @1 r$ c/ C
#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
. [ m' q: [+ L
" j/ J8 K- P8 V
/******************** Bit definition for RCC_PLLI2SCFGR register ************/
* M- s# l2 |7 Y8 O' N+ Q
#define RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F), N* o- n8 f5 U" r
#define RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001)
% z! a' S1 K) A- z& u
#define RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002)
' E6 G+ q, ^% m) Y$ Y3 w
#define RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004) ~) v. D4 ~: h( b: I0 P3 t' U2 K
#define RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008)3 L( R: Q3 o$ m$ b4 \3 k" c
#define RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010)- S% {% J8 {1 J3 J0 K+ U& E
#define RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020)
0 `" @* S1 h6 X8 a+ [
* v+ k i5 m1 M" s, L
#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)2 S1 L T9 d8 N7 i4 i* _. o! M
#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
" G) a' Y# Q9 `) i A3 r
#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)* j: j& p& l& }$ U3 @) Q4 H
#define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)' V: c b+ D4 w& M, y
#define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)- B+ Y0 ~2 v, N7 ]) w
#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
" I0 t3 X4 @) b# K- E
#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)# e0 ~& _3 M5 t3 t2 M' r, a
#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)3 X9 w5 [' h( t% x. F
#define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)8 O# v4 B$ u/ E |. t* v
#define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)2 w0 t# v8 \ R0 `5 O+ m
% \. ^ I {- K9 o4 x8 S5 j& E
#if defined(STM32F412xG) || defined(STM32F413_423xx)
! v; x+ n1 ~$ ^% H _+ P+ v
#define RCC_PLLI2SCFGR_PLLI2SSRC ((uint32_t)0x00400000)
" i; N' k' `6 e |' i/ ^
#endif /* STM32F412xG || STM32F413_423xx */
5 P' m% w' u7 C- S5 Q3 F' E, W
( i+ t, z9 O6 c
#if defined(STM32F446xx)$ O9 Z. j; r" e7 Q3 g
#define RCC_PLLI2SCFGR_PLLI2SP ((uint32_t)0x00030000)
/ N$ ?3 A( J" J% v; Q7 n
#define RCC_PLLI2SCFGR_PLLI2SP_0 ((uint32_t)0x00010000). l! @8 a: }1 @( R% \
#define RCC_PLLI2SCFGR_PLLI2SP_1 ((uint32_t)0x00020000)2 T/ T% T5 D0 x" I8 [# B% i7 r2 W
#endif /* STM32F446xx */9 q- ^; y5 U$ C7 b$ e. J
0 `3 Q9 b/ A+ a
#define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
" L7 t& d6 @+ E5 D
#define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
" a2 x4 u" G5 ?" @% s
#define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)6 p( @9 f0 g1 L$ c+ y
#define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
4 Y" O* I4 D2 {0 f
#define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
1 x; M' L U1 h# d
7 V; j: i( \6 b. r1 M
#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
2 S3 V& n3 |$ i; o0 U4 s
#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
' C( T* S9 m( A: y7 e
#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)5 ~9 y0 ~# z4 n9 F+ G
#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)% {( q: ]. x3 m. J: w. Y
. P0 D1 u: I; {5 u( }8 f
/******************** Bit definition for RCC_PLLSAICFGR register ************/. [* r( ?) ~- W' i7 u2 i
#if defined(STM32F446xx)
8 w: d6 b8 ]4 n9 s) j+ ~7 K; K) O6 z8 a
#define RCC_PLLSAICFGR_PLLSAIM ((uint32_t)0x0000003F)3 J' s' N2 G5 x, N2 I
#define RCC_PLLSAICFGR_PLLSAIM_0 ((uint32_t)0x00000001)
6 Y- H4 f/ k2 `7 K7 p0 F- L
#define RCC_PLLSAICFGR_PLLSAIM_1 ((uint32_t)0x00000002)0 O3 h: p5 Z( q1 W2 z# i
#define RCC_PLLSAICFGR_PLLSAIM_2 ((uint32_t)0x00000004)" ?5 F g3 m0 T" [0 b- u" {
#define RCC_PLLSAICFGR_PLLSAIM_3 ((uint32_t)0x00000008)' v% H0 o ?- G1 ]2 |0 b* {5 r
#define RCC_PLLSAICFGR_PLLSAIM_4 ((uint32_t)0x00000010)
, {3 b4 }* R; n* Z) h6 j _- e
#define RCC_PLLSAICFGR_PLLSAIM_5 ((uint32_t)0x00000020)
: O$ }+ b- Y9 J- u1 Q9 t, r
#endif /* STM32F446xx */
5 }% d2 O2 c7 {5 t
) c9 l1 m; t0 ^9 C6 o. H
#define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
8 x9 N" N4 X) C6 g# a4 N
#define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
3 w+ ?# v- ~5 M! y% V" I& {
#define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)( n$ L- o* l# f8 t
#define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)2 i( W+ H$ V7 y. n9 p
#define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)- U; Q9 t$ R( P0 B% [( U7 Q$ e9 i
#define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
6 M0 K \3 g$ K6 d7 [) t
#define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)' e6 g9 U( p4 M1 k. S( [
#define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
. ?8 q5 ^5 ~. V( s, {7 [8 L
#define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
4 n! c7 \' v1 F/ q! }- O W
#define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)/ v, C9 P9 m K
9 g4 K. L4 F( W, J9 P
#if defined(STM32F446xx) || defined(STM32F469_479xx) 1 p5 E' ]' X; v1 S
#define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)# L7 B% Q% C# q
#define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)/ S3 k% R8 Z( ]) e- E) h9 |4 ?
#define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)
8 Y0 Y8 \" \ J# V
#endif /* STM32F446xx || STM32F469_479xx */- Q; \5 }, N& d
% _7 L" ?( F" o# j: q
#define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)5 [) S" P: \7 s( [7 t
#define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)% f' y( L3 { ^/ v; W
#define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)9 W! ?7 w1 f' s* G
#define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000). `3 v# i4 E% W% i0 H
#define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)4 o7 m3 U. X4 a- ?! e( c% z
7 S: T8 t* f( M8 i. J/ h2 |
#define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)4 G4 O7 V8 c) `2 F
#define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)) _, h$ \/ I, h( c8 N1 {. Z
#define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)" E3 g& q; O% W* e
#define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000) H% H; s4 P: V0 u" l! }
X. K, s# m, \* U) x/ H! f
/******************** Bit definition for RCC_DCKCFGR register ***************/+ v4 W* \% v+ U+ f9 a- a0 N( R
#define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)
x! {6 K* u! ]) t: h0 {
#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
) D3 X. }$ b/ o/ k
#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)" V! p+ Q, d8 j: U# ~2 P3 V
9 F3 H3 B) O# U, B4 Z+ X/ m
#if defined(STM32F412xG) || defined(STM32F413_423xx)$ W; j: X9 m8 o+ V- `9 q2 p+ G
#define RCC_DCKCFGR_CKDFSDM1SEL ((uint32_t)0x80000000)
8 Q. M3 s! |6 I
#define RCC_DCKCFGR_CKDFSDM1ASEL ((uint32_t)0x00008000): B1 [; [: P* {
#endif /* STM32F412xG || STM32F413_423xx */# M1 F( f* [( h- r' ?6 z' ~5 X( O
4 T$ c! h3 S. n O/ }) ]
#if defined(STM32F413_423xx)
6 ^: s3 w6 ~; ~" W( }
#define RCC_DCKCFGR_PLLI2SDIVR ((uint32_t)0x0000001F)
: @; A' v: b4 }1 m9 O* g& Z
#define RCC_DCKCFGR_PLLI2SDIVR_0 ((uint32_t)0x00000001)* [( ] U) d' a
#define RCC_DCKCFGR_PLLI2SDIVR_1 ((uint32_t)0x00000002)
* ` M, {7 Q2 j; [
#define RCC_DCKCFGR_PLLI2SDIVR_2 ((uint32_t)0x00000004)/ D" ?/ D: V; k6 d$ N+ N3 o0 t
#define RCC_DCKCFGR_PLLI2SDIVR_3 ((uint32_t)0x00000008)- ]' I! T4 i$ @ l
#define RCC_DCKCFGR_PLLI2SDIVR_4 ((uint32_t)0x00000010). q. _( h5 R8 a
- b- ]% T# I+ n+ c8 |2 k% @+ E
#define RCC_DCKCFGR_PLLDIVR ((uint32_t)0x00001F00)3 \# N8 v" g$ t. j s" x
#define RCC_DCKCFGR_PLLDIVR_0 ((uint32_t)0x00000100)
! _, p6 q* g$ Q% D, H0 _+ f
#define RCC_DCKCFGR_PLLDIVR_1 ((uint32_t)0x00000200)- R* K( H# [. c- I6 B# i( z# ?7 s
#define RCC_DCKCFGR_PLLDIVR_2 ((uint32_t)0x00000400)3 D4 g. i$ J q! M; ^; J* F2 O
#define RCC_DCKCFGR_PLLDIVR_3 ((uint32_t)0x00000800)
9 z% C# H; d; G% f7 Y% ?
#define RCC_DCKCFGR_PLLDIVR_4 ((uint32_t)0x00001000)
" c; _: E: S, {, U! r
#define RCC_DCKCFGR_CKDFSDM2ASEL ((uint32_t)0x00004000)* z: y. Z1 K1 d! H1 W
#endif /* STM32F413_423xx */
$ n( r0 b2 N( m* S& I i
. Y- P8 W' c/ `! v% K; d+ l! u0 l
#define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)0 ~& x( _0 l5 g7 D: W* d
#define RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000)5 p# m5 |3 |! R' ^. s
#define RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000)- e u" B3 [0 j. C& |2 c
#if defined(STM32F446xx)" q1 w% O5 Q& x% [0 \
#define RCC_DCKCFGR_SAI1SRC ((uint32_t)0x00300000)1 n. l D5 `' l6 D
#define RCC_DCKCFGR_SAI1SRC_0 ((uint32_t)0x00100000)
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#define RCC_DCKCFGR_SAI1SRC_1 ((uint32_t)0x00200000)+ R4 V& t: W$ _# K+ @. ?
#endif /* STM32F446xx */; ?+ C* D5 ^' W# S7 u* |: J
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#define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)9 h- ^) x, b9 E+ ^3 q9 a4 l% L
#define RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000)/ b6 r5 u$ q) s
#define RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000)! b3 A* i5 J4 Q6 X! r- i: f! ^6 @. U
#if defined(STM32F446xx)% k6 m( A! M: S! R$ Y4 q
#define RCC_DCKCFGR_SAI2SRC ((uint32_t)0x00C00000)
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#define RCC_DCKCFGR_SAI2SRC_0 ((uint32_t)0x00400000)
/ \$ ?5 i0 Q0 I3 T: u5 c' a. S
#define RCC_DCKCFGR_SAI2SRC_1 ((uint32_t)0x00800000)
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#endif /* STM32F446xx */- R$ R0 u$ I, S* |' O1 Q, e
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#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)/ {7 E0 I% R% k( {
#if defined(STM32F469_479xx)
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#define RCC_DCKCFGR_CK48MSEL ((uint32_t)0x08000000)
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#define RCC_DCKCFGR_SDIOSEL ((uint32_t)0x10000000); r' A3 j3 ]+ [) \# T0 A
#define RCC_DCKCFGR_DSISEL ((uint32_t)0x20000000)
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#endif /* STM32F469_479xx */
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#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
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#define RCC_DCKCFGR_I2S1SRC ((uint32_t)0x06000000)
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#define RCC_DCKCFGR_I2S1SRC_0 ((uint32_t)0x02000000)
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#define RCC_DCKCFGR_I2S1SRC_1 ((uint32_t)0x04000000)) ]! J3 E1 w N# U8 U, _
#define RCC_DCKCFGR_I2S2SRC ((uint32_t)0x18000000)
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#define RCC_DCKCFGR_I2S2SRC_0 ((uint32_t)0x08000000)) Q2 J9 A! e( V. F, c3 ]
#define RCC_DCKCFGR_I2S2SRC_1 ((uint32_t)0x10000000)
# \) l- p, V8 _# h% b) j8 `
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/******************** Bit definition for RCC_CKGATENR register ***************/6 W. P/ p9 r4 L9 Q6 _' |
#define RCC_CKGATENR_AHB2APB1_CKEN ((uint32_t)0x00000001)
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#define RCC_CKGATENR_AHB2APB2_CKEN ((uint32_t)0x00000002)
; f9 d' S* E3 z! B. O. O. e
#define RCC_CKGATENR_CM4DBG_CKEN ((uint32_t)0x00000004)9 I. Q, U" i7 | p
#define RCC_CKGATENR_SPARE_CKEN ((uint32_t)0x00000008)
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#define RCC_CKGATENR_SRAM_CKEN ((uint32_t)0x00000010)& R" h+ }: D1 Q. Y
#define RCC_CKGATENR_FLITF_CKEN ((uint32_t)0x00000020); F( ^- x# [( a+ D8 F( q6 Z q6 K
#define RCC_CKGATENR_RCC_CKEN ((uint32_t)0x00000040)# n$ O6 E. h( H
#if defined(STM32F412xG) || defined(STM32F413_423xx)
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#define RCC_CKGATENR_RCC_EVTCTL ((uint32_t)0x00000080)
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#endif /* STM32F412xG || STM32F413_423xx */
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/******************** Bit definition for RCC_DCKCFGR2 register ***************/$ a# h: g) S5 {
#define RCC_DCKCFGR2_FMPI2C1SEL ((uint32_t)0x00C00000)2 L, }" @$ n" @. @ `- s
#define RCC_DCKCFGR2_FMPI2C1SEL_0 ((uint32_t)0x00400000)1 Y5 u& V0 l: ^" t
#define RCC_DCKCFGR2_FMPI2C1SEL_1 ((uint32_t)0x00800000)
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#define RCC_DCKCFGR2_CECSEL ((uint32_t)0x04000000)
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#define RCC_DCKCFGR2_CK48MSEL ((uint32_t)0x08000000): a5 ]+ T4 z6 r) [* J
#define RCC_DCKCFGR2_SDIOSEL ((uint32_t)0x10000000)
# z( \4 ], e- V3 v# }
#if defined(STM32F446xx)
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#define RCC_DCKCFGR2_SPDIFRXSEL ((uint32_t)0x20000000)
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#endif /* STM32F446xx */: X& \5 V* X8 a' y* x( @
#if defined(STM32F413_423xx)- f, S f4 y( | V2 f- p) ?
#define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0xC0000000)
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#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x40000000)& j8 E0 r9 M1 {( X/ C" y
#define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x80000000)
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#endif /* STM32F413_423xx */
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#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */* B: c+ ?0 {# b7 N( I/ V! k3 i$ B
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#if defined(STM32F410xx)- y E t) f6 D; U" k; p h
#define RCC_DCKCFGR_I2SSRC ((uint32_t)0x06000000)
#define RCC_DCKCFGR_I2SSRC_0 ((uint32_t)0x02000000)
$ p, a/ r; X [% ]* d
#define RCC_DCKCFGR_I2SSRC_1 ((uint32_t)0x04000000)7 a+ k8 w e2 _- p! O7 A+ x) V
#endif /* STM32F410xx */: f3 }, M' M$ n0 L
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#if defined(STM32F410xx)
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/******************** Bit definition for RCC_DCKCFGR2 register **************/
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#define RCC_DCKCFGR2_FMPI2C1SEL ((uint32_t)0x00C00000)0 E6 C' P4 s( w& c! c9 G3 |2 `
#define RCC_DCKCFGR2_FMPI2C1SEL_0 ((uint32_t)0x00400000)
/ { s4 a" J+ {. O9 G& p( P& t
#define RCC_DCKCFGR2_FMPI2C1SEL_1 ((uint32_t)0x00800000)
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#define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0xC0000000)
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#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x40000000)" u) E% S0 e2 z0 @/ c2 z. x
#define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x80000000)
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#endif /* STM32F410xx */4 \3 e/ x4 A! d- ~